ADC Exported Types

ADC Exported Types

group ADC_Exported_Types

Typedefs

typedef struct hal_adc_handle_s hal_adc_handle_t

HAL ADC Handle type definition.

ADC handle type definition

typedef void ( * hal_adc_cb_t ) ( hal_adc_handle_t * hadc )

HAL ADC pointers to callback functions.

pointer to ADC callback function

typedef void ( * hal_adc_awd_cb_t ) ( hal_adc_handle_t * hadc , hal_adc_awd_instance_t awd_instance )

pointer to ADC analog watchdog callback function

Enums

enum hal_adc_t

HAL ADC instance.

Values:

enumerator HAL_ADC1
enumerator HAL_ADC2
enum hal_adc_state_t

ADC global state.

Values:

enumerator HAL_ADC_STATE_RESET

ADC not yet initialized

enumerator HAL_ADC_STATE_INIT

ADC initialized but not yet configured

enumerator HAL_ADC_STATE_CONFIGURING

ADC configuration ongoing (step optional depending on series or ADC instances)

enumerator HAL_ADC_STATE_IDLE

ADC configured and ready to be activated

enumerator HAL_ADC_STATE_ACTIVE

ADC activated, ready to operate (ADC conversions depending on ADC groups state)

enumerator HAL_ADC_STATE_CALIB

ADC calibration ongoing

enum hal_adc_group_state_t

ADC group (regular, injected) state.

Values:

enumerator HAL_ADC_GROUP_STATE_RESET

ADC group not yet initialized

enumerator HAL_ADC_GROUP_STATE_IDLE

ADC group initialized and ready to operate

enumerator HAL_ADC_GROUP_STATE_ACTIVE

ADC group operating (ADC conversion ongoing or can start upon trigger request)

enumerator HAL_ADC_GROUP_STATE_ACTIVE_SILENT

ADC group operating (ADC conversion ongoing or can start upon trigger request) without any interruption

enum hal_adc_common_state_t

HAL ADC handle link to common instance state.

Values:

enumerator HAL_ADC_COMMON_STATE_RESET

HAL ADC handle link to common instance not yet initialized

enumerator HAL_ADC_COMMON_STATE_INDEPT

HAL ADC handle independent (not linked to common instance)

enumerator HAL_ADC_COMMON_STATE_LINKED

HAL ADC handle linked to other handles of common instance

enumerator HAL_ADC_COMMON_STATE_MM

HAL ADC handle linked to other handles of common instance and configured in multimode

enum hal_adc_group_conv_per_start_t

HAL ADC group conversions per conversion start configuration.

Values:

enumerator HAL_ADC_GROUP_CONV_UNIT

HAL ADC group configured to have a unitary (only one) conversion per conversion start

enumerator HAL_ADC_GROUP_CONV_MULTIPLE

HAL ADC group configured to have multiple conversions from one conversion start (for example: continuous mode, trigger from timer, …)

enum hal_adc_resolution_t

HAL ADC resolution.

Values:

enumerator HAL_ADC_RESOLUTION_6_BIT

ADC resolution 6 bit ADC resolution 6 bit

enumerator HAL_ADC_RESOLUTION_8_BIT

ADC resolution 8 bit ADC resolution 8 bit

enumerator HAL_ADC_RESOLUTION_10_BIT

ADC resolution 10 bit ADC resolution 10 bit

enumerator HAL_ADC_RESOLUTION_12_BIT

ADC resolution 12 bit ADC resolution 12 bit

enum hal_adc_left_bit_shift_t

HAL ADC data shift left.

Values:

enumerator HAL_ADC_LEFT_BIT_SHIFT_NONE

ADC conversion data not shifted (alignment right) ADC conversion data not shifted (alignment right, on data register MSB bit 0)

enumerator HAL_ADC_LEFT_BIT_SHIFT_1_BIT

ADC conversion data shift left of 1 bit (data multiplied by 2). ADC conversion data shift left of 1 bit (data multiplied by 2)

enumerator HAL_ADC_LEFT_BIT_SHIFT_2_BITS

ADC conversion data shift left of 2 bits (data multiplied by 4). ADC conversion data shift left of 2 bits (data multiplied by 4)

enumerator HAL_ADC_LEFT_BIT_SHIFT_3_BITS

ADC conversion data shift left of 3 bits (data multiplied by 8). ADC conversion data shift left of 3 bits (data multiplied by 8)

enumerator HAL_ADC_LEFT_BIT_SHIFT_4_BITS

ADC conversion data shift left of 4 bits (data multiplied by 16). ADC conversion data shift left of 4 bits (data multiplied by 16)

enumerator HAL_ADC_LEFT_BIT_SHIFT_5_BITS

ADC conversion data shift left of 5 bits (data multiplied by 32). ADC conversion data shift left of 5 bits (data multiplied by 32)

enumerator HAL_ADC_LEFT_BIT_SHIFT_6_BITS

ADC conversion data shift left of 6 bits (data multiplied by 64). ADC conversion data shift left of 6 bits (data multiplied by 64)

enumerator HAL_ADC_LEFT_BIT_SHIFT_7_BITS

ADC conversion data shift left of 7 bits (data multiplied by 128). ADC conversion data shift left of 7 bits (data multiplied by 128)

enumerator HAL_ADC_LEFT_BIT_SHIFT_8_BITS

ADC conversion data shift left of 8 bits (data multiplied by 256). ADC conversion data shift left of 8 bits (data multiplied by 256)

enumerator HAL_ADC_LEFT_BIT_SHIFT_9_BITS

ADC conversion data shift left of 9 bits (data multiplied by 512). ADC conversion data shift left of 9 bits (data multiplied by 512)

enumerator HAL_ADC_LEFT_BIT_SHIFT_10_BITS

ADC conversion data shift left of 10 bits (data multiplied by 1024). ADC conversion data shift left of 10 bits (data multiplied by 1024)

enumerator HAL_ADC_LEFT_BIT_SHIFT_11_BITS

ADC conversion data shift left of 11 bits (data multiplied by 2048). ADC conversion data shift left of 11 bits (data multiplied by 2048)

enumerator HAL_ADC_LEFT_BIT_SHIFT_12_BITS

ADC conversion data shift left of 12 bits (data multiplied by 4096). ADC conversion data shift left of 12 bits (data multiplied by 4096)

enumerator HAL_ADC_LEFT_BIT_SHIFT_13_BITS

ADC conversion data shift left of 13 bits (data multiplied by 8192). ADC conversion data shift left of 13 bits (data multiplied by 8192)

enumerator HAL_ADC_LEFT_BIT_SHIFT_14_BITS

ADC conversion data shift left of 14 bits (data multiplied by 16384). ADC conversion data shift left of 14 bits (data multiplied by 16384)

enumerator HAL_ADC_LEFT_BIT_SHIFT_15_BITS

ADC conversion data shift left of 15 bits (data multiplied by 32768). ADC conversion data shift left of 15 bits (data multiplied by 32768)

enum hal_adc_lp_auto_wait_state_t

HAL ADC low power feature auto wait.

Values:

enumerator HAL_ADC_LP_AUTO_WAIT_DISABLE

No ADC low power mode activated ADC low power mode auto delay disabled.

enumerator HAL_ADC_LP_AUTO_WAIT_ENABLE

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode(). ADC low power mode auto delay enabled: dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). Refer to detailed description of function LL_ADC_SetLPModeAutoWait().

enum hal_adc_sampling_mode_t

HAL ADC sampling mode.

Values:

enumerator HAL_ADC_SAMPLING_MODE_NORMAL

ADC conversions sampling phase duration is defined using Channel - Sampling time. ADC conversions sampling phase duration is defined using hal_adc_sampling_time_t.

enumerator HAL_ADC_SAMPLING_MODE_BULB

ADC conversions sampling phase starts immediately after end of conversion, stops upon trigger event. Note: first conversion is using minimal sampling time (see Channel - Sampling time). Note: Usable only if conversions from ADC group regular (not ADC group injected) and not in continuous mode. ADC conversions sampling phase starts immediately after end of conversion, stops upon trigger event. Note: First conversion is using minimal sampling time (refer to hal_adc_sampling_time_t). Note: Usable only if conversions from ADC group regular (not ADC group injected) and not in continuous mode.

enumerator HAL_ADC_SAMPLING_MODE_TRIGGER_CTRL

ADC conversions sampling phase is controlled by trigger events: trigger rising edge starts sampling, trigger falling edge stops sampling and start conversion. Note: Usable only if conversions from ADC group regular (not ADC group injected) and not in continuous mode. ADC conversions sampling phase by trigger events: trigger rising edge starts sampling, trigger falling edge stops sampling and start conversion. Note: Usable only if conversions from ADC group regular (not ADC group injected) and not in continuous mode.

enum hal_adc_group_t

HAL ADC groups.

Values:

enumerator HAL_ADC_GROUP_REGULAR

ADC group regular (available on all STM32 devices) ADC group regular

enumerator HAL_ADC_GROUP_INJECTED

ADC group injected (not available on all STM32 devices) ADC group injected

enumerator HAL_ADC_GROUP_REGULAR_INJECTED

ADC both groups regular and injected ADC both groups regular and injected (usable only by specific functions: analog watchdog configuration)

enumerator HAL_ADC_GROUP_NONE

ADC group none ADC group none. Note: Can be used to remove a channel from analog watchdog monitoring.

enum hal_adc_reg_trig_src_t

HAL ADC group regular conversion trigger source.

Values:

enumerator HAL_ADC_REG_TRIG_SOFTWARE

ADC group regular conversion trigger internal: SW start. ADC group regular conversion trigger from software start

enumerator HAL_ADC_REG_TRIG_EXTI11

ADC group regular conversion trigger from periph: EXTI line 11 ADC group regular conversion trigger from periph: EXTI line 11

enumerator HAL_ADC_REG_TRIG_TIM1_OC1

ADC group regular conversion trigger from periph: TIM1 channel 1 ADC group regular conversion trigger from periph: TIM1 channel 1.

enumerator HAL_ADC_REG_TRIG_TIM1_OC2

ADC group regular conversion trigger from periph: TIM1 channel 2 ADC group regular conversion trigger from periph: TIM1 channel 2.

enumerator HAL_ADC_REG_TRIG_TIM1_OC3

ADC group regular conversion trigger from periph: TIM1 channel 3 ADC group regular conversion trigger from periph: TIM1 channel 3.

enumerator HAL_ADC_REG_TRIG_TIM1_TRGO

ADC group regular conversion trigger from periph: TIM1 TRGO ADC group regular conversion trigger from periph: TIM1 TRGO

enumerator HAL_ADC_REG_TRIG_TIM1_TRGO2

ADC group regular conversion trigger from periph: TIM1 TRGO2 ADC group regular conversion trigger from periph: TIM1 TRGO2

enumerator HAL_ADC_REG_TRIG_TIM2_OC2

ADC group regular conversion trigger from periph: TIM2 channel 2 ADC group regular conversion trigger from periph: TIM2 channel 2.

enumerator HAL_ADC_REG_TRIG_TIM2_TRGO

ADC group regular conversion trigger from periph: TIM2 TRGO ADC group regular conversion trigger from periph: TIM2 TRGO

enumerator HAL_ADC_REG_TRIG_TIM5_OC4

ADC group regular conversion trigger from periph: TIM5 channel 4 ADC group regular conversion trigger from periph: TIM5 channel 4.

enumerator HAL_ADC_REG_TRIG_TIM5_TRGO

ADC group regular conversion trigger from periph: TIM15 TRGO ADC group regular conversion trigger from periph: TIM5 TRGO

enumerator HAL_ADC_REG_TRIG_TIM6_TRGO

ADC group regular conversion trigger from periph: TIM6 TRGO ADC group regular conversion trigger from periph: TIM6 TRGO

enumerator HAL_ADC_REG_TRIG_TIM8_TRGO

ADC group regular conversion trigger from periph: TIM8 TRGO ADC group regular conversion trigger from periph: TIM8 TRGO

enumerator HAL_ADC_REG_TRIG_TIM8_TRGO2

ADC group regular conversion trigger from periph: TIM8 TRGO2 ADC group regular conversion trigger from periph: TIM8 TRGO2

enumerator HAL_ADC_REG_TRIG_TIM15_TRGO

ADC group regular conversion trigger from periph: TIM15 TRGO ADC group regular conversion trigger from periph: TIM15 TRGO

enumerator HAL_ADC_REG_TRIG_LPTIM1_OC1

ADC group regular conversion trigger from periph: LPTIM1 channel 1 ADC group regular conversion trigger from periph: LPTIM1 channel 1.

enum hal_adc_reg_trig_edge_t

HAL ADC group regular conversion trigger edge.

Values:

enumerator HAL_ADC_REG_TRIG_EDGE_NONE

ADC group regular conversion trigger disabled (SW start)

enumerator HAL_ADC_REG_TRIG_EDGE_RISING

ADC group regular conversion trigger polarity set to rising edge ADC group regular conversion trigger polarity set to rising edge

enumerator HAL_ADC_REG_TRIG_EDGE_FALLING

ADC group regular conversion trigger polarity set to falling edge ADC group regular conversion trigger polarity set to falling edge

enumerator HAL_ADC_REG_TRIG_EDGE_RISING_FALLING

ADC group regular conversion trigger polarity set to both rising and falling edges ADC group regular conversion trigger polarity set to both rising and falling edges

enum hal_adc_reg_seq_discont_length_t

HAL ADC group regular sequencer scan discontinuous length.

Values:

enumerator HAL_ADC_REG_SEQ_DISCONT_DISABLE

ADC group regular sequencer discontinuous mode disabled ADC group regular sequencer discontinuous mode disabled

enumerator HAL_ADC_REG_SEQ_DISCONT_1RANK

ADC group regular sequencer discontinuous mode enabled with sequence interruption every rank ADC group regular sequencer discontinuous mode enabled with sequence interruption every rank

enumerator HAL_ADC_REG_SEQ_DISCONT_2RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks.

enumerator HAL_ADC_REG_SEQ_DISCONT_3RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 3 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 3 ranks.

enumerator HAL_ADC_REG_SEQ_DISCONT_4RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 4 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 4 ranks.

enumerator HAL_ADC_REG_SEQ_DISCONT_5RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 5 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 5 ranks.

enumerator HAL_ADC_REG_SEQ_DISCONT_6RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 6 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 6 ranks.

enumerator HAL_ADC_REG_SEQ_DISCONT_7RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 7 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 7 ranks.

enumerator HAL_ADC_REG_SEQ_DISCONT_8RANKS

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 8 ranks ADC group regular sequencer discontinuous mode enabled with sequence interruption every 8 ranks.

enum hal_adc_reg_continuous_mode_t

HAL ADC group regular continuous mode.

Values:

enumerator HAL_ADC_REG_CONV_SINGLE

ADC conversions performed in single mode: conversions start from a trigger, are performed for each channel of the sequence, then stop. ADC conversions performed in single mode: conversions start from a trigger, are performed for each channel of the sequence, then stop.

enumerator HAL_ADC_REG_CONV_CONTINUOUS

ADC conversions performed in continuous mode: conversions start from a trigger, are performed for each channel of the sequence, then restart automatically. ADC conversions performed in continuous mode: conversions start from a trigger, are performed for each channel of the sequence, then restart automatically.

enum hal_adc_reg_overrun_mode_t

HAL ADC group regular overrun mode.

Note

Overrun occurs when conversion is completed while conversion data in data register (from previous conversion) has not been fetched (by CPU or DMA).

Values:

enumerator HAL_ADC_REG_OVR_DATA_PRESERVED

ADC group regular behavior in case of overrun: data preserved. Note: an internal FIFO of 8 elements in enabled in this mode. Overrun occurs when the FIFO overflows. FIFO is emptied by successive reads of data register. ADC group regular behavior in case of overrun: data preserved. Note: an internal FIFO of 8 elements is enabled in this mode. Overrun occurs when the FIFO overflows. FIFO is emptied by successive reads of data register.

enumerator HAL_ADC_REG_OVR_DATA_OVERWRITTEN

ADC group regular behavior in case of overrun: data overwritten ADC group regular behavior in case of overrun: data overwritten

enum hal_adc_inj_trig_src_t

HAL ADC group injected conversion trigger source.

Values:

enumerator HAL_ADC_INJ_TRIG_SOFTWARE

ADC group injected conversion trigger internal: SW start. ADC group injected conversion trigger from software start

enumerator HAL_ADC_INJ_TRIG_EXTI15

ADC group injected conversion trigger from periph: EXTI line 15 ADC group injected conversion trigger from external peripheral: EXTI line 15.

enumerator HAL_ADC_INJ_TRIG_TIM1_OC4

ADC group injected conversion trigger from periph: TIM1 channel 4 ADC group injected conversion trigger from external peripheral: TIM1 channel 4 .

enumerator HAL_ADC_INJ_TRIG_TIM1_TRGO

ADC group injected conversion trigger from periph: TIM1 TRGO ADC group injected conversion trigger from external peripheral: TIM1 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM1_TRGO2

ADC group injected conversion trigger from periph: TIM1 TRGO2 ADC group injected conversion trigger from external peripheral: TIM1 TRGO2

enumerator HAL_ADC_INJ_TRIG_TIM2_OC1

ADC group injected conversion trigger from periph: TIM2 channel 1 ADC group injected conversion trigger from external peripheral: TIM2 channel 1 .

enumerator HAL_ADC_INJ_TRIG_TIM2_TRGO

ADC group injected conversion trigger from periph: TIM2 TRGO ADC group injected conversion trigger from external peripheral: TIM2 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM5_OC1

ADC group injected conversion trigger from periph: TIM5 channel 1 ADC group injected conversion trigger from external peripheral: TIM5 channel 1 .

enumerator HAL_ADC_INJ_TRIG_TIM5_OC2

ADC group injected conversion trigger from periph: TIM5 channel 2 ADC group injected conversion trigger from external peripheral: TIM5 channel 2 .

enumerator HAL_ADC_INJ_TRIG_TIM5_OC3

ADC group injected conversion trigger from periph: TIM5 channel 3 ADC group injected conversion trigger from external peripheral: TIM5 channel 3 .

enumerator HAL_ADC_INJ_TRIG_TIM5_TRGO

ADC group injected conversion trigger from periph: TIM15 TRGO ADC group injected conversion trigger from external peripheral: TIM5 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM7_TRGO

ADC group injected conversion trigger from periph: TIM7 TRGO ADC group injected conversion trigger from external peripheral: TIM7 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM8_OC4

ADC group injected conversion trigger from periph: TIM8 channel 4 ADC group injected conversion trigger from external peripheral: TIM8 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM8_TRGO

ADC group injected conversion trigger from periph: TIM8 TRGO ADC group injected conversion trigger from external peripheral: TIM8 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM8_TRGO2

ADC group injected conversion trigger from periph: TIM8 TRGO2 ADC group injected conversion trigger from external peripheral: TIM8 TRGO2

enumerator HAL_ADC_INJ_TRIG_TIM12_TRGO

ADC group injected conversion trigger from periph: TIM12 TRGO ADC group injected conversion trigger from external peripheral: TIM12 TRGO

enumerator HAL_ADC_INJ_TRIG_TIM15_TRGO

ADC group injected conversion trigger from periph: TIM15 TRGO ADC group injected conversion trigger from external peripheral: TIM15 TRGO

enumerator HAL_ADC_INJ_TRIG_LPTIM1_OC1

ADC group injected conversion trigger from periph: LPTIM1 channel 1 ADC group injected conversion trigger from external peripheral: LPTIM1 channel 1

enumerator HAL_ADC_INJ_TRIG_FROM_REGULAR

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. ADC group injected conversion trigger from ADC group regular end of sequence (no action ADC group injected conversion start or stop). Intended usage: extend ADC group regular sequencer length.

enum hal_adc_inj_trig_edge_t

HAL ADC group injected conversion trigger edge.

Values:

enumerator HAL_ADC_INJ_TRIG_EDGE_NONE

ADC group injected conversion trigger disabled (SW start)

enumerator HAL_ADC_INJ_TRIG_EDGE_RISING

ADC group injected conversion trigger polarity set to rising edge ADC group injected conversion trigger polarity set to rising edge

enumerator HAL_ADC_INJ_TRIG_EDGE_FALLING

ADC group injected conversion trigger polarity set to falling edge ADC group injected conversion trigger polarity set to falling edge

enumerator HAL_ADC_INJ_TRIG_EDGE_RISING_FALLING

ADC group injected conversion trigger polarity set to both rising and falling edges ADC group injected conversion trigger polarity set to both rising and falling edges

enum hal_adc_inj_seq_discont_length_t

HAL ADC group injected sequencer scan discontinuous length.

Values:

enumerator HAL_ADC_INJ_SEQ_DISCONT_DISABLE

ADC group injected sequencer discontinuous mode disabled ADC group injected sequencer discontinuous mode disabled

enumerator HAL_ADC_INJ_SEQ_DISCONT_1RANK

ADC group injected sequencer discontinuous mode enabled with sequence interruption every rank ADC group injected sequencer discontinuous mode enabled with sequence interruption every rank

enum hal_adc_channel_t

HAL ADC channel.

Values:

enumerator HAL_ADC_CHANNEL_0

Channel ADCx_IN0 ADC channel to GPIO pin ADCx_IN0

enumerator HAL_ADC_CHANNEL_1

Channel ADCx_IN1 ADC channel to GPIO pin ADCx_IN1

enumerator HAL_ADC_CHANNEL_2

Channel ADCx_IN2 ADC channel to GPIO pin ADCx_IN2

enumerator HAL_ADC_CHANNEL_3

Channel ADCx_IN3 ADC channel to GPIO pin ADCx_IN3

enumerator HAL_ADC_CHANNEL_4

Channel ADCx_IN4 ADC channel to GPIO pin ADCx_IN4

enumerator HAL_ADC_CHANNEL_5

Channel ADCx_IN5 ADC channel to GPIO pin ADCx_IN5

enumerator HAL_ADC_CHANNEL_6

Channel ADCx_IN6 ADC channel to GPIO pin ADCx_IN6

enumerator HAL_ADC_CHANNEL_7

Channel ADCx_IN7 ADC channel to GPIO pin ADCx_IN7

enumerator HAL_ADC_CHANNEL_8

Channel ADCx_IN8 ADC channel to GPIO pin ADCx_IN8

enumerator HAL_ADC_CHANNEL_9

Channel ADCx_IN9 ADC channel to GPIO pin ADCx_IN9

enumerator HAL_ADC_CHANNEL_10

Channel ADCx_IN10 ADC channel to GPIO pin ADCx_IN10

enumerator HAL_ADC_CHANNEL_11

Channel ADCx_IN11 ADC channel to GPIO pin ADCx_IN11

enumerator HAL_ADC_CHANNEL_12

Channel ADCx_IN12 ADC channel to GPIO pin ADCx_IN12

enumerator HAL_ADC_CHANNEL_13

Channel ADCx_IN13 ADC channel to GPIO pin ADCx_IN13

enumerator HAL_ADC_CHANNEL_VREFINT

ADC channel to VrefInt (internal voltage reference). ADC channel to VrefInt (internal voltage reference)

enumerator HAL_ADC_CHANNEL_TEMPSENSOR

ADC internal channel ADC channel to internal temperature sensor.

enumerator HAL_ADC_CHANNEL_NONE

ADC no channel No ADC channel selected (usable only by specific functions: analog watchdog configuration)

enumerator HAL_ADC_CHANNEL_ALL

ADC all channels All ADC channels selected (usable only by specific functions: analog watchdog configuration)

enum hal_adc_sampling_time_t

HAL ADC sampling time (channel wise)

Values:

enumerator HAL_ADC_SAMPLING_TIME_3CYCLES

Sampling time 3 ADC clock cycles Sampling time 3 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_5CYCLES

Sampling time 5 ADC clock cycles Sampling time 5 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_8CYCLES

Sampling time 8 ADC clock cycles Sampling time 8 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_13CYCLES

Sampling time 13 ADC clock cycles Sampling time 13 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_25CYCLES

Sampling time 25 ADC clock cycles Sampling time 25 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_48CYCLES

Sampling time 48 ADC clock cycles Sampling time 45 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_139CYCLES

Sampling time 139 ADC clock cycles Sampling time 139 ADC clock cycles

enumerator HAL_ADC_SAMPLING_TIME_289CYCLES

Sampling time 289 ADC clock cycles Sampling time 289 ADC clock cycles

enum hal_adc_in_mode_t

HAL ADC channel input mode (single, differential ended)

Values:

enumerator HAL_ADC_IN_SINGLE_ENDED

ADC channel input set to single ended (literal also used to set calibration mode) ADC channel input set to single-ended

enum hal_adc_awd_instance_t

HAL ADC analog watchdog instance.

Note

Analog watchdog instances specificities:

  • AWD standard (instance AWD1):

    • channels monitored: can monitor 1 channel or all channels.

    • groups monitored: ADC groups regular and-or injected.

    • resolution: resolution is not limited (corresponds to ADC resolution configured).

  • AWD flexible (instances AWD2, AWD3):

    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels.

    • groups monitored: no selection possible (monitoring on both groups regular and injected).

Values:

enumerator HAL_ADC_AWD_1

ADC analog watchdog instance 1 ADC analog watchdog number 1

enumerator HAL_ADC_AWD_2

ADC analog watchdog instance 2 ADC analog watchdog number 2

enumerator HAL_ADC_AWD_3

ADC analog watchdog instance 3 ADC analog watchdog number 3

enum hal_adc_awd_threshold_sel_t

HAL ADC analog watchdog threshold selection.

Values:

enumerator HAL_ADC_AWD_THRESHOLD_HIGH

ADC analog watchdog threshold high ADC analog watchdog threshold high

enumerator HAL_ADC_AWD_THRESHOLD_LOW

ADC analog watchdog threshold low ADC analog watchdog threshold low

enum hal_adc_awd_filtering_t

HAL ADC analog watchdog filtering.

Values:

enumerator HAL_ADC_AWD_FILTERING_NONE

ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt ADC analog watchdog no filtering, one out-of-window sample triggers flag raise

enumerator HAL_ADC_AWD_FILTERING_2SAMPLES

ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 2 consecutives out-of-window samples trigger flag raise

enumerator HAL_ADC_AWD_FILTERING_3SAMPLES

ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 3 consecutives out-of-window samples trigger flag raise

enumerator HAL_ADC_AWD_FILTERING_4SAMPLES

ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 4 consecutives out-of-window samples trigger flag raise

enumerator HAL_ADC_AWD_FILTERING_5SAMPLES

ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 5 consecutives out-of-window samples trigger flag raise

enumerator HAL_ADC_AWD_FILTERING_6SAMPLES

ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 6 consecutives out-of-window samples trigger flag raise

enumerator HAL_ADC_AWD_FILTERING_7SAMPLES

ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 7 consecutives out-of-window samples trigger flag raise

enumerator HAL_ADC_AWD_FILTERING_8SAMPLES

ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt ADC analog watchdog 8 consecutives out-of-window samples trigger flag raise

enum hal_adc_ovs_instance_t

HAL ADC oversampling instance.

Values:

enumerator HAL_ADC_OVS_1

ADC oversampling instance for standard oversampling: a single oversampling accumulator is common to regular and injected conversions. Therefore, settings ratio and shift are common and process is sequential. For constraints of oversampling on groups regular and injected, refer to parameters of ADC_LL_EC_OVS_SCOPE. ADC oversampling instance for standard oversampling: a single oversampling accumulator is common to regular and injected conversions. Therefore, settings ratio and shift are common and process is sequential. For constraints of oversampling on groups regular and injected, refer to parameters of hal_adc_ovs_scope_t.

enum hal_adc_ovs_scope_t

HAL ADC oversampling scope.

Values:

enumerator HAL_ADC_OVS_DISABLE

ADC oversampling disabled. ADC oversampling disabled.

enumerator HAL_ADC_OVS_REG_CONTINUED

ADC oversampling on conversions of ADC group regular. If ADC group injected conversion insertion within regular sequence: oversampling on group regular is temporary stopped and, after injected conversion, continued (oversampling accumulator maintained). ADC oversampling on conversions of ADC group regular. If ADC group injected conversion insertion within regular sequence: oversampling on group regular is temporary stopped and, after injected conversion, continued (oversampling accumulator maintained).

enumerator HAL_ADC_OVS_REG_RESUMED

ADC oversampling on conversions of ADC group regular. If ADC group injected conversion insertion within regular sequence: after injected conversion, oversampling on group regular is resumed from start (oversampler accumulator reset). ADC oversampling on conversions of ADC group regular. If ADC group injected conversion insertion within regular sequence: after injected conversion, oversampling on group regular is resumed from start (oversampler accumulator reset).

enumerator HAL_ADC_OVS_INJ

ADC oversampling on conversions of ADC group injected, in sequential mode: oversampling conversions sequence sequential, switching data registers after each oversampling process (all ratio occurrences, shift). Note: A single oversampling accumulator is common to regular and injected conversions. Therefore, settings ratio and shift are common and process is sequential. ADC oversampling on conversions of ADC group injected, in sequential mode: oversampling conversions sequence sequential, switching data registers after each oversampling process (all ratio occurrences, shift). Note: A single oversampling accumulator is common to regular and injected conversions. Therefore, settings ratio and shift are common and process is sequential.

enumerator HAL_ADC_OVS_INJ_REG_RESUMED

ADC oversampling on conversions of ADC groups regular and injected. Combination of LL_ADC_OVS_REG_RESUMED and LL_ADC_OVS_INJ: refer to description of these parameters. Note: Can be used only with function LL_ADC_SetOverSamplingScope(). For configuration with accumulator explicit selection, refer to LL_ADC_SetOverSamplingInstScope(), used with combination of regular and injected related parameters. ADC oversampling on conversions of ADC groups regular and injected. Combination of LL_ADC_OVS_REG_RESUMED and LL_ADC_OVS_INJ: refer to description of these parameters.

enum hal_adc_ovs_discont_t

HAL ADC oversampling discontinuous mode.

Values:

enumerator HAL_ADC_OVS_CONT

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio start from 1 trigger) ADC oversampling discontinuous mode: continuous (all conversions of oversampling ratio start from 1 trigger)

enumerator HAL_ADC_OVS_DISCONT

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) Note: Discontinuous mode applied only on group regular oversampling (not injected oversampling). ADC oversampling discontinuous mode: discontinuous (each conversion of oversampling ratio needs a trigger). Note: Discontinuous mode applied only on group regular oversampling (not injected oversampling).

enum hal_adc_offset_instance_t

HAL ADC offset instance.

Values:

enumerator HAL_ADC_OFFSET_1

ADC offset instance 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer) ADC offset instance 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

enumerator HAL_ADC_OFFSET_2

ADC offset instance 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer) ADC offset instance 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

enumerator HAL_ADC_OFFSET_3

ADC offset instance 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer) ADC offset instance 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

enumerator HAL_ADC_OFFSET_4

ADC offset instance 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer) ADC offset instance 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

enum hal_adc_offset_sat_sign_state_t

HAL ADC offset signed saturation.

Values:

enumerator HAL_ADC_OFFSET_SAT_SIGNED_DISABLE

ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) ADC offset signed saturation disabled

enumerator HAL_ADC_OFFSET_SAT_SIGNED_ENABLE

ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) ADC offset signed saturation enabled

enum hal_adc_offset_sat_unsign_state_t

HAL ADC offset unsigned saturation.

Values:

enumerator HAL_ADC_OFFSET_SAT_UNSIGNED_DISABLE

ADC offset unsigned saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) ADC offset unsigned saturation disabled

enumerator HAL_ADC_OFFSET_SAT_UNSIGNED_ENABLE

ADC offset unsigned saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) ADC offset unsigned saturation enabled

enum hal_adc_mm_inst_t

HAL ADC multimode - Instances.

Values:

enumerator HAL_ADC_MM_MASTER

In multimode, selection among several ADC instances: ADC master Multimode ADC instance selection: ADC master

enumerator HAL_ADC_MM_SLAVE

In multimode, selection among several ADC instances: ADC slave Multimode ADC instance selection: ADC slave

enumerator HAL_ADC_MM_MASTER_SLAVE

In multimode, selection among several ADC instances: both ADC master and ADC slave Multimode ADC instance selection: both ADC master and ADC slave

enum hal_adc_mm_mode_t

HAL ADC multimode - Mode.

Values:

enumerator HAL_ADC_MM_INDEPENDENT

ADC dual mode disabled (ADC independent mode) ADC dual mode disabled (ADC independent mode)

enumerator HAL_ADC_MM_DUAL_REG_SIMULT

ADC dual mode enabled: group regular simultaneous ADC dual mode group regular simultaneous

enumerator HAL_ADC_MM_DUAL_REG_INTERL

ADC dual mode enabled: Combined group regular interleaved ADC dual mode group regular interleaved

enumerator HAL_ADC_MM_DUAL_INJ_SIMULT

ADC dual mode enabled: group injected simultaneous ADC dual mode group injected simultaneous

enumerator HAL_ADC_MM_DUAL_INJ_ALTERN

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not SW start) ADC dual mode group injected alternate trigger. Works only with external triggers (not SW start)

enumerator HAL_ADC_MM_DUAL_REG_SIM_INJ_SIM

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous ADC dual mode combined group regular simultaneous + group injected simultaneous

enumerator HAL_ADC_MM_DUAL_REG_SIM_INJ_ALT

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger ADC dual mode combined group regular simultaneous + group injected alternate trigger

enumerator HAL_ADC_MM_DUAL_REG_INT_INJ_SIM

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous ADC dual mode combined group regular interleaved + group injected simultaneous

enum hal_adc_mm_reg_data_format_t

HAL ADC multimode - Data format.

Values:

enumerator HAL_ADC_MM_REG_DATA_EACH_ADC

ADC multimode group regular data format: full range, no data packing. Intended for cases: - multimode without DMA transfer - multimode with DMA transfer in two different buffers. - high data width (can exceed ADC resolution in case of oversampling or post-processing) over data packing constraints. For no data transfer: - to retrieve conversion data, use LL_ADC_REG_ReadConversionData32() with each ADC instance. For data transfer by DMA: - configure DMA to get data from register DR of ADC instance with LL_ADC_DMA_GetRegAddr(). Each ADC uses its own DMA channel, with its individual DMA transfer settings. Therefore, two destination buffers. ADC multimode group regular data format: full range, no data packing. Intended for cases:

  • multimode without DMA transfer

  • multimode with DMA transfer in two different buffers.

  • high data width (can exceed ADC resolution in case of oversampling or post-processing: offset, …) over data packing constraints. For no data transfer:

  • to retrieve conversion data, use HAL_ADC_REG_ReadConversionData() with each ADC instance. For data transfer by DMA:

  • use function HAL_ADC_MM_REG_StartConvM_DMA(). Each ADC uses its own DMA channel, with its individual DMA transfer settings. Therefore, two destination buffers.

enumerator HAL_ADC_MM_REG_DATA_PACK_32_BITS

ADC multimode group regular data format: full range and 2 data packing on 32 bits. Intended for cases: - multimode with DMA transfer in a single buffer. - high data width (can exceed ADC resolution in case of oversampling or post-processing) over data packing constraints. For no data transfer: - to retrieve conversion data, use LL_ADC_REG_ReadMultiConversionData32() or LL_ADC_REG_ReadConversionData32() with each ADC instance. For data transfer by DMA: - configure DMA to get data from register CDR or CDR2 with LL_ADC_DMA_GetRegAddr(). Note: conversion data in two ADC common instance data registers (CDR, CDR2) with packing option on 32 bits. - Register CDR: data packing on 32 bits: ADC master and slave data are concatenated (data master in [15; 0], data slave in [31; 16]), therefore data width must be lower than 16 bits (can exceed ADC resolution with post-processing: oversampling, offset, …). - Register CDR2: data of master and slave are alternatively set in full register width 32 bits, therefore no constraint on data width. In case of usage with DMA, CDR generates one transfer request and CDR2 two transfer requests per conversion. ADC multimode group regular data format: full range (no packing) and 2 data packing on 32 bits. Intended for cases:

enumerator HAL_ADC_MM_REG_DATA_PACK_16_BITS

ADC multimode group regular data format: full range and 2 data packing on 16 bits. Intended for cases: - multimode with DMA transfer in a single buffer with elements 16 bits. For no data transfer: - to retrieve conversion data, use LL_ADC_REG_ReadConversionData32() with each ADC instance. For data transfer by DMA: - configure DMA to get data from register CDR or CDR2 with LL_ADC_DMA_GetRegAddr(). Note: conversion data in two ADC common instance data registers (CDR, CDR2) with packing option on 16 bits. - Register CDR: data packing on 16 bits: ADC master and slave data are concatenated (data master in [7; 0], data slave in [15; 8]), therefore data width must be lower than 8 bits (can exceed ADC resolution with post-processing: oversampling, offset, …). - Register CDR2: data of master and slave are alternatively set in full register width 32 bits, therefore no constraint on data width. In case of usage with DMA, CDR generates one transfer request and CDR2 two transfer requests per conversion. ADC multimode group regular data format: full range (no packing) and 2 data packing on 16 bits. Intended for cases:

  • multimode with DMA transfer in a single buffer with elements 16 bits. For no data transfer:

  • to retrieve conversion data, use HAL_ADC_REG_ReadConversionData() with each ADC instance. For data transfer by DMA:

  • with data packing on 16 bits: ADC master and slave data are concatenated (data master in [7; 0], data slave in [15; 8]), therefore data width must be lower than 8 bits. Use parameter hal_adc_mm_reg_data_transfer_pack_t value HAL_ADC_MM_REG_DATA_TRANSFER_PACK.

  • with no data packing: same as setting HAL_ADC_MM_REG_DATA_PACK_32_BITS.

enum hal_adc_mm_reg_data_transfer_pack_t

HAL ADC multimode - Data transfer.

Values:

enumerator HAL_ADC_MM_REG_DATA_TRANSFER_PACK

ADC multimode group regular data transfer by DMA with packing: data transfer is performed every 2 conversions of ADC instances part of multimode. Therefore, for dual mode, destination buffer each element is composed of data from ADC master and ADC slave concatenated (buffer size equal to size of each ADC expected number of conversions). Concatenation format: refer to hal_adc_mm_reg_data_format_t. Benefit: Number of DMA requests reduced. Limitation: Setting not compliant with all data width (can exceed ADC resolution in case of oversampling or post-processing: offset, …).

enumerator HAL_ADC_MM_REG_DATA_TRANSFER_UNPACK

ADC multimode group regular data transfer by DMA without packing: data transfer is performed for each conversion of ADC instances part of multimode. Therefore, for dual mode, destination buffer each element is composed alternatively of data from ADC master and ADC slave (buffer size must be twice the size of each ADC expected number of conversions). Benefit: Setting compliant with all data width (can exceed ADC resolution in case of oversampling or post-processing: offset, …).

enum hal_adc_mm_interl_delay_t

HAL ADC multimode - Delay between two sampling phases (for mode interleaved)

Values:

enumerator HAL_ADC_MM_INTERL_DELAY_1CYCLE

ADC multimode (mode interleaved) delay between two sampling phases: 1 ADC clock cycle for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 1 ADC clock cycle for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_2CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 2 ADC clock cycles for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 2 ADC clock cycles for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_3CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 3 ADC clock cycles for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 3 ADC clock cycles for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_4CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 4 ADC clock cycles for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 4 ADC clock cycles for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_5CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 5 ADC clock cycles for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 5 ADC clock cycles for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_6CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 6 ADC clock cycles for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 6 ADC clock cycles for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_7CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 7 ADC clock cycles for all resolutions ADC multimode (mode interleaved) delay between two sampling phases: 7 ADC clock cycles for all resolutions

enumerator HAL_ADC_MM_INTERL_DELAY_8CYCLES

ADC multimode (mode interleaved delay between two sampling phases: 8 ADC clock cycles for resolution 12, 10, 8 bit ADC multimode (mode interleaved) delay between two sampling phases: 8 ADC clock cycles for resolutions 12, 10, 8 bit

enumerator HAL_ADC_MM_INTERL_DELAY_9CYCLES

ADC multimode (mode interleaved delay between two sampling phases: 9 ADC clock cycles for resolution 12, 10, 8 bit ADC multimode (mode interleaved) delay between two sampling phases: 9 ADC clock cycles for resolutions 12, 10, 8 bit

enumerator HAL_ADC_MM_INTERL_DELAY_10CYCLES

ADC multimode (mode interleaved delay between two sampling phases: 10 ADC clock cycles for resolution 12, 10 bit ADC multimode (mode interleaved) delay between two sampling phases: 10 ADC clock cycles for resolutions 12, 10 bit

enumerator HAL_ADC_MM_INTERL_DELAY_11CYCLES

ADC multimode (mode interleaved delay between two sampling phases: 11 ADC clock cycles for resolution 12, 10 bit ADC multimode (mode interleaved) delay between two sampling phases: 11 ADC clock cycles for resolutions 12, 10 bit

enumerator HAL_ADC_MM_INTERL_DELAY_12CYCLES

ADC multimode (mode interleaved delay between two sampling phases: 12 ADC clock cycles for resolution 12 bit ADC multimode (mode interleaved) delay between two sampling phases: 12 ADC clock cycles for resolution 12 bit

enumerator HAL_ADC_MM_INTERL_DELAY_13CYCLES

ADC multimode (mode interleaved) delay between two sampling phases: 13 ADC clock cycles for resolution 12 bit ADC multimode (mode interleaved) delay between two sampling phases: 13 ADC clock cycles for resolution 12 bit

enum hal_adc_event_t

HAL ADC events.

Values:

enumerator HAL_ADC_EVENT_EOC

0x00000004 End of conversion flag ADC flag group regular end of unitary conversion ADC event group regular end of unitary conversion

enumerator HAL_ADC_EVENT_EOS

0x00000008 End of regular sequence flag ADC flag group regular end of sequence conversions ADC event group regular end of sequence conversions

enumerator HAL_ADC_EVENT_OVR

0x00000010 ADC overrun ADC flag group regular overrun ADC event group regular overrun

enumerator HAL_ADC_EVENT_EOSMP

0x00000002 End of sampling flag ADC flag group regular end of sampling phase ADC event group regular end of sampling phase

enumerator HAL_ADC_EVENT_JEOC

0x00000020 Injected channel end of conversion flag ADC flag group injected end of unitary conversion ADC event group injected end of unitary conversion

enumerator HAL_ADC_EVENT_JEOS

0x00000040 Injected channel end of sequence flag ADC flag group injected end of sequence conversions ADC event group injected end of sequence conversions

enumerator HAL_ADC_EVENT_AWD_1

0x00000080 Analog watchdog 1 flag ADC flag analog watchdog 1 out of window event ADC event analog watchdog 1

enumerator HAL_ADC_EVENT_AWD_2

0x00000100 Analog watchdog 2 flag ADC flag analog watchdog 2 out of window event ADC event analog watchdog 2

enumerator HAL_ADC_EVENT_AWD_3

0x00000200 Analog watchdog 3 flag ADC flag analog watchdog 3 out of window event ADC event analog watchdog 3

struct hal_adc_config_t
#include <stm32c5xx_hal_adc.h>

ADC instance configuration.

Public Members

hal_adc_resolution_t resolution

ADC resolution

hal_adc_sampling_mode_t sampling_mode

ADC sampling mode

struct hal_adc_post_processing_config_t
#include <stm32c5xx_hal_adc.h>

ADC instance configuration advanced: conversion data post processing.

Public Members

hal_adc_left_bit_shift_t left_bit_shift

ADC data post-processing: left bit shift for ADC groups regular and injected conversions.

uint32_t gain_compensation_x1000

ADC data post-processing: ADC gain coefficient applied to raw conversions data. Value multiplied by 1000 to have an integer value (example: to set coefficient 0.982, parameter value must be 982). Therefore, unitary gain corresponds to value 1000. Can be a number between: Min_Data = 0, Max_Data = 3999. Note: Coefficient resolution managed by ADC peripheral is higher than 1/1000, if needed to reach more accurate resolution, refer to function LL_ADC_SetGainCompensation(). Note: Applies to ADC groups regular and injected conversions.

struct hal_adc_low_power_config_t
#include <stm32c5xx_hal_adc.h>

ADC instance configuration advanced: low power features.

Public Members

hal_adc_lp_auto_wait_state_t lp_auto_wait

ADC low power feature autowait

struct hal_adc_calib_t
#include <stm32c5xx_hal_adc.h>

ADC calibration data.

Public Members

uint32_t factors [ 1U ]

ADC calibration factors buffer

struct hal_adc_reg_config_t
#include <stm32c5xx_hal_adc.h>

ADC group regular configuration.

Public Members

hal_adc_reg_trig_src_t trigger_src

ADC group regular conversion trigger source

hal_adc_reg_trig_edge_t trigger_edge

ADC group regular conversion trigger edge

uint8_t sequencer_length

ADC group regular sequencer scan length. Min_Data = 1, Max_Data = 16

hal_adc_reg_seq_discont_length_t sequencer_discont

ADC group regular sequencer scan discontinuous length

hal_adc_reg_continuous_mode_t continuous

ADC group regular continuous mode

hal_adc_reg_overrun_mode_t overrun

ADC group regular overrun mode

struct hal_adc_inj_config_t
#include <stm32c5xx_hal_adc.h>

ADC group injected configuration.

Public Members

hal_adc_inj_trig_src_t trigger_src

ADC group injected conversion trigger source

hal_adc_inj_trig_edge_t trigger_edge

ADC group injected conversion trigger edge

uint8_t sequencer_length

ADC group injected sequencer scan length. Can be a number between Min_Data = 1, Max_Data = 4

hal_adc_inj_seq_discont_length_t sequencer_discont

ADC group injected sequencer scan discontinuous length

struct hal_adc_channel_config_t
#include <stm32c5xx_hal_adc.h>

ADC channel configuration.

Public Members

hal_adc_group_t group

ADC group in which set the channel

uint8_t sequencer_rank

ADC group sequencer rank (position in conversions sequence) Can be a number in range of parameter “sequencer_length” in structures hal_adc_reg_config_t and hal_adc_inj_config_t: Min_Data = 1, Max_Data = {4; 16} depending on ADC group

hal_adc_sampling_time_t sampling_time

Sampling time

hal_adc_in_mode_t input_mode

ADC channel input mode (single, differential ended)

struct hal_adc_awd_config_t
#include <stm32c5xx_hal_adc.h>

ADC analog watchdog configuration.

Note

To use analog watchdog with interruption, start ADC conversion with optional interruption (HAL_ADC_xxx_StartConv_IT_Opt() or HAL_ADC_xxx_StartConv_DMA_Opt()) and parameter HAL_ADC_OPT_IT_xxx_AWDx.

Public Members

hal_adc_group_t group

ADC group from which conversion data is compared to thresholds. Analog watchdog instances specificities impacting this parameter: refer to description of “hal_adc_awd_instance_t”.

hal_adc_channel_t channel

ADC channel to be monitored

int32_t threshold_high

ADC analog watchdog threshold high value. Can be a number between Min_Data=-4194304 (two’s complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) Note: Value is signed and can exceed ADC resolution with post-processing computation (offset, oversampling, data shift, …). Note: To compute digital value from physical value (voltage), use helper macro HAL_ADC_CALC_VOLTAGE_TO_DATA().

int32_t threshold_low

ADC analog watchdog threshold low value. Can be a number between Min_Data=-4194304 (two’s complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) Note: Value is signed and can exceed ADC resolution with post-processing computation (offset, oversampling, data shift, …). Note: To compute digital value from physical value (voltage), use helper macro HAL_ADC_CALC_VOLTAGE_TO_DATA().

hal_adc_awd_filtering_t filtering

ADC analog watchdog filtering (specific to AWD instance: AWD1)

struct hal_adc_ovs_config_t
#include <stm32c5xx_hal_adc.h>

ADC oversampling configuration.

Public Members

hal_adc_ovs_scope_t scope

ADC oversampling scope

hal_adc_ovs_discont_t discont

ADC oversampling discontinuous mode

uint16_t ratio

ADC oversampling ratio: sum of conversions data computed to oversampling conversions data (before potential shift). Can be a number between Min_Data = 1, Max_Data = 1024

uint8_t shift

ADC oversampling shift: right bit shift Can be a number between Min_Data = 1, Max_Data = 10. Note: to compute shift value from ratio value and keeping data resolution, use function “HAL_ADC_GetOverSamplingShiftKeepRes()”.

struct hal_adc_offset_config_t
#include <stm32c5xx_hal_adc.h>

ADC offset configuration.

Public Members

hal_adc_channel_t channel

ADC channel with related conversion data to be processed

int32_t level

ADC offset level to be subtracted or added to the raw ADC converted data. Value between Min_Data= -1*0x003FFFFF (two’s complement 0xFFC00001) and Max_Data=0x003FFFFF. Note: Value is signed and can exceed ADC resolution with post-processing computation (offset, oversampling, data shift, …). Note: To compute digital value from physical value (voltage), use helper macro HAL_ADC_CALC_VOLTAGE_TO_DATA().

hal_adc_offset_sat_sign_state_t saturation_signed

ADC offset signed saturation

hal_adc_offset_sat_unsign_state_t saturation_unsigned

ADC offset unsigned saturation

struct hal_adc_mm_config_t
#include <stm32c5xx_hal_adc.h>

ADC multimode configuration.

Public Members

hal_adc_mm_mode_t mode

ADC multimode mode

hal_adc_mm_reg_data_format_t reg_data_format

ADC multimode group regular data format

hal_adc_mm_reg_data_transfer_pack_t reg_data_transfer_packing

ADC multimode group regular data transfer by DMA packing

hal_adc_mm_interl_delay_t interl_delay

ADC multimode interleaved delay between two sampling phases (parameter applicable only for mode interleaved)

struct hal_adc_handle_s
#include <stm32c5xx_hal_adc.h>

ADC Handle Structure Definition.

Public Members

hal_adc_t instance

Peripheral instance

hal_adc_handle_t * p_link_next_handle

Pointer to another HAL ADC handle of instance belonging to the same ADC common instance (therefore, sharing common features). Used to access multiple HAL ADC handles (daisy chain: from one to another and circular). Set using function HAL_ADC_SetLinkNextHandle().

volatile hal_adc_state_t global_state

HAL ADC global state

volatile hal_adc_group_state_t group_state [ 2U ]

HAL ADC groups (regular, injected) state

volatile hal_adc_common_state_t common_state

HAL ADC handle link to common instance state

volatile hal_adc_group_conv_per_start_t group_conv_per_start [ 2U ]

ADC group conversions per conversion start configuration

hal_dma_handle_t * hdma_reg

Pointer of DMA handle assigned to ADC group regular

hal_adc_mm_reg_data_transfer_pack_t mm_reg_data_transfer_packing

ADC multimode group regular data transfer by DMA packing

const void * p_user_data

User Data Pointer

hal_adc_cb_t p_error_cb

Callback function: Error

hal_adc_cb_t p_reg_end_of_sampling_cb

Callback function: ADC group regular end of sampling phase

hal_adc_cb_t p_reg_eoc_cb

Callback function: ADC group regular end of unitary conversion

hal_adc_cb_t p_reg_eos_cb

Callback function: ADC group regular end of sequence conversions

hal_adc_cb_t p_reg_xfer_half_cb

Callback function: ADC group regular conversion data buffer half transfer

hal_adc_cb_t p_reg_xfer_cplt_cb

Callback function: ADC group regular conversion data buffer transfer complete

hal_adc_cb_t p_reg_xfer_stop_cb

Callback function: ADC group regular conversion data transfer abort

hal_adc_cb_t p_inj_eoc_cb

Callback function: ADC group injected end of unitary conversion

hal_adc_cb_t p_inj_eos_cb

Callback function: ADC group injected end of sequence conversions

hal_adc_awd_cb_t p_awd_out_window_cb

Callback function: ADC analog watchdog out of window event

volatile uint32_t last_error_codes

Last error codes (bitfields of Error codes defined has bitfields)