STM32C5xx HAL Drivers Go to parent

HAL CCB Constants ¶

Error codes defined as bitfields ¶

Note

This section is not available for STM32C562xx.

group CCB_Error_Code

Defines

HAL_CCB_ERROR_NONE (0x0U) ¶: No error

HAL_CCB_ERROR_CCB_RCC_RESET (0x1U) ¶: CCB RCC reset detected when OPSTEP > 0x0

HAL_CCB_ERROR_SAES_RCC_RESET (0x2U) ¶: SAES RCC reset detected when OPSTEP > 0x0

HAL_CCB_ERROR_PKA_RCC_RESET (0x3U) ¶: PKA RCC reset detected when OPSTEP > 0x0

HAL_CCB_ERROR_RNG_RCC_RESET (0x4U) ¶: RNG RCC reset detected when OPSTEP > 0x0

HAL_CCB_ERROR_CCB_CLOCK_GATED (0x5U) ¶: RCC gated the CCB clock when OPSTEP > 0x0

HAL_CCB_ERROR_SAES_CLOCK_GATED (0x6U) ¶: RCC gated the SAES clock when OPSTEP > 0x0

HAL_CCB_ERROR_PKA_CLOCK_GATED (0x7U) ¶: RCC gated the PKA clock when OPSTEP > 0x0

HAL_CCB_ERROR_RNG_CLOCK_GATED (0x8U) ¶: RCC gated the RNG clock when OPSTEP > 0x0

HAL_CCB_ERROR_SAES_IV1_TRIVIAL (0x9U) ¶: SAES_IV1 is trivial (all 0s or all 1s) when OPSTEP = 0x2

HAL_CCB_ERROR_SAES_IV2_TRIVIAL (0xAU) ¶: SAES_IV2 is trivial (all 0s or all 1s) when OPSTEP = 0x2

HAL_CCB_ERROR_SAES_IV3_TRIVIAL (0xBU) ¶: SAES_IV3 is trivial (all 0s or all 1s) when OPSTEP = 0x2

HAL_CCB_ERROR_SAES_GCM_TAG_FAIL (0xCU) ¶: SAES GCM TAG comparison failed or wrong register read at OPSTEP = 0x17

HAL_CCB_ERROR_SAES_KEYSIZE_INVALID (0xDU) ¶: KEYSIZE different from 256 bits in SAES_CR when enabled and OPSTEP > 0x0

HAL_CCB_ERROR_SAES_CHMOD_INVALID (0xEU) ¶: CHMOD different than GCM or SAES not enabled or KEYVALID cleared when GCMPH > 0x0

HAL_CCB_ERROR_SAES_KMOD_INVALID (0xFU) ¶: KMOD different from wrapped key mode in SAES_CR at OPSTEP = 0x1 or 0x1A

HAL_CCB_ERROR_SAES_KEYSEL_INVALID (0x10U) ¶: KEYSEL different from 0x1 or 0x4 in SAES_CR when enabled, KEYVALID set, OPSTEP = 0x1

HAL_CCB_ERROR_SAES_GCMPH_INVALID (0x11U) ¶: GCMPH not correct (not incremented) in SAES_CR when OPSTEP > 0x1

HAL_CCB_ERROR_SAES_MODE_MISMATCH (0x12U) ¶: MODE in SAES_CR does not match expected value when OPSTEP > 0x1

HAL_CCB_ERROR_SAES_BUSY (0x13U) ¶: BUSY = 1 in SAES_SR when OPSTEP = 0x18 or 0x19

HAL_CCB_ERROR_PKA_EN_INVALID (0x14U) ¶: EN = 0 in PKA_CR when OPSTEP > 0x2 (except 0x12)

HAL_CCB_ERROR_PKA_INITOK_INVALID (0x15U) ¶: INITOK = 0 in PKA_SR when OPSTEP > 0x2 (except 0x12)

HAL_CCB_ERROR_AHB (0x16U) ¶: Authorized by local firewall, but unexpected AHB error when OPSTEP > 0x0

HAL_CCB_ERROR_PKA_LMF_SET (0x17U) ¶: LMF = 1 in PKA_SR (only ECDSA verification available) when OPSTEP > 0x0

HAL_CCB_ERROR_REFTAG_ZERO (0x18U) ¶: CCB_REFTAGRx registers are equal to 0 when OPSTEP > 0x12

HAL_CCB_ERROR_SECURITY_PROTECTION (0x1AU) ¶: Security/privilege protection inconsistent or changed when OPSTEP > 0x0

HAL_CCB_ERROR_PKA_MODE_MISMATCH (0x1BU) ¶: MODE in PKA_CR does not match expected value when OPSTEP > 0x0

HAL_CCB_ERROR_EVENT_ENDSTEP_0 (0x1CU) ¶: OPSTEP end-step event not found at OPSTEP = 0x0

HAL_CCB_ERROR_EVENT_ENDSTEP_1 (0x1DU) ¶: OPSTEP end-step event not found at OPSTEP = 0x1

HAL_CCB_ERROR_EVENT_ENDSTEP_2 (0x1EU) ¶: OPSTEP end-step event not found at OPSTEP = 0x2

HAL_CCB_ERROR_EVENT_ENDSTEP_3 (0x1FU) ¶: OPSTEP end-step event not found at OPSTEP = 0x3

HAL_CCB_ERROR_EVENT_ENDSTEP_A (0x20U) ¶: OPSTEP end-step event not found at OPSTEP = 0xA

HAL_CCB_ERROR_EVENT_ENDSTEP_12 (0x21U) ¶: OPSTEP end-step event not found at OPSTEP = 0x12

HAL_CCB_ERROR_EVENT_ENDSTEP_13 (0x22U) ¶: OPSTEP end-step event not found at OPSTEP = 0x13

HAL_CCB_ERROR_EVENT_ENDSTEP_17 (0x23U) ¶: OPSTEP end-step event not found at OPSTEP = 0x17

Flag event ¶

Note

This section is not available for STM32C562xx.

group CCB_Flag_Event

Defines

HAL_CCB_FLAG_BUSY CCB_SR_CCB_BUSY ¶: CCB busy or PKA RAM is being cleared following a peripheral reset

HAL_CCB_TAMP_EVT_RNG CCB_SR_TAMP_EVT0 ¶: RNG TAMP Event

HAL_CCB_TAMP_EVT_SAES CCB_SR_TAMP_EVT1 ¶: SAES TAMP Event

HAL_CCB_TAMP_EVT_PKA_RAM_REG CCB_SR_TAMP_EVT2 ¶: PKA RAM TAMP Event

HAL_CCB_TAMP_EVT_PKA_OPR CCB_SR_TAMP_EVT3 ¶: PKA TAMP Event

HAL_CCB_TAMP_EVT_CCB CCB_SR_TAMP_EVT4 ¶: CCB TAMP Event