HAL DMA Types

HAL DMA Types

group DMA_Exported_Types

Typedefs

typedef struct hal_dma_handle_s hal_dma_handle_t

HAL DMA channel handle structure type

typedef void ( * hal_dma_cb_t ) ( hal_dma_handle_t * hdma )

DMA channel process callback type definition

Enums

enum hal_dma_channel_t

DMA channel instances enumeration definition

Values:

enumerator HAL_LPDMA1_CH0

LPDMA1 Channel 0

enumerator HAL_LPDMA1_CH1

LPDMA1 Channel 1

enumerator HAL_LPDMA1_CH2

LPDMA1 Channel 2

enumerator HAL_LPDMA1_CH3

LPDMA1 Channel 3

enumerator HAL_LPDMA1_CH4

LPDMA1 Channel 4

enumerator HAL_LPDMA1_CH5

LPDMA1 Channel 5

enumerator HAL_LPDMA1_CH6

LPDMA1 Channel 6

enumerator HAL_LPDMA1_CH7

LPDMA1 Channel 7

enumerator HAL_LPDMA2_CH0

LPDMA2 Channel 0

enumerator HAL_LPDMA2_CH1

LPDMA2 Channel 1

enumerator HAL_LPDMA2_CH2

LPDMA2 Channel 2

enumerator HAL_LPDMA2_CH3

LPDMA2 Channel 3

enum hal_dma_state_t

DMA channel state enumeration definition

Values:

enumerator HAL_DMA_STATE_RESET

DMA channel not initialized

enumerator HAL_DMA_STATE_INIT

DMA channel initialized but not yet configured

enumerator HAL_DMA_STATE_IDLE

DMA channel initialized and configured

enumerator HAL_DMA_STATE_ACTIVE

DMA channel transfer is ongoing

enumerator HAL_DMA_STATE_SUSPEND

DMA channel transfer suspended

enumerator HAL_DMA_STATE_ABORT

DMA channel transfer aborted

enum hal_dma_xfer_level_t

HAL DMA channel transfer level completion enumeration definition

Values:

enumerator HAL_DMA_XFER_FULL_COMPLETE

0x00000001 Idle flag Idle flag Full channel transfer

enumerator HAL_DMA_XFER_HALF_COMPLETE

0x00000200 Half transfer complete flag Half transfer complete flag 0x00000001 Idle flag Idle flag Half channel transfer

enum hal_dma_xfer_mode_t

DMA xfer mode enumeration definition

Values:

enumerator HAL_DMA_XFER_MODE_DIRECT

DMA direct mode

enumerator HAL_DMA_XFER_MODE_LINKEDLIST_LINEAR

DMA linked list linear mode

enumerator HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR

DMA linked list circular mode

enum hal_dma_request_source_t

HAL DMA channel requests enumeration definition

Values:

enumerator HAL_LPDMA1_REQUEST_ADC1

LPDMA1 HW Request is ADC1 LPDMA1 HW request is ADC1

enumerator HAL_LPDMA1_REQUEST_ADC2

LPDMA1 HW Request is ADC2 LPDMA1 HW request is ADC2

enumerator HAL_LPDMA1_REQUEST_TIM6_UPD

LPDMA1 HW Request is TIM6_UPD LPDMA1 HW request is TIM6_UPD

enumerator HAL_LPDMA1_REQUEST_TIM7_UPD

LPDMA1 HW Request is TIM7_UPD LPDMA1 HW request is TIM7_UPD

enumerator HAL_LPDMA1_REQUEST_SPI1_RX

LPDMA1 HW Request is SPI1_RX LPDMA1 HW request is SPI1_RX

enumerator HAL_LPDMA1_REQUEST_SPI1_TX

LPDMA1 HW Request is SPI1_TX LPDMA1 HW request is SPI1_TX

enumerator HAL_LPDMA1_REQUEST_SPI2_RX

LPDMA1 HW Request is SPI2_RX LPDMA1 HW request is SPI2_RX

enumerator HAL_LPDMA1_REQUEST_SPI2_TX

LPDMA1 HW Request is SPI2_TX LPDMA1 HW request is SPI2_TX

enumerator HAL_LPDMA1_REQUEST_SPI3_RX

LPDMA1 HW Request is SPI3_RX LPDMA1 HW request is SPI3_RX

enumerator HAL_LPDMA1_REQUEST_SPI3_TX

LPDMA1 HW Request is SPI3_TX LPDMA1 HW request is SPI3_TX

enumerator HAL_LPDMA1_REQUEST_I2C1_RX

LPDMA1 HW Request is I2C1_RX LPDMA1 HW request is I2C1_RX

enumerator HAL_LPDMA1_REQUEST_I2C1_TX

LPDMA1 HW Request is I2C1_TX LPDMA1 HW request is I2C1_TX

enumerator HAL_LPDMA1_REQUEST_USART1_RX

LPDMA1 HW Request is USART1_RX LPDMA1 HW request is USART1_RX

enumerator HAL_LPDMA1_REQUEST_USART1_TX

LPDMA1 HW Request is USART1_TX LPDMA1 HW request is USART1_TX

enumerator HAL_LPDMA1_REQUEST_USART2_RX

LPDMA1 HW Request is USART2_RX LPDMA1 HW request is USART2_RX

enumerator HAL_LPDMA1_REQUEST_USART2_TX

LPDMA1 HW Request is USART2_TX LPDMA1 HW request is USART2_TX

enumerator HAL_LPDMA1_REQUEST_USART3_RX

LPDMA1 HW Request is USART3_RX LPDMA1 HW request is USART3_RX

enumerator HAL_LPDMA1_REQUEST_USART3_TX

LPDMA1 HW Request is USART3_TX LPDMA1 HW request is USART3_TX

enumerator HAL_LPDMA1_REQUEST_UART4_RX

LPDMA1 HW Request is UART4_RX LPDMA1 HW request is UART4_RX

enumerator HAL_LPDMA1_REQUEST_UART4_TX

LPDMA1 HW Request is UART4_TX LPDMA1 HW request is UART4_TX

enumerator HAL_LPDMA1_REQUEST_UART5_RX

LPDMA1 HW Request is UART5_RX LPDMA1 HW request is UART5_RX

enumerator HAL_LPDMA1_REQUEST_UART5_TX

LPDMA1 HW Request is UART5_TX LPDMA1 HW request is UART5_TX

enumerator HAL_LPDMA1_REQUEST_LPUART1_RX

LPDMA1 HW Request is LPUART1_RX LPDMA1 HW request is LPUART1_RX

enumerator HAL_LPDMA1_REQUEST_LPUART1_TX

LPDMA1 HW Request is LPUART1_TX LPDMA1 HW request is LPUART1_TX

enumerator HAL_LPDMA1_REQUEST_TIM1_CC1

LPDMA1 HW Request is TIM1_CC1 LPDMA1 HW request is TIM1_CC1

enumerator HAL_LPDMA1_REQUEST_TIM1_CC2

LPDMA1 HW Request is TIM1_CC2 LPDMA1 HW request is TIM1_CC2

enumerator HAL_LPDMA1_REQUEST_TIM1_CC3

LPDMA1 HW Request is TIM1_CC3 LPDMA1 HW request is TIM1_CC3

enumerator HAL_LPDMA1_REQUEST_TIM1_CC4

LPDMA1 HW Request is TIM1_CC4 LPDMA1 HW request is TIM1_CC4

enumerator HAL_LPDMA1_REQUEST_TIM1_UPD

LPDMA1 HW Request is TIM1_UPD LPDMA1 HW request is TIM1_UPD

enumerator HAL_LPDMA1_REQUEST_TIM1_TRGI

LPDMA1 HW Request is TIM1_TRGI LPDMA1 HW request is TIM1_TRGI

enumerator HAL_LPDMA1_REQUEST_TIM1_COM

LPDMA1 HW Request is TIM1_COM LPDMA1 HW request is TIM1_COM

enumerator HAL_LPDMA1_REQUEST_TIM2_CC1

LPDMA1 HW Request is TIM2_CC1 LPDMA1 HW request is TIM2_CC1

enumerator HAL_LPDMA1_REQUEST_TIM2_CC2

LPDMA1 HW Request is TIM2_CC2 LPDMA1 HW request is TIM2_CC2

enumerator HAL_LPDMA1_REQUEST_TIM2_CC3

LPDMA1 HW Request is TIM2_CC3 LPDMA1 HW request is TIM2_CC3

enumerator HAL_LPDMA1_REQUEST_TIM2_CC4

LPDMA1 HW Request is TIM2_CC4 LPDMA1 HW request is TIM2_CC4

enumerator HAL_LPDMA1_REQUEST_TIM2_UPD

LPDMA1 HW Request is TIM2_UPD LPDMA1 HW request is TIM2_UPD

enumerator HAL_LPDMA1_REQUEST_TIM2_TRGI

LPDMA1 HW Request is TIM2_TRGI LPDMA1 HW request is TIM2_TRGI

enumerator HAL_LPDMA1_REQUEST_TIM5_CC1

LPDMA1 HW Request is TIM5_CC1 LPDMA1 HW request is TIM5_CC1

enumerator HAL_LPDMA1_REQUEST_TIM5_CC2

LPDMA1 HW Request is TIM5_CC2 LPDMA1 HW request is TIM5_CC2

enumerator HAL_LPDMA1_REQUEST_TIM5_CC3

LPDMA1 HW Request is TIM5_CC3 LPDMA1 HW request is TIM5_CC3

enumerator HAL_LPDMA1_REQUEST_TIM5_CC4

LPDMA1 HW Request is TIM5_CC4 LPDMA1 HW request is TIM5_CC4

enumerator HAL_LPDMA1_REQUEST_TIM5_UPD

LPDMA1 HW Request is TIM5_UPD LPDMA1 HW request is TIM5_UPD

enumerator HAL_LPDMA1_REQUEST_TIM5_TRGI

LPDMA1 HW Request is TIM5_TRGI LPDMA1 HW request is TIM5_TRGI

enumerator HAL_LPDMA1_REQUEST_TIM15_CC1

LPDMA1 HW Request is TIM15_CC1 LPDMA1 HW request is TIM15_CC1

enumerator HAL_LPDMA1_REQUEST_TIM15_CC2

LPDMA1 HW Request is TIM15_CC2 LPDMA1 HW request is TIM15_CC2

enumerator HAL_LPDMA1_REQUEST_TIM15_UPD

LPDMA1 HW Request is TIM15_UPD LPDMA1 HW request is TIM15_UPD

enumerator HAL_LPDMA1_REQUEST_TIM15_TRGI

LPDMA1 HW Request is TIM15_TRGI LPDMA1 HW request is TIM15_TRGI

enumerator HAL_LPDMA1_REQUEST_TIM15_COM

LPDMA1 HW Request is TIM15_COM LPDMA1 HW request is TIM15_COM

enumerator HAL_LPDMA1_REQUEST_TIM16_CC1

LPDMA1 HW Request is TIM16_CC1 LPDMA1 HW request is TIM16_CC1

enumerator HAL_LPDMA1_REQUEST_TIM16_UPD

LPDMA1 HW Request is TIM16_UPD LPDMA1 HW request is TIM16_UPD

enumerator HAL_LPDMA1_REQUEST_TIM17_CC1

LPDMA1 HW Request is TIM17_CC1 LPDMA1 HW request is TIM17_CC1

enumerator HAL_LPDMA1_REQUEST_TIM17_UPD

LPDMA1 HW Request is TIM17_UPD LPDMA1 HW request is TIM17_UPD

enumerator HAL_LPDMA1_REQUEST_LPTIM1_IC1

LPDMA1 HW Request is LPTIM1_IC1 LPDMA1 HW request is LPTIM1_IC1

enumerator HAL_LPDMA1_REQUEST_LPTIM1_IC2

LPDMA1 HW Request is LPTIM1_IC2 LPDMA1 HW request is LPTIM1_IC2

enumerator HAL_LPDMA1_REQUEST_LPTIM1_UE

LPDMA1 HW Request is LPTIM1_UE LPDMA1 HW request is LPTIM1_UE

enumerator HAL_LPDMA1_REQUEST_CORDIC_RD

LPDMA1 HW Request is CORDIC_RD LPDMA1 HW request is CORDIC_RD

enumerator HAL_LPDMA1_REQUEST_CORDIC_WR

LPDMA1 HW Request is CORDIC_WR LPDMA1 HW request is CORDIC_WR

enumerator HAL_LPDMA1_REQUEST_I3C1_RX

LPDMA1 HW Request is I3C1_RX LPDMA1 HW request is I3C1_RX

enumerator HAL_LPDMA1_REQUEST_I3C1_TX

LPDMA1 HW Request is I3C1_TX LPDMA1 HW request is I3C1_TX

enumerator HAL_LPDMA1_REQUEST_I3C1_TC

LPDMA1 HW Request is I3C1_TC LPDMA1 HW request is I3C1_TC

enumerator HAL_LPDMA1_REQUEST_I3C1_RS

LPDMA1 HW Request is I3C1_RS LPDMA1 HW request is I3C1_RS

enumerator HAL_LPDMA1_REQUEST_AES_OUT

LPDMA1 HW Request is AES_OUT LPDMA1 HW request is AES_OUT

enumerator HAL_LPDMA1_REQUEST_AES_IN

LPDMA1 HW Request is AES_IN LPDMA1 HW request is AES_IN

enumerator HAL_LPDMA1_REQUEST_HASH_IN

LPDMA1 HW Request is HASH_IN LPDMA1 HW request is HASH_IN

enumerator HAL_LPDMA1_REQUEST_I2C2_RX

LPDMA1 HW Request is I2C2_RX LPDMA1 HW request is I2C2_RX

enumerator HAL_LPDMA1_REQUEST_I2C2_TX

LPDMA1 HW Request is I2C2_TX LPDMA1 HW request is I2C2_TX

enumerator HAL_LPDMA1_REQUEST_TIM8_CC1

LPDMA1 HW Request is TIM8_CC1 LPDMA1 HW request is TIM8_CC1

enumerator HAL_LPDMA1_REQUEST_TIM8_CC2

LPDMA1 HW Request is TIM8_CC2 LPDMA1 HW request is TIM8_CC2

enumerator HAL_LPDMA1_REQUEST_TIM8_CC3

LPDMA1 HW Request is TIM8_CC3 LPDMA1 HW request is TIM8_CC3

enumerator HAL_LPDMA1_REQUEST_TIM8_CC4

LPDMA1 HW Request is TIM8_CC4 LPDMA1 HW request is TIM8_CC4

enumerator HAL_LPDMA1_REQUEST_TIM8_UPD

LPDMA1 HW Request is TIM8_UPD LPDMA1 HW request is TIM8_UPD

enumerator HAL_LPDMA1_REQUEST_TIM8_TRGI

LPDMA1 HW Request is TIM8_TRGI LPDMA1 HW request is TIM8_TRGI

enumerator HAL_LPDMA1_REQUEST_TIM8_COM

LPDMA1 HW Request is TIM8_COM LPDMA1 HW request is TIM8_COM

enumerator HAL_LPDMA1_REQUEST_DAC1_CH1

LPDMA1 HW Request is DAC1_CH1 LPDMA1 HW request is DAC1_CH1

enumerator HAL_LPDMA2_REQUEST_ADC1

LPDMA2 HW Request is ADC1 LPDMA2 HW request is ADC1

enumerator HAL_LPDMA2_REQUEST_ADC2

LPDMA2 HW Request is ADC2 LPDMA2 HW request is ADC2

enumerator HAL_LPDMA2_REQUEST_TIM6_UPD

LPDMA2 HW Request is TIM6_UPD LPDMA2 HW request is TIM6_UPD

enumerator HAL_LPDMA2_REQUEST_TIM7_UPD

LPDMA2 HW Request is TIM7_UPD LPDMA2 HW request is TIM7_UPD

enumerator HAL_LPDMA2_REQUEST_SPI1_RX

LPDMA2 HW Request is SPI1_RX LPDMA2 HW request is SPI1_RX

enumerator HAL_LPDMA2_REQUEST_SPI1_TX

LPDMA2 HW Request is SPI1_TX LPDMA2 HW request is SPI1_TX

enumerator HAL_LPDMA2_REQUEST_SPI2_RX

LPDMA2 HW Request is SPI2_RX LPDMA2 HW request is SPI2_RX

enumerator HAL_LPDMA2_REQUEST_SPI2_TX

LPDMA2 HW Request is SPI2_TX LPDMA2 HW request is SPI2_TX

enumerator HAL_LPDMA2_REQUEST_SPI3_RX

LPDMA2 HW Request is SPI3_RX LPDMA2 HW request is SPI3_RX

enumerator HAL_LPDMA2_REQUEST_SPI3_TX

LPDMA2 HW Request is SPI3_TX LPDMA2 HW request is SPI3_TX

enumerator HAL_LPDMA2_REQUEST_I2C1_RX

LPDMA2 HW Request is I2C1_RX LPDMA2 HW request is I2C1_RX

enumerator HAL_LPDMA2_REQUEST_I2C1_TX

LPDMA2 HW Request is I2C1_TX LPDMA2 HW request is I2C1_TX

enumerator HAL_LPDMA2_REQUEST_USART1_RX

LPDMA2 HW Request is USART1_RX LPDMA2 HW request is USART1_RX

enumerator HAL_LPDMA2_REQUEST_USART1_TX

LPDMA2 HW Request is USART1_TX LPDMA2 HW request is USART1_TX

enumerator HAL_LPDMA2_REQUEST_USART2_RX

LPDMA2 HW Request is USART2_RX LPDMA2 HW request is USART2_RX

enumerator HAL_LPDMA2_REQUEST_USART2_TX

LPDMA2 HW Request is USART2_TX LPDMA2 HW request is USART2_TX

enumerator HAL_LPDMA2_REQUEST_USART3_RX

LPDMA2 HW Request is USART3_RX LPDMA2 HW request is USART3_RX

enumerator HAL_LPDMA2_REQUEST_USART3_TX

LPDMA2 HW Request is USART3_TX LPDMA2 HW request is USART3_TX

enumerator HAL_LPDMA2_REQUEST_UART4_RX

LPDMA2 HW Request is UART4_RX LPDMA2 HW request is UART4_RX

enumerator HAL_LPDMA2_REQUEST_UART4_TX

LPDMA2 HW Request is UART4_TX LPDMA2 HW request is UART4_TX

enumerator HAL_LPDMA2_REQUEST_UART5_RX

LPDMA2 HW Request is UART5_RX LPDMA2 HW request is UART5_RX

enumerator HAL_LPDMA2_REQUEST_UART5_TX

LPDMA2 HW Request is UART5_TX LPDMA2 HW request is UART5_TX

enumerator HAL_LPDMA2_REQUEST_LPUART1_RX

LPDMA2 HW Request is LPUART1_RX LPDMA2 HW request is LPUART1_RX

enumerator HAL_LPDMA2_REQUEST_LPUART1_TX

LPDMA2 HW Request is LPUART1_TX LPDMA2 HW request is LPUART1_TX

enumerator HAL_LPDMA2_REQUEST_TIM1_CC1

LPDMA2 HW Request is TIM1_CC1 LPDMA2 HW request is TIM1_CC1

enumerator HAL_LPDMA2_REQUEST_TIM1_CC2

LPDMA2 HW Request is TIM1_CC2 LPDMA2 HW request is TIM1_CC2

enumerator HAL_LPDMA2_REQUEST_TIM1_CC3

LPDMA2 HW Request is TIM1_CC3 LPDMA2 HW request is TIM1_CC3

enumerator HAL_LPDMA2_REQUEST_TIM1_CC4

LPDMA2 HW Request is TIM1_CC4 LPDMA2 HW request is TIM1_CC4

enumerator HAL_LPDMA2_REQUEST_TIM1_UPD

LPDMA2 HW Request is TIM1_UPD LPDMA2 HW request is TIM1_UPD

enumerator HAL_LPDMA2_REQUEST_TIM1_TRGI

LPDMA2 HW Request is TIM1_TRGI LPDMA2 HW request is TIM1_TRGI

enumerator HAL_LPDMA2_REQUEST_TIM1_COM

LPDMA2 HW Request is TIM1_COM LPDMA2 HW request is TIM1_COM

enumerator HAL_LPDMA2_REQUEST_TIM2_CC1

LPDMA2 HW Request is TIM2_CC1 LPDMA2 HW request is TIM2_CC1

enumerator HAL_LPDMA2_REQUEST_TIM2_CC2

LPDMA2 HW Request is TIM2_CC2 LPDMA2 HW request is TIM2_CC2

enumerator HAL_LPDMA2_REQUEST_TIM2_CC3

LPDMA2 HW Request is TIM2_CC3 LPDMA2 HW request is TIM2_CC3

enumerator HAL_LPDMA2_REQUEST_TIM2_CC4

LPDMA2 HW Request is TIM2_CC4 LPDMA2 HW request is TIM2_CC4

enumerator HAL_LPDMA2_REQUEST_TIM2_UPD

LPDMA2 HW Request is TIM2_UPD LPDMA2 HW request is TIM2_UPD

enumerator HAL_LPDMA2_REQUEST_TIM2_TRGI

LPDMA2 HW Request is TIM2_TRGI LPDMA2 HW request is TIM2_TRGI

enumerator HAL_LPDMA2_REQUEST_TIM5_CC1

LPDMA2 HW Request is TIM5_CC1 LPDMA2 HW request is TIM5_CC1

enumerator HAL_LPDMA2_REQUEST_TIM5_CC2

LPDMA2 HW Request is TIM5_CC2 LPDMA2 HW request is TIM5_CC2

enumerator HAL_LPDMA2_REQUEST_TIM5_CC3

LPDMA2 HW Request is TIM5_CC3 LPDMA2 HW request is TIM5_CC3

enumerator HAL_LPDMA2_REQUEST_TIM5_CC4

LPDMA2 HW Request is TIM5_CC4 LPDMA2 HW request is TIM5_CC4

enumerator HAL_LPDMA2_REQUEST_TIM5_UPD

LPDMA2 HW Request is TIM5_UPD LPDMA2 HW request is TIM5_UPD

enumerator HAL_LPDMA2_REQUEST_TIM5_TRGI

LPDMA2 HW Request is TIM5_TRGI LPDMA2 HW request is TIM5_TRGI

enumerator HAL_LPDMA2_REQUEST_TIM15_CC1

LPDMA2 HW Request is TIM15_CC1 LPDMA2 HW request is TIM15_CC1

enumerator HAL_LPDMA2_REQUEST_TIM15_CC2

LPDMA2 HW Request is TIM15_CC2 LPDMA2 HW request is TIM15_CC2

enumerator HAL_LPDMA2_REQUEST_TIM15_UPD

LPDMA2 HW Request is TIM15_UPD LPDMA2 HW request is TIM15_UPD

enumerator HAL_LPDMA2_REQUEST_TIM15_TRGI

LPDMA2 HW Request is TIM15_TRGI LPDMA2 HW request is TIM15_TRGI

enumerator HAL_LPDMA2_REQUEST_TIM15_COM

LPDMA2 HW Request is TIM15_COM LPDMA2 HW request is TIM15_COM

enumerator HAL_LPDMA2_REQUEST_TIM16_CC1

LPDMA2 HW Request is TIM16_CC1 LPDMA2 HW request is TIM16_CC1

enumerator HAL_LPDMA2_REQUEST_TIM16_UPD

LPDMA2 HW Request is TIM16_UPD LPDMA2 HW request is TIM16_UPD

enumerator HAL_LPDMA2_REQUEST_TIM17_CC1

LPDMA2 HW Request is TIM17_CC1 LPDMA2 HW request is TIM17_CC1

enumerator HAL_LPDMA2_REQUEST_TIM17_UPD

LPDMA2 HW Request is TIM17_UPD LPDMA2 HW request is TIM17_UPD

enumerator HAL_LPDMA2_REQUEST_LPTIM1_IC1

LPDMA2 HW Request is LPTIM1_IC1 LPDMA2 HW request is LPTIM1_IC1

enumerator HAL_LPDMA2_REQUEST_LPTIM1_IC2

LPDMA2 HW Request is LPTIM1_IC2 LPDMA2 HW request is LPTIM1_IC2

enumerator HAL_LPDMA2_REQUEST_LPTIM1_UE

LPDMA2 HW Request is LPTIM1_UE LPDMA2 HW request is LPTIM1_UE

enumerator HAL_LPDMA2_REQUEST_CORDIC_RD

LPDMA2 HW Request is CORDIC_RD LPDMA2 HW request is CORDIC_RD

enumerator HAL_LPDMA2_REQUEST_CORDIC_WR

LPDMA2 HW Request is CORDIC_WR LPDMA2 HW request is CORDIC_WR

enumerator HAL_LPDMA2_REQUEST_I3C1_RX

LPDMA2 HW Request is I3C1_RX LPDMA2 HW request is I3C1_RX

enumerator HAL_LPDMA2_REQUEST_I3C1_TX

LPDMA2 HW Request is I3C1_TX LPDMA2 HW request is I3C1_TX

enumerator HAL_LPDMA2_REQUEST_I3C1_TC

LPDMA2 HW Request is I3C1_TC LPDMA2 HW request is I3C1_TC

enumerator HAL_LPDMA2_REQUEST_I3C1_RS

LPDMA2 HW Request is I3C1_RS LPDMA2 HW request is I3C1_RS

enumerator HAL_LPDMA2_REQUEST_AES_OUT

LPDMA2 HW Request is AES_OUT LPDMA2 HW request is AES_OUT

enumerator HAL_LPDMA2_REQUEST_AES_IN

LPDMA2 HW Request is AES_IN LPDMA2 HW request is AES_IN

enumerator HAL_LPDMA2_REQUEST_HASH_IN

LPDMA2 HW Request is HASH_IN LPDMA2 HW request is HASH_IN

enumerator HAL_LPDMA2_REQUEST_I2C2_RX

LPDMA2 HW Request is I2C2_RX LPDMA2 HW request is I2C2_RX

enumerator HAL_LPDMA2_REQUEST_I2C2_TX

LPDMA2 HW Request is I2C2_TX LPDMA2 HW request is I2C2_TX

enumerator HAL_LPDMA2_REQUEST_TIM8_CC1

LPDMA2 HW Request is TIM8_CC1 LPDMA2 HW request is TIM8_CC1

enumerator HAL_LPDMA2_REQUEST_TIM8_CC2

LPDMA2 HW Request is TIM8_CC2 LPDMA2 HW request is TIM8_CC2

enumerator HAL_LPDMA2_REQUEST_TIM8_CC3

LPDMA2 HW Request is TIM8_CC3 LPDMA2 HW request is TIM8_CC3

enumerator HAL_LPDMA2_REQUEST_TIM8_CC4

LPDMA2 HW Request is TIM8_CC4 LPDMA2 HW request is TIM8_CC4

enumerator HAL_LPDMA2_REQUEST_TIM8_UPD

LPDMA2 HW Request is TIM8_UPD LPDMA2 HW request is TIM8_UPD

enumerator HAL_LPDMA2_REQUEST_TIM8_TRGI

LPDMA2 HW Request is TIM8_TRGI LPDMA2 HW request is TIM8_TRGI

enumerator HAL_LPDMA2_REQUEST_TIM8_COM

LPDMA2 HW Request is TIM8_COM LPDMA2 HW request is TIM8_COM

enumerator HAL_LPDMA2_REQUEST_DAC1_CH1

LPDMA2 HW Request is DAC1_CH1 LPDMA2 HW request is DAC1_CH1

enumerator HAL_DMA_REQUEST_SW

0x00000200 Software request DMA SW request

enum hal_dma_hardware_request_mode_t

DMA channel mode enumeration definition

Values:

enumerator HAL_DMA_HARDWARE_REQUEST_BURST

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level DMA burst request transfer

enumerator HAL_DMA_HARDWARE_REQUEST_BLOCK

0x00000800 Block hardware request Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level DMA block request transfer

enum hal_dma_direction_t

DMA channel direction enumeration definition

Values:

enumerator HAL_DMA_DIRECTION_MEMORY_TO_MEMORY

0x00000200 Software request Memory to memory direction Memory to memory direction

enumerator HAL_DMA_DIRECTION_PERIPH_TO_MEMORY

Peripheral to memory direction. Retained to ensure compatibility with other STM32. Peripheral to memory direction

enumerator HAL_DMA_DIRECTION_MEMORY_TO_PERIPH

Peripheral to memory direction. Retained to ensure compatibility with other STM32. Memory to peripheral direction. Retained to ensure compatibility with other STM32. Memory to peripheral direction

enum hal_dma_src_addr_increment_t

DMA channel source increment enumeration definition

Values:

enumerator HAL_DMA_SRC_ADDR_FIXED

Source fixed single/burst Source fixed single / burst

enumerator HAL_DMA_SRC_ADDR_INCREMENTED

0x00000008 Source incrementing burst Source incremented single/burst Source incremented single / burst

enum hal_dma_dest_addr_increment_t

DMA channel destination increment enumeration definition

Values:

enumerator HAL_DMA_DEST_ADDR_FIXED

Destination fixed single/burst Destination fixed single / burst

enumerator HAL_DMA_DEST_ADDR_INCREMENTED

0x00080000 Destination incrementing burst Destination incremented single/burst Destination incremented single / burst

enum hal_dma_src_data_width_t

DMA channel source data width enumeration definition

Values:

enumerator HAL_DMA_SRC_DATA_WIDTH_BYTE

Source data width: byte Source data width: byte

enumerator HAL_DMA_SRC_DATA_WIDTH_HALFWORD

Bit 0 Source data width: halfword Source data width: halfword

enumerator HAL_DMA_SRC_DATA_WIDTH_WORD

Bit 1 Source data width: word Source data width: word

enum hal_dma_dest_data_width_t

DMA channel destination data width enumeration definition

Values:

enumerator HAL_DMA_DEST_DATA_WIDTH_BYTE

Destination data width: byte Destination data width: byte

enumerator HAL_DMA_DEST_DATA_WIDTH_HALFWORD

Bit 0 Destination data width: halfword Destination data width: halfword

enumerator HAL_DMA_DEST_DATA_WIDTH_WORD

Bit 1 Destination data width: word Destination data width: word

enum hal_dma_priority_t

DMA channel priority enumeration definition

Values:

enumerator HAL_DMA_PRIORITY_LOW_WEIGHT_LOW

Priority level : Low Priority, Low Weight Priority level: low priority, low weight

enumerator HAL_DMA_PRIORITY_LOW_WEIGHT_MID

0x00400000 Priority level : Low Priority, Mid Weight Priority level: low priority, mid weight

enumerator HAL_DMA_PRIORITY_LOW_WEIGHT_HIGH

0x00800000 Priority level : Low Priority, High Weight Priority level: low priority, high weight

enumerator HAL_DMA_PRIORITY_HIGH

0x00C00000 Priority level Priority level : High Priority Priority level: high priority

enum hal_dma_flow_control_mode_t

DMA channel flow control mode enumeration definition

Values:

enumerator HAL_DMA_FLOW_CONTROL_DMA

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol in DMA flow control mode DMA request DMA channel flow control

enumerator HAL_DMA_FLOW_CONTROL_PERIPH

0x00001000 Hardware request in peripheral flow control mode Hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral flow control mode DMA request peripheral flow control

enum hal_dma_trigger_source_t

HAL DMA channel trigger hardware signal enumeration definition

Values:

enumerator HAL_LPDMA1_TRIGGER_EXTI0

LPDMA1 HW Trigger is EXTI0 LPDMA1 HW Trigger is EXTI0

enumerator HAL_LPDMA1_TRIGGER_EXTI1

LPDMA1 HW Trigger is EXTI1 LPDMA1 HW Trigger is EXTI1

enumerator HAL_LPDMA1_TRIGGER_EXTI2

LPDMA1 HW Trigger is EXTI2 LPDMA1 HW Trigger is EXTI2

enumerator HAL_LPDMA1_TRIGGER_EXTI3

LPDMA1 HW Trigger is EXTI3 LPDMA1 HW Trigger is EXTI3

enumerator HAL_LPDMA1_TRIGGER_EXTI4

LPDMA1 HW Trigger is EXTI4 LPDMA1 HW Trigger is EXTI4

enumerator HAL_LPDMA1_TRIGGER_EXTI5

LPDMA1 HW Trigger is EXTI5 LPDMA1 HW Trigger is EXTI5

enumerator HAL_LPDMA1_TRIGGER_EXTI6

LPDMA1 HW Trigger is EXTI6 LPDMA1 HW Trigger is EXTI6

enumerator HAL_LPDMA1_TRIGGER_EXTI7

LPDMA1 HW Trigger is EXTI7 LPDMA1 HW Trigger is EXTI7

enumerator HAL_LPDMA1_TRIGGER_TAMP_TRG1

LPDMA1 HW Trigger is TAMP_TRG1 LPDMA1 HW Trigger is TAMP_TRG1

enumerator HAL_LPDMA1_TRIGGER_TAMP_TRG2

LPDMA1 HW Trigger is TAMP_TRG2 LPDMA1 HW Trigger is TAMP_TRG2

enumerator HAL_LPDMA1_TRIGGER_TAMP_TRG3

LPDMA1 HW Trigger is TAMP_TRG3 LPDMA1 HW Trigger is TAMP_TRG3

enumerator HAL_LPDMA1_TRIGGER_LPTIM1_CH1

LPDMA1 HW Trigger is LPTIM1_CH1 LPDMA1 HW Trigger is LPTIM1_CH1

enumerator HAL_LPDMA1_TRIGGER_LPTIM1_CH2

LPDMA1 HW Trigger is LPTIM1_CH2 LPDMA1 HW Trigger is LPTIM1_CH2

enumerator HAL_LPDMA1_TRIGGER_RTC_ALRA_TRG

LPDMA1 HW Trigger is RTC_ALRA_TRG LPDMA1 HW Trigger is RTC_ALRA_TRG

enumerator HAL_LPDMA1_TRIGGER_RTC_ALRB_TRG

LPDMA1 HW Trigger is RTC_ALRB_TRG LPDMA1 HW Trigger is RTC_ALRB_TRG

enumerator HAL_LPDMA1_TRIGGER_RTC_WUT_TRG

LPDMA1 HW Trigger is RTC_WUT_TRG LPDMA1 HW Trigger is RTC_WUT_TRG

enumerator HAL_LPDMA1_TRIGGER_TIM2_TRGO

LPDMA1 HW Trigger is TIM2_TRGO LPDMA1 HW Trigger is TIM2_TRGO

enumerator HAL_LPDMA1_TRIGGER_TIM15_TRGO

LPDMA1 HW Trigger is TIM15_TRGO LPDMA1 HW Trigger is TIM15_TRGO

enumerator HAL_LPDMA1_TRIGGER_COMP1_OUT

LPDMA1 HW Trigger is COMP1_OUT LPDMA1 HW Trigger is COMP1_OUT

enumerator HAL_LPDMA1_TRIGGER_EVENTOUT

LPDMA1 HW Trigger is EVENTOUT LPDMA1 HW Trigger is EVENTOUT

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH0_TC

LPDMA1 HW Trigger is LPDMA1_CH0_TC LPDMA1 HW Trigger is LPDMA1_CH0_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH1_TC

LPDMA1 HW Trigger is LPDMA1_CH1_TC LPDMA1 HW Trigger is LPDMA1_CH1_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH2_TC

LPDMA1 HW Trigger is LPDMA1_CH2_TC LPDMA1 HW Trigger is LPDMA1_CH2_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH3_TC

LPDMA1 HW Trigger is LPDMA1_CH3_TC LPDMA1 HW Trigger is LPDMA1_CH3_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH4_TC

LPDMA1 HW Trigger is LPDMA1_CH4_TC LPDMA1 HW Trigger is LPDMA1_CH4_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH5_TC

LPDMA1 HW Trigger is LPDMA1_CH5_TC LPDMA1 HW Trigger is LPDMA1_CH5_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH6_TC

LPDMA1 HW Trigger is LPDMA1_CH6_TC LPDMA1 HW Trigger is LPDMA1_CH6_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA1_CH7_TC

LPDMA1 HW Trigger is LPDMA1_CH7_TC LPDMA1 HW Trigger is LPDMA1_CH7_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA2_CH0_TC

LPDMA1 HW Trigger is LPDMA2_CH0_TC LPDMA1 HW Trigger is LPDMA2_CH0_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA2_CH1_TC

LPDMA1 HW Trigger is LPDMA2_CH1_TC LPDMA1 HW Trigger is LPDMA2_CH1_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA2_CH2_TC

LPDMA1 HW Trigger is LPDMA2_CH2_TC LPDMA1 HW Trigger is LPDMA2_CH2_TC

enumerator HAL_LPDMA1_TRIGGER_LPDMA2_CH3_TC

LPDMA1 HW Trigger is LPDMA2_CH3_TC LPDMA1 HW Trigger is LPDMA2_CH3_TC

enumerator HAL_LPDMA2_TRIGGER_EXTI0

LPDMA2 HW Trigger is EXTI0 LPDMA2 HW Trigger is EXTI0

enumerator HAL_LPDMA2_TRIGGER_EXTI1

LPDMA2 HW Trigger is EXTI1 LPDMA2 HW Trigger is EXTI1

enumerator HAL_LPDMA2_TRIGGER_EXTI2

LPDMA2 HW Trigger is EXTI2 LPDMA2 HW Trigger is EXTI2

enumerator HAL_LPDMA2_TRIGGER_EXTI3

LPDMA2 HW Trigger is EXTI3 LPDMA2 HW Trigger is EXTI3

enumerator HAL_LPDMA2_TRIGGER_EXTI4

LPDMA2 HW Trigger is EXTI4 LPDMA2 HW Trigger is EXTI4

enumerator HAL_LPDMA2_TRIGGER_EXTI5

LPDMA2 HW Trigger is EXTI5 LPDMA2 HW Trigger is EXTI5

enumerator HAL_LPDMA2_TRIGGER_EXTI6

LPDMA2 HW Trigger is EXTI6 LPDMA2 HW Trigger is EXTI6

enumerator HAL_LPDMA2_TRIGGER_EXTI7

LPDMA2 HW Trigger is EXTI7 LPDMA2 HW Trigger is EXTI7

enumerator HAL_LPDMA2_TRIGGER_TAMP_TRG1

LPDMA2 HW Trigger is TAMP_TRG1 LPDMA2 HW Trigger is TAMP_TRG1

enumerator HAL_LPDMA2_TRIGGER_TAMP_TRG2

LPDMA2 HW Trigger is TAMP_TRG2 LPDMA2 HW Trigger is TAMP_TRG2

enumerator HAL_LPDMA2_TRIGGER_TAMP_TRG3

LPDMA2 HW Trigger is TAMP_TRG3 LPDMA2 HW Trigger is TAMP_TRG3

enumerator HAL_LPDMA2_TRIGGER_LPTIM1_CH1

LPDMA2 HW Trigger is LPTIM1_CH1 LPDMA2 HW Trigger is LPTIM1_CH1

enumerator HAL_LPDMA2_TRIGGER_LPTIM1_CH2

LPDMA2 HW Trigger is LPTIM1_CH2 LPDMA2 HW Trigger is LPTIM1_CH2

enumerator HAL_LPDMA2_TRIGGER_RTC_ALRA_TRG

LPDMA2 HW Trigger is RTC_ALRA_TRG LPDMA2 HW Trigger is RTC_ALRA_TRG

enumerator HAL_LPDMA2_TRIGGER_RTC_ALRB_TRG

LPDMA2 HW Trigger is RTC_ALRB_TRG LPDMA2 HW Trigger is RTC_ALRB_TRG

enumerator HAL_LPDMA2_TRIGGER_RTC_WUT_TRG

LPDMA2 HW Trigger is RTC_WUT_TRG LPDMA2 HW Trigger is RTC_WUT_TRG

enumerator HAL_LPDMA2_TRIGGER_TIM2_TRGO

LPDMA2 HW Trigger is TIM2_TRGO LPDMA2 HW Trigger is TIM2_TRGO

enumerator HAL_LPDMA2_TRIGGER_TIM15_TRGO

LPDMA2 HW Trigger is TIM15_TRGO LPDMA2 HW Trigger is TIM15_TRGO

enumerator HAL_LPDMA2_TRIGGER_COMP1_OUT

LPDMA2 HW Trigger is COMP1_OUT LPDMA2 HW Trigger is COMP1_OUT

enumerator HAL_LPDMA2_TRIGGER_EVENTOUT

LPDMA2 HW Trigger is EVENTOUT LPDMA2 HW Trigger is EVENTOUT

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH0_TC

LPDMA2 HW Trigger is LPDMA1_CH0_TC LPDMA2 HW Trigger is LPDMA1_CH0_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH1_TC

LPDMA2 HW Trigger is LPDMA1_CH1_TC LPDMA2 HW Trigger is LPDMA1_CH1_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH2_TC

LPDMA2 HW Trigger is LPDMA1_CH2_TC LPDMA2 HW Trigger is LPDMA1_CH2_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH3_TC

LPDMA2 HW Trigger is LPDMA1_CH3_TC LPDMA2 HW Trigger is LPDMA1_CH3_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH4_TC

LPDMA2 HW Trigger is LPDMA1_CH4_TC LPDMA2 HW Trigger is LPDMA1_CH4_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH5_TC

LPDMA2 HW Trigger is LPDMA1_CH5_TC LPDMA2 HW Trigger is LPDMA1_CH5_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH6_TC

LPDMA2 HW Trigger is LPDMA1_CH6_TC LPDMA2 HW Trigger is LPDMA1_CH6_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA1_CH7_TC

LPDMA2 HW Trigger is LPDMA1_CH7_TC LPDMA2 HW Trigger is LPDMA1_CH7_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA2_CH0_TC

LPDMA2 HW Trigger is LPDMA2_CH0_TC LPDMA2 HW Trigger is LPDMA2_CH0_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA2_CH1_TC

LPDMA2 HW Trigger is LPDMA2_CH1_TC LPDMA2 HW Trigger is LPDMA2_CH1_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA2_CH2_TC

LPDMA2 HW Trigger is LPDMA2_CH2_TC LPDMA2 HW Trigger is LPDMA2_CH2_TC

enumerator HAL_LPDMA2_TRIGGER_LPDMA2_CH3_TC

LPDMA2 HW Trigger is LPDMA2_CH3_TC LPDMA2 HW Trigger is LPDMA2_CH3_TC

enum hal_dma_trigger_polarity_t

DMA channel trigger polarity enumeration definition

Values:

enumerator HAL_DMA_TRIGGER_POLARITY_MASKED

No trigger of the selected DMA request. Masked trigger event No trigger of the selected DMA request. Masked trigger event

enumerator HAL_DMA_TRIGGER_POLARITY_RISING

Bit 0 Trigger of the selected DMA request on the rising edge of the selected trigger event input Trigger of the selected DMA request on the rising edge of the selected trigger event input

enumerator HAL_DMA_TRIGGER_POLARITY_FALLING

Bit 1 Trigger of the selected DMA request on the falling edge of the selected trigger event input Trigger of the selected DMA request on the falling edge of the selected trigger event input

enum hal_dma_trigger_mode_t

DMA channel trigger mode enumeration definition

Values:

enumerator HAL_DMA_TRIGGER_BLOCK_TRANSFER

A block transfer is conditioned by (at least)one hit trigger A block transfer is conditioned by (at least) one hit trigger

enumerator HAL_DMA_TRIGGER_NODE_TRANSFER

Bit 1 A LLI link transfer is conditioned by (at least)one hit trigger An LLI link transfer is conditioned by (at least) one hit trigger

enumerator HAL_DMA_TRIGGER_SINGLE_BURST_TRANSFER

0x0000C000 Trigger mode A Single/Burst transfer is conditioned by (at least) one hit trigger A single/burst transfer is conditioned by (at least) one hit trigger

enum hal_dma_dest_data_trunc_padd_t

DMA channel destination data truncation and padding enumeration definition

Values:

enumerator HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO

If src data width < dest data width: => Right aligned, padded with 0 up to the destination data width. If src data width > dest data width: => Right aligned, left truncated down to the destination data width. Destination data left truncation with zero padding

enumerator HAL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN

0x00000800 Padding / alignment mode Bit 0 If src data width < dest data width: => Right aligned, padded with sign extended up to the destination data width. If src data width > dest data width: => Left aligned, right truncated down to the destination data width. Destination data right truncation with sign padding

enum hal_dma_priv_attr_t

Privileged access level attribute

Values:

enumerator HAL_DMA_NPRIV

Non-privileged attribute DMA non-privileged attribute

enumerator HAL_DMA_PRIV

Privileged attribute DMA privileged attribute

enum hal_dma_attr_lock_status_t

Attributes lock status

Values:

enumerator HAL_DMA_UNLOCKED

DMA unlocked attribute

enumerator HAL_DMA_LOCKED

DMA locked attribute

enum hal_dma_linkedlist_xfer_event_mode_t

DMA channel half transfer and transfer complete event generation enumeration definition

Values:

enumerator HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK

The TC (and the HT) event is generated at the (respectively half of the) end of a block The TC (and the HT) event is generated at the (respectively half of the) end of a block The TC event is generated at the end of each block and the HT event is generated at the half of each block

enumerator HAL_DMA_LINKEDLIST_XFER_EVENT_NODE

Bit 1 The TC (and the HT) event is generated at the (respectively half) end of each linked list item The TC event is generated at the end of each linked list item and the HT event is generated at the half of each linked list item

enumerator HAL_DMA_LINKEDLIST_XFER_EVENT_Q

0xC0000000 Transfer complete event mode The TC (and the HT) event is generated at the (respectively half) end of the last linked list item The TC event is generated at the end of the last linked list item and the HT event is generated at the half of the last linked list item

enum hal_dma_linkedlist_execution_mode_t

DMA channel linked list execution enumeration definition

Values:

enumerator HAL_DMA_LINKEDLIST_EXECUTION_Q

Channel executed for the full linked list Channel executed for the full linked list

enumerator HAL_DMA_LINKEDLIST_EXECUTION_NODE

0x00010000 Link step mode Channel executed once for the current linked list item Channel executed once for the current LLI

enum hal_dma_node_type_t

DMA channel node type enumeration definition

Values:

enumerator HAL_DMA_NODE_LINEAR_ADDRESSING

Linear addressing DMA node

struct hal_dma_direct_xfer_config_t
#include <stm32c5xx_hal_dma.h>

DMA channel transfer configuration structure definition

Public Members

hal_dma_request_source_t request

DMA channel transfer request

hal_dma_direction_t direction

DMA channel transfer direction

hal_dma_src_addr_increment_t src_inc

DMA channel source increment mode

hal_dma_dest_addr_increment_t dest_inc

DMA channel destination increment mode

hal_dma_src_data_width_t src_data_width

DMA channel source data width

hal_dma_dest_data_width_t dest_data_width

DMA channel destination data width

hal_dma_priority_t priority

DMA channel priority level

struct hal_dma_trigger_config_t
#include <stm32c5xx_hal_dma.h>

DMA channel trigger configuration structure definition

Public Members

hal_dma_trigger_source_t source

DMA channel trigger event source selection

hal_dma_trigger_polarity_t polarity

DMA channel trigger event polarity

hal_dma_trigger_mode_t mode

DMA channel trigger mode

struct hal_dma_data_handling_config_t
#include <stm32c5xx_hal_dma.h>

DMA channel data handling configuration structure definition

Public Members

hal_dma_dest_data_trunc_padd_t trunc_padd

DMA channel data truncation or padding mode

struct hal_dma_linkedlist_xfer_config_t
#include <stm32c5xx_hal_dma.h>

DMA channel linked list configuration structure definition

Public Members

hal_dma_priority_t priority

DMA channel priority level

hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode

DMA channel transfer event mode

struct hal_dma_node_config_t
#include <stm32c5xx_hal_dma.h>

DMA channel node configuration enumeration definition

Public Members

hal_dma_direct_xfer_config_t xfer

DMA Channel direct transfer configuration

hal_dma_hardware_request_mode_t hw_request_mode

DMA channel hardware request mode

hal_dma_flow_control_mode_t flow_ctrl_mode

DMA channel flow control mode

hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode

DMA Channel transfer event mode

hal_dma_trigger_config_t trigger

DMA Channel trigger configuration

hal_dma_data_handling_config_t data_handling

DMA Channel data handling configuration

uint32_t src_addr

DMA Channel source address

uint32_t dest_addr

DMA Channel destination address

uint32_t size_byte

DMA Channel size in byte

struct hal_dma_node_t
#include <stm32c5xx_hal_dma.h>

DMA linked list node structure definition

Public Members

uint32_t regs [ ( 6U ) ]

Specifies the physical DMA channel node registers description

uint32_t info

Specified the physical DMA channel node information

struct hal_dma_handle_s
#include <stm32c5xx_hal_dma.h>

HAL DMA channel handle Structure definition

Public Members

hal_dma_channel_t instance

DMA channel instance

void * p_parent

DMA channel parent

volatile hal_dma_state_t global_state

DMA channel transfer state

volatile uint32_t last_error_codes

DMA channel transfer error codes

volatile hal_dma_xfer_mode_t xfer_mode

DMA channel transfer mode

hal_dma_node_t * p_head_node

DMA channel q

hal_dma_cb_t p_xfer_halfcplt_cb

DMA channel half transfer complete callback

hal_dma_cb_t p_xfer_cplt_cb

DMA channel transfer complete callback

hal_dma_cb_t p_xfer_abort_cb

DMA channel transfer Abort callback

hal_dma_cb_t p_xfer_suspend_cb

DMA channel transfer Suspend callback

hal_dma_cb_t p_xfer_error_cb

DMA channel transfer error callback

const void * p_user_data

DMA channel user data