HAL ETH types ¶

Enumerations ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group1

Enums

enum hal_eth_t ¶

HAL ETH instances enumeration definition.

Values:

enumerator HAL_ETH1 ¶: Instance ETH

enum hal_eth_state_t ¶

HAL ETH state enumeration definition.

Values:

enumerator HAL_ETH_STATE_RESET ¶: ETH Peripheral is not yet Initialized or De-Initialized

enumerator HAL_ETH_STATE_INIT ¶: ETH Peripheral is initialized but not yet configured

enumerator HAL_ETH_STATE_CONFIGURED ¶: ETH Peripheral initialized and a global config applied

enumerator HAL_ETH_STATE_POWER_DOWN ¶: ETH peripheral is in power down mode

enumerator HAL_ETH_STATE_FAULT ¶: ETH Peripheral encountered an unrecoverable error and a recovery sequence is needed

enum hal_eth_channel_state_t ¶

HAL ETH channel state structures definition.

Values:

enumerator HAL_ETH_CHANNEL_STATE_RESET ¶: Channel is disabled (Reset state)

enumerator HAL_ETH_CHANNEL_STATE_CONFIGURED ¶: Channel is configured and stopped

enumerator HAL_ETH_CHANNEL_STATE_ACTIVE ¶: Channel is started and running (Active state)

enumerator HAL_ETH_CHANNEL_STATE_SUSPENDED ¶: Channel is started and suspended (Idle state)

enum hal_eth_fifo_event_mode_t ¶

ETH FIFO event mode type enum definition.

Values:

enumerator HAL_ETH_FIFO_EVENT_NONE ¶: ETH Interrupt is disabled - Polling mode, no interrupt

enumerator HAL_ETH_FIFO_EVENT_ALWAYS ¶: ETH FIFO event on every executed descriptor

enumerator HAL_ETH_FIFO_EVENT_CYCLIC ¶: ETH Interrupt after every N descriptors. This mode reduces interrupt load for high-throughput operation.

enum hal_eth_media_interface_t ¶

HAL ETH Media Interfaces enum definition.

Values:

enumerator HAL_ETH_MEDIA_IF_MII ¶: Media Independent Interface

enumerator HAL_ETH_MEDIA_IF_RMII ¶: Reduced Media Independent Interface

enum hal_eth_tx_pkt_src_addr_ctrl_t ¶

HAL ETH Tx Packet Source Address Controls.

Values:

enumerator HAL_ETH_TX_PKT_SRC_ADDR_CONTROL_DISABLE ¶: SA Insertion Control: Do not include the source address.

enumerator HAL_ETH_TX_PKT_SRC_ADDR_INSERT ¶: SA Insertion Control: Include or insert the source address.

enumerator HAL_ETH_TX_PKT_SRC_ADDR_REPLACE ¶: SA Insertion Control: Replace the source address

enum hal_eth_tx_pkt_crc_pad_ctrl_t ¶

HAL ETH Tx Packet CRC Pad Controls.

Values:

enumerator HAL_ETH_TX_PKT_CRC_PAD_DISABLE ¶: CRC Pad Control: Disable CRC Insertion

enumerator HAL_ETH_TX_PKT_CRC_PAD_INSERT ¶: CRC Pad Control: CRC and Pad Insertion

enumerator HAL_ETH_TX_PKT_CRC_INSERT ¶: CRC Pad Control: CRC Insertion (Disable Pad Insertion)

enumerator HAL_ETH_TX_PKT_CRC_REPLACE ¶: CRC Pad Control: CRC Replacement

enum hal_eth_tx_pkt_csum_ctrl_t ¶

HAL ETH Tx Packet Checksum Controls.

Values:

enumerator HAL_ETH_TX_PKT_CSUM_DISABLE ¶: Do Nothing: Checksum Engine is disabled

enumerator HAL_ETH_TX_PKT_CSUM_HEADER_INSERT ¶: Only IP header checksum calculation and insertion are enabled.

enumerator HAL_ETH_TX_PKT_CSUM_PAYLOAD_INSERT ¶: IP header checksum and payload checksum calculation and insertion are enabled, but pseudo header checksum is not calculated in hardware

enumerator HAL_ETH_TX_PKT_CSUM_PAYLOAD_HEADER_INSERT ¶: IP Header checksum and payload checksum calculation and insertion are enabled, and pseudo header checksum is calculated in hardware.

enum hal_eth_tx_pkt_vlan_ctrl_t ¶

HAL ETH Tx Packet VLAN Controls.

Values:

enumerator HAL_ETH_TX_PKT_VLAN_DISABLE ¶: Do not add a VLAN tag.

enumerator HAL_ETH_TX_PKT_VLAN_REMOVE ¶: Remove the VLAN tag from the packets before transmission.

enumerator HAL_ETH_TX_PKT_VLAN_INSERT ¶: Insert a VLAN tag.

enumerator HAL_ETH_TX_PKT_VLAN_REPLACE ¶: Replace the VLAN tag.

enum hal_eth_tx_pkt_inner_vlan_ctrl_t ¶

HAL ETH Tx Packet Inner VLAN Controls.

Values:

enumerator HAL_ETH_TX_PKT_INNER_VLAN_DISABLE ¶: Do not add the inner VLAN tag.

enumerator HAL_ETH_TX_PKT_INNER_VLAN_REMOVE ¶: Remove the inner VLAN tag from the packets before transmission.

enumerator HAL_ETH_TX_PKT_INNER_VLAN_INSERT ¶: Insert the inner VLAN tag.

enumerator HAL_ETH_TX_PKT_INNER_VLAN_REPLACE ¶: Replace the inner VLAN tag.

enum hal_eth_tx_pkt_notify_ctrl_t ¶

HAL ETH Tx Packet Notification Controls.

Values:

enumerator HAL_ETH_TX_PKT_NOTIFY_DISABLE ¶: Do not notify application when the packet transmit request is completed

enumerator HAL_ETH_TX_PKT_NOTIFY_ENABLE ¶: Notify application when the packet transmit request is completed

enum hal_eth_mac_speed_t ¶

HAL ETH Speed.

Values:

enumerator HAL_ETH_MAC_SPEED_10M ¶: ETH MAC Speed 10M

enumerator HAL_ETH_MAC_SPEED_100M ¶: 0x00004000 MAC Speed ETH MAC Speed 100M

enum hal_eth_mac_duplex_mode_t ¶

HAL ETH Duplex Mode.

Values:

enumerator HAL_ETH_MAC_FULL_DUPLEX_MODE ¶: 0x00002000 Duplex Mode ETH MAC Full Duplex Mode

enumerator HAL_ETH_MAC_HALF_DUPLEX_MODE ¶: ETH MAC Half Duplex Mode

enum hal_eth_mac_loopback_ctrl_t ¶

HAL ETH Loopback mode Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_LOOPBACK_DISABLE ¶: ETH MAC Loopback mode Disable

enumerator HAL_ETH_MAC_LOOPBACK_ENABLE ¶: 0x00001000 Loopback Mode ETH MAC Loopback mode Enable

enum hal_eth_mac_src_addr_ctrl_t ¶

HAL ETH Source Address Control (Disable, Insertion or Replacement)

Values:

enumerator HAL_ETH_MAC_SA_DISABLE ¶: Disable SA insertion or replacement in the transmitted packets

enumerator HAL_ETH_MAC_SA_MAC0_INS ¶: Inserts the content of the MAC Address 0 registers in the SA field of all transmitted packets

enumerator HAL_ETH_MAC_SA_MAC1_INS ¶: Inserts the content of the MAC Address 1 registers in the SA field of all transmitted packets

enumerator HAL_ETH_MAC_SA_MAC0_REP ¶: Replace the content of the MAC Address 0 registers in the SA field of all transmitted packets

enumerator HAL_ETH_MAC_SA_MAC1_REP ¶: 0x70000000 Source Address Insertion or Replacement Control Replace the content of the MAC Address 1 registers in the SA field of all transmitted packets

enum hal_eth_mac_inter_pkt_gap_t ¶

HAL ETH Inter Packet Gap.

Values:

enumerator HAL_ETH_MAC_INTER_PKT_GAP_96_BIT ¶: ETH MAC Inter Packet Gap 96 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_88_BIT ¶: ETH MAC Inter Packet Gap 88 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_80_BIT ¶: ETH MAC Inter Packet Gap 80 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_72_BIT ¶: ETH MAC Inter Packet Gap 72 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_64_BIT ¶: ETH MAC Inter Packet Gap 64 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_56_BIT ¶: ETH MAC Inter Packet Gap 56 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_48_BIT ¶: ETH MAC Inter Packet Gap 48 Bit

enumerator HAL_ETH_MAC_INTER_PKT_GAP_40_BIT ¶: 0x07000000 Inter-Packet Gap ETH MAC Inter Packet Gap 40 Bit

enum hal_eth_mac_back_off_limit_t ¶

HAL ETH MAC Back Off Limit.

Values:

enumerator HAL_ETH_MAC_BACK_OFF_LIMIT_10 ¶: ETH MAC Back Off Limit 10

enumerator HAL_ETH_MAC_BACK_OFF_LIMIT_8 ¶: ETH MAC Back Off Limit 8

enumerator HAL_ETH_MAC_BACK_OFF_LIMIT_4 ¶: ETH MAC Back Off Limit 4

enumerator HAL_ETH_MAC_BACK_OFF_LIMIT_1 ¶: 0x00000060 Back-Off Limit ETH MAC Back Off Limit 1

enum hal_eth_mac_preeamble_length_t ¶

HAL ETH MAC Preamble Length.

Values:

enumerator HAL_ETH_MAC_PREAMBLE_LENGTH_7 ¶: ETH MAC Preamble Length 7

enumerator HAL_ETH_MAC_PREAMBLE_LENGTH_5 ¶: ETH MAC Preamble Length 5

enumerator HAL_ETH_MAC_PREAMBLE_LENGTH_3 ¶: ETH MAC Preamble Length 3

enum hal_eth_mac_rx_wd_timeout_t ¶

HAL ETH MAC Watchdog Timeout.

Values:

enumerator HAL_ETH_MAC_RX_WDT_2KB ¶: ETH MAC Watchdog Timeout 2KB

enumerator HAL_ETH_MAC_RX_WDT_3KB ¶: ETH MAC Watchdog Timeout 3KB

enumerator HAL_ETH_MAC_RX_WDT_4KB ¶: ETH MAC Watchdog Timeout 4KB

enumerator HAL_ETH_MAC_RX_WDT_5KB ¶: ETH MAC Watchdog Timeout 5KB

enumerator HAL_ETH_MAC_RX_WDT_6KB ¶: ETH MAC Watchdog Timeout 6KB

enumerator HAL_ETH_MAC_RX_WDT_7KB ¶: ETH MAC Watchdog Timeout 7KB

enumerator HAL_ETH_MAC_RX_WDT_8KB ¶: ETH MAC Watchdog Timeout 8KB

enumerator HAL_ETH_MAC_RX_WDT_9KB ¶: ETH MAC Watchdog Timeout 9KB

enumerator HAL_ETH_MAC_RX_WDT_10KB ¶: ETH MAC Watchdog Timeout 10KB

enumerator HAL_ETH_MAC_RX_WDT_11KB ¶: ETH MAC Watchdog Timeout 11KB

enumerator HAL_ETH_MAC_RX_WDT_12KB ¶: ETH MAC Watchdog Timeout 12KB

enumerator HAL_ETH_MAC_RX_WDT_13KB ¶: ETH MAC Watchdog Timeout 13KB

enumerator HAL_ETH_MAC_RX_WDT_14KB ¶: ETH MAC Watchdog Timeout 14KB

enumerator HAL_ETH_MAC_RX_WDT_15KB ¶: ETH MAC Watchdog Timeout 15KB

enumerator HAL_ETH_MAC_RX_WDT_16KB ¶: ETH MAC Watchdog Timeout 16KB

enum hal_eth_mac_gpkt_sz_limit_ctrl_t ¶

HAL ETH MAC Giant Packet Size Limit Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_GPKT_SZ_LIMIT_DISABLE ¶: ETH MAC Giant Packet Size Limit Disable

enumerator HAL_ETH_MAC_GPKT_SZ_LIMIT_ENABLE ¶: 0x00800000 Giant Packet Size Limit Control Enable ETH MAC Giant Packet Size Limit Enable

enum hal_eth_mac_2k_pkt_len_ctrl_t ¶

HAL ETH MAC IEEE 802.3as Support for 2K length Packets Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_2K_PKT_LEN_DISABLE ¶: ETH MAC IEEE 802.3as Support for 2K length Packets Disable

enumerator HAL_ETH_MAC_2K_PKT_LEN_ENABLE ¶: 0x00400000 IEEE 802.3as Support for 2K Packets ETH MAC IEEE 802.3as Support for 2K length Packets Enable

enum hal_eth_mac_crc_strip_pkt_ctrl_t ¶

HAL ETH MAC CRC stripping for Type Packets Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_CRC_STRIP_PKT_DISABLE ¶: ETH MAC CRC stripping for Type Packets Disable

enumerator HAL_ETH_MAC_CRC_STRIP_PKT_ENABLE ¶: 0x00200000 CRC stripping for Type packets ETH MAC CRC stripping for Type Packets Enable

enum hal_eth_mac_auto_pad_crc_s_ctrl_t ¶

HAL ETH MAC Automatic MAC Pad/CRC Stripping Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_AUTO_PAD_CRC_S_DISABLE ¶: ETH MAC Automatic Pad/CRC Stripping Disable

enumerator HAL_ETH_MAC_AUTO_PAD_CRC_S_ENABLE ¶: 0x00100000 Automatic Pad or CRC Stripping ETH MAC Automatic Pad/CRC Stripping Enable

enum hal_eth_mac_rx_wd_tim_ctrl_t ¶

HAL ETH MAC Watchdog Timer on Rx Path Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_RX_WD_TIM_DISABLE ¶: 0x00080000 Watchdog Disable ETH MAC Watchdog timer on Rx path Disable

enumerator HAL_ETH_MAC_RX_WD_TIM_ENABLE ¶: ETH MAC Watchdog timer on Rx path Enable

enum hal_eth_mac_tx_jabber_tim_ctrl_t ¶

HAL ETH MAC Jabber Timer on Tx Path Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_TX_JABBER_TIM_DISABLE ¶: 0x00020000 Jabber Disable ETH MAC Jabber timer on Tx path Disable

enumerator HAL_ETH_MAC_TX_JABBER_TIM_ENABLE ¶: ETH MAC Jabber timer on Tx path Enable

enum hal_eth_mac_rx_jumbo_pkt_ctrl_t ¶

HAL ETH MAC Jumbo Packet on Rx Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_RX_JUMBO_PKT_DISABLE ¶: ETH MAC Jumbo Packet on Rx path Disable

enumerator HAL_ETH_MAC_RX_JUMBO_PKT_ENABLE ¶: 0x00010000 Jumbo Packet Enable ETH MAC Jumbo Packet on Rx path Enable

enum hal_eth_mac_rx_csum_pkt_ctrl_t ¶

HAL ETH MAC Checksum Packet on Rx path Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_RX_CSUM_PKT_DISABLE ¶: ETH Checksum Packet on Rx path Disable

enumerator HAL_ETH_MAC_RX_CSUM_PKT_ENABLE ¶: 0x08000000 Checksum Offload ETH Checksum Packet on Rx path Enable

enum hal_eth_mac_rx_receive_own_ctrl_t ¶

HAL ETH MAC Receive Own on Rx path Control enumeration definition.

Values:

enumerator HAL_ETH_MAC_RX_RECEIVE_OWN_DISABLE ¶: 0x00000400 Disable Receive Own ETH MAC Receive Own on Rx path Disable

enumerator HAL_ETH_MAC_RX_RECEIVE_OWN_ENABLE ¶: ETH MAC Receive Own on Rx path Enable

enum hal_eth_mac_cs_before_tr_ctrl_t ¶

HAL ETH MAC Enables or disables the Carrier Sense Before Transmission in Full Duplex mode.

Values:

enumerator HAL_ETH_MAC_CS_BEFORE_TR_DISABLE ¶: ETH MAC Carrier Sense Before Transmission in Full-duplex mode Disable

enumerator HAL_ETH_MAC_CS_BEFORE_TR_ENABLE ¶: 0x00000800 Enable Carrier Sense Before Transmission in Full-duplex mode ETH MAC Carrier Sense Before Transmission in Full-duplex mode Enable

enum hal_eth_mac_cs_during_tr_ctrl_t ¶

HAL ETH MAC Enables or disables the Carrier Sense During Transmission in the Half Duplex mode.

Values:

enumerator HAL_ETH_MAC_CS_DURING_TR_DISABLE ¶: 0x00000200 Disable Carrier Sense During Transmission ETH MAC Disable Carrier Sense During Transmission errors.

enumerator HAL_ETH_MAC_CS_DURING_TR_ENABLE ¶: ETH MAC Enable Carrier Sense During Transmission errors.

enum hal_eth_mac_retry_tr_ctrl_t ¶

HAL ETH MAC Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.

Values:

enumerator HAL_ETH_MAC_RETRY_TR_DISABLE ¶: 0x00000100 Disable Retry ETH MAC Disable Retry Transmission

enumerator HAL_ETH_MAC_RETRY_TR_ENABLE ¶: ETH MAC Enable Retry Transmission

enum hal_eth_mac_deferral_check_ctrl_t ¶

HAL ETH MAC Enables or disables the deferral check function in Half Duplex mode.

Values:

enumerator HAL_ETH_MAC_DEFERRAL_CHECK_DISABLE ¶: ETH MAC Disable Deferral Check

enumerator HAL_ETH_MAC_DEFERRAL_CHECK_ENABLE ¶: 0x00000010 Deferral Check ETH MAC Enable Deferral Check

enum hal_eth_mac_uc_slow_proto_ctrl_t ¶

HAL ETH MAC Enable or disables the Detection of Slow Protocol Packets with unicast address.

Values:

enumerator HAL_ETH_MAC_UC_SLOW_PROTO_DISABLE ¶: ETH MAC Disable Unicast Slow Protocol Packet Detect

enumerator HAL_ETH_MAC_UC_SLOW_PROTO_ENABLE ¶: 0x00040000 Unicast Slow Protocol Packet Detect ETH MAC Enable Unicast Slow Protocol Packet Detect

enum hal_eth_mac_slow_proto_ctrl_t ¶

HAL ETH MAC Enable or disables the Slow Protocol Detection.

Values:

enumerator HAL_ETH_MAC_SLOW_PROTO_DISABLE ¶: ETH MAC Disable Slow Protocol Detection

enumerator HAL_ETH_MAC_SLOW_PROTO_ENABLE ¶: 0x00020000 Slow Protocol Detection Enable ETH MAC Enable Slow Protocol Detection

enum hal_eth_mac_rx_crc_pkt_chk_ctrl_t ¶

HAL ETH MAC Enable or disables the CRC Checking for Received Packets.

Values:

enumerator HAL_ETH_MAC_RX_CRC_PKT_CHK_DISABLE ¶: 0x00010000 Disable CRC Checking for Received Packets ETH MAC Disable CRC Checking for Received Packets

enumerator HAL_ETH_MAC_RX_CRC_PKT_CHK_ENABLE ¶: ETH MAC Enable CRC Checking for Received Packets

enum hal_eth_mac_ex_int_pkt_gap_ctrl_t ¶

HAL ETH MAC Enable or disables the extended inter packet gap.

Values:

enumerator HAL_ETH_MAC_E_INTER_PKT_GAP_DISABLE ¶: ETH MAC Disable Extended Inter-Packet Gap

enumerator HAL_ETH_MAC_E_INTER_PKT_GAP_ENABLE ¶: 0x01000000 Extended Inter-Packet Gap Enable ETH MAC Enable Extended Inter-Packet Gap

enum hal_eth_mac_prog_wd_ctrl_t ¶

HAL ETH MAC Enable or disables the Programmable Watchdog.

Values:

enumerator HAL_ETH_MAC_PROG_WD_DISABLE ¶: ETH MAC Disable Programmable Watchdog

enumerator HAL_ETH_MAC_PROG_WD_ENABLE ¶: 0x00000100 Programmable Watchdog Enable ETH MAC Enable Programmable Watchdog

enum hal_eth_mac_zero_q_pause_ctrl_t ¶

HAL ETH MAC Enable or disables the automatic generation of Zero Quanta Pause Control packets.

Values:

enumerator HAL_ETH_MAC_ZERO_Q_PAUSE_DISABLE ¶: 0x00000080 Disable Zero-Quanta Pause ETH MAC Disable Zero-Quanta Pause

enumerator HAL_ETH_MAC_ZERO_Q_PAUSE_ENABLE ¶: ETH MAC Enable Zero-Quanta Pause

enum hal_eth_mac_tr_flow_ctrl_t ¶

HAL ETH MAC Enables or disables the MAC to transmit Pause packets in Full Duplex mode or the MAC back pressure operation in Half Duplex mode.

Values:

enumerator HAL_ETH_MAC_TR_FLOW_CTRL_DISABLE ¶: ETH MAC Disable Transmit Flow Control

enumerator HAL_ETH_MAC_TR_FLOW_CTRL_ENABLE ¶: 0x00000002 Transmit Flow Control Enable ETH MAC Enable Transmit Flow Control

enum hal_eth_mac_uc_pause_pkt_ctrl_t ¶

HAL ETH MAC Enables or disables the MAC to detect Pause packets with unicast address of the station.

Values:

enumerator HAL_ETH_MAC_UC_PAUSE_PKT_DISABLE ¶: ETH MAC Disable Unicast Pause Packet Detect

enumerator HAL_ETH_MAC_UC_PAUSE_PKT_ENABLE ¶: 0x00000002 Unicast Pause Packet Detect ETH MAC Enable Unicast Pause Packet Detect

enum hal_eth_mac_receive_flow_ctrl_t ¶

HAL ETH MAC Enables or disables the MAC to decodes the received Pause packet and disables its transmitter for a specified (Pause) time.

Values:

enumerator HAL_ETH_MAC_RECEIVE_FLOW_DISABLE ¶: ETH MAC Disable Receive Flow Control

enumerator HAL_ETH_MAC_RECEIVE_FLOW_ENABLE ¶: 0x00000001 Receive Flow Control Enable ETH MAC Enable Receive Flow Control

enum hal_eth_mac_pause_low_thr_t ¶

HAL ETH MAC Pause Low Threshold.

Values:

enumerator HAL_ETH_MAC_PLT_MINUS_4_SLOT_TIME ¶: ETH MAC Pause Low Threshold Minus 4

enumerator HAL_ETH_MAC_PLT_MINUS_28_SLOT_TIME ¶: ETH MAC Pause Low Threshold Minus 28

enumerator HAL_ETH_MAC_PLT_MINUS_36_SLOT_TIME ¶: ETH MAC Pause Low Threshold Minus 36

enumerator HAL_ETH_MAC_PLT_MINUS_144_SLOT_TIME ¶: ETH MAC Pause Low Threshold Minus 144

enumerator HAL_ETH_MAC_PLT_MINUS_256_SLOT_TIME ¶: ETH MAC Pause Low Threshold Minus 256

enumerator HAL_ETH_MAC_PLT_MINUS_512_SLOT_TIME ¶: ETH MAC Pause Low Threshold Minus 512

enum hal_eth_dma_addr_align_ctrl_t ¶

Enables or disables the Peripheral Bus Master interface address aligned burst transfers on Read and Write channels.

Values:

enumerator HAL_ETH_DMA_ADDR_ALIGN_DISABLE ¶: ETH DMA Disable Address-Aligned Beats

enumerator HAL_ETH_DMA_ADDR_ALIGN_ENABLE ¶: 0x00001000 Address-Aligned Beats ETH DMA Enable Address-Aligned Beats

enum hal_eth_dma_burst_len_mode_t ¶

HAL ETH Burst Length Mode.

Values:

enumerator HAL_ETH_DMA_BURST_LEN_FIXED ¶: 0x00000001 Fixed Burst Length Fixed Burst Length as specified by the BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8 or BLEN4 field

enumerator HAL_ETH_DMA_BURST_LEN_MAX_ALLOWED ¶: Burst transfers of length equal to or less than the maximum allowed burst length

enum hal_eth_dma_mixed_burst_ctrl_t ¶

ETH DMA Mixed Burst Mode Enumeration definition.

Values:

enumerator HAL_ETH_DMA_MIXED_BURST_MODE_ENABLED ¶: 0x00004000 Mixed Burst Mixed Burst is enabled. When this control is enabled, the BUS master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the BUS master performs fixed burst transfers (INCRx and SINGLE).

enumerator HAL_ETH_DMA_MIXED_BURST_MODE_DISABLED ¶: Mixed Burst is disabled.

enum hal_eth_dma_rebuild_inc_ctrl_t ¶

ETH DMA Rebuild Increment Burst Enumeration definition.

Values:

enumerator HAL_ETH_DMA_REBUILD_INC_BURST_ENABLED ¶: 0x00008000 Rebuild INCRx Burst Rebuild INCRx Burst is enabled. When this control is enabled and the System Bus master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the BUS master interface rebuilds the pending beats of an EBT with an unspecified (INCR) burst.

enumerator HAL_ETH_DMA_REBUILD_INC_BURST_DISABLED ¶: Rebuild INCRx Burst is disabled. For EBT/SPLIT/RETRY, pending beats are rebuilt using unspecified-length (INCR) bursts (default behavior)

enum hal_eth_dma_tr_prio_ctrl_t ¶

DMA Transmit Priority Control enumeration.

This enumeration controls whether the DMA gives priority to transmit operations over receive operations. Enabling this can improve transmit performance in scenarios where transmit latency is critical.

Values:

enumerator HAL_ETH_DMA_TR_PRIO_DISABLE ¶: Transmit priority is disabled; receive operations are prioritized over transmit.

enumerator HAL_ETH_DMA_TR_PRIO_ENABLE ¶: 0x00000800 Transmit priority Transmit priority is enabled; transmit operations are prioritized over receive.

enum hal_eth_dma_tx_pbl_x8_mode_ctrl_t ¶

ETH DMA Tx PBLx8 mode control enumeration definition.

This enumeration enables or disables the multiplication by eight of the programmable burst length (PBL) via the PBLX8 bit in ETH_DMACCR.

Values:

enumerator HAL_ETH_DMA_TX_PBL_X8_DISABLE ¶: ETH TX DMA Disable 8xPBL mode

enumerator HAL_ETH_DMA_TX_PBL_X8_ENABLE ¶: 0x00010000 8xPBL mode ETH TX DMA Enable 8xPBL mode

enum hal_eth_dma_tx_burst_length_t ¶

HAL ETH DMA Tx Burst Length.

Values:

enumerator HAL_ETH_DMA_TX_BLEN_1_BEAT ¶: DMA Transmit Programmable Burst Length = 1 beat

enumerator HAL_ETH_DMA_TX_BLEN_2_BEAT ¶: DMA Transmit Programmable Burst Length = 2 beats

enumerator HAL_ETH_DMA_TX_BLEN_4_BEAT ¶: DMA Transmit Programmable Burst Length = 4 beats

enumerator HAL_ETH_DMA_TX_BLEN_8_BEAT ¶: DMA Transmit Programmable Burst Length = 8 beats

enumerator HAL_ETH_DMA_TX_BLEN_16_BEAT ¶: DMA Transmit Programmable Burst Length = 16 beats

enumerator HAL_ETH_DMA_TX_BLEN_32_BEAT ¶: DMA Transmit Programmable Burst Length = 32 beats

enum hal_eth_dma_tx_sec_pkt_op_ctrl_t ¶

Enables or disables the Operate on second Packet mode, which allows the DMA to process a second Packet of Transmit data even before obtaining the status for the first one.

Values:

enumerator HAL_ETH_DMA_TX_SEC_PKT_OP_DISABLE ¶: ETH TX DMA Disable Operate on Second Packet

enumerator HAL_ETH_DMA_TX_SEC_PKT_OP_ENABLE ¶: 0x00000010 Operate on Second Packet ETH TX DMA Enable Operate on Second Packet

enum hal_eth_dma_rx_burst_length_t ¶

HAL ETH DMA Rx Burst Length.

Values:

enumerator HAL_ETH_DMA_RX_BLEN_1_BEAT ¶: DMA Receive Programmable Burst Length = 1 beat

enumerator HAL_ETH_DMA_RX_BLEN_2_BEAT ¶: DMA Receive Programmable Burst Length = 2 beats

enumerator HAL_ETH_DMA_RX_BLEN_4_BEAT ¶: DMA Receive Programmable Burst Length = 4 beats

enumerator HAL_ETH_DMA_RX_BLEN_8_BEAT ¶: DMA Receive Programmable Burst Length = 8 beats

enumerator HAL_ETH_DMA_RX_BLEN_16_BEAT ¶: DMA Receive Programmable Burst Length = 16 beats

enumerator HAL_ETH_DMA_RX_BLEN_32_BEAT ¶: DMA Receive Programmable Burst Length = 32 beats

enum hal_eth_mtl_tx_fwd_status_ctrl_t ¶

HAL ETH MTL Tx Forward Status to Application.

Values:

enumerator HAL_ETH_MTL_TX_FWD_STATUS_DISABLE ¶: 0x00000002 Drop Transmit Status Tx Forward Status to application Disable

enumerator HAL_ETH_MTL_TX_FWD_STATUS_ENABLE ¶: Tx Forward Status to application Enable

enum hal_eth_mtl_tx_ops_mode_t ¶

HAL ETH MTL Tx Queue Operation Mode.

Values:

enumerator HAL_ETH_MTL_TX_QUEUE_ENABLED ¶: Transmit Queue Enabled

enum hal_eth_mtl_tx_queue_size_t ¶

MTL Transmit Queue Size enumeration.

This enumeration specifies the size in bytes of the Ethernet MTL Transmit queue.

Values:

enumerator HAL_ETH_MTL_TX_QUEUE_SZ_2048_BYTE ¶: Transmit Queue Size 2048 bytes

enum hal_eth_mtl_tx_transmit_mode_t ¶

HAL ETH MTL Transmit Mode.

Values:

enumerator HAL_ETH_MTL_TX_Q_STORE_AND_FORWARD ¶: 0x00000002 Transmit Store and Forward Transmit Store and Forward Mode

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_32_BYTE ¶: Transmit Threshold Control 32 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_64_BYTE ¶: Transmit Threshold Control 64 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_96_BYTE ¶: Transmit Threshold Control 96 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_128_BYTE ¶: Transmit Threshold Control 128 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_192_BYTE ¶: Transmit Threshold Control 192 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_256_BYTE ¶: Transmit Threshold Control 256 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_384_BYTE ¶: Transmit Threshold Control 384 bytes

enumerator HAL_ETH_MTL_TX_Q_THRESHOLD_512_BYTE ¶: 0x00000070 Transmit Threshold Control Transmit Threshold Control 512 bytes

enum hal_eth_mtl_rx_ops_mode_t ¶

HAL ETH MTL Rx Queue Operation Mode.

Values:

enumerator HAL_ETH_MTL_RX_QUEUE_ENABLED ¶: Receive Queue Enabled

enum hal_eth_mtl_rx_queue_size_t ¶

ETH MTL Receive Queue Size enumeration.

This enumeration specifies the size in bytes of the Ethernet MTL Receive queue.

Values:

enumerator HAL_ETH_MTL_RX_QUEUE_SZ_2048_BYTE ¶: Receive Queue Size 2048 bytes

enum hal_eth_mtl_rx_drop_cs_err_ctrl_t ¶

ETH MTL Drop Checksum Error Packet Control enumeration.

This enumeration controls whether the Ethernet MAC MTL (MAC Transmission Layer) will drop received packets with checksum errors or forward them to the application.

Values:

enumerator HAL_ETH_MTL_RX_DROP_CS_ERR_DISABLE ¶: 0x00000040 Disable Dropping of TCP/IP Checksum Error Packets TCP-IP Packets with checksum errors are forwarded to the application.

enumerator HAL_ETH_MTL_RX_DROP_CS_ERR_ENABLE ¶: TCP-IP Packets with checksum errors are dropped and not forwarded to the application.

enum hal_eth_mtl_rx_fwd_err_pkt_ctrl_t ¶

ETH MTL Forward Error Packets Control enumeration.

This enumeration controls whether the Ethernet MTL will forward received packets that have errors to the application or discard them.

Values:

enumerator HAL_ETH_MTL_RX_FWD_ERR_PKT_DISABLE ¶: Received packets with errors are discarded and not forwarded to the application.

enumerator HAL_ETH_MTL_RX_FWD_ERR_PKT_ENABLE ¶: 0x00000010 Forward Error Packets Received packets with errors are forwarded to the application.

enum hal_eth_mtl_rx_fwd_usz_pkt_ctrl_t ¶

ETH MTL Control for forwarding received undersized good packets in the MTL RX path.

This enumeration defines the options for handling received undersized good packets in the Ethernet MAC MTL (MAC Transmission Layer) RX path. Depending on the selected value, the hardware will either discard or forward such packets to the application.

Values:

enumerator HAL_ETH_MTL_RX_FWD_USZ_PKT_DISABLE ¶: Received undersized good packets are discarded and not forwarded to the application.

enumerator HAL_ETH_MTL_RX_FWD_USZ_PKT_ENABLE ¶: 0x00000008 Forward Undersized Good Packets Received undersized good packets are forwarded to the application.

enum hal_eth_mtl_rx_queue_mode_t ¶

HAL ETH MTL Receive Mode.

Values:

enumerator HAL_ETH_MTL_RX_Q_STORE_AND_FORWARD ¶: 0x00000020 Receive Queue Store and Forward Receive Store and Forward operating mode

enumerator HAL_ETH_MTL_RX_Q_THRESHOLD_64 ¶: Receive Threshold Control

enumerator HAL_ETH_MTL_RX_Q_THRESHOLD_32 ¶: Receive Threshold Control

enumerator HAL_ETH_MTL_RX_Q_THRESHOLD_96 ¶: Receive Threshold Control

enumerator HAL_ETH_MTL_RX_Q_THRESHOLD_128 ¶: 0x00000003 Receive Queue Threshold Control Receive Threshold Control

enum hal_eth_arp_offload_status_t ¶

HAL ETH MAC ARP Offloading Status.

Values:

enumerator HAL_ETH_ARP_OFFLOAD_DISABLED ¶: ETH ARP Offloading Disabled

enumerator HAL_ETH_ARP_OFFLOAD_ENABLED ¶: 0x80000000 ARP Offload Enable ETH ARP Offloading Enabled

enum hal_eth_wakeup_trigger_t ¶

Ethernet Wakeup trigger type enumeration.

This enumeration defines the possible trigger conditions for the Ethernet Wakeup External line. It is used to indicate which edge(s) have caused a pending interrupt on the External line.

Values:

enumerator HAL_ETH_WAKEUP_TRIGGER_NONE ¶: No Trigger Mode No trigger pending

enumerator HAL_ETH_WAKEUP_TRIGGER_RISING ¶: Trigger Rising Mode Rising edge trigger pending

enumerator HAL_ETH_WAKEUP_TRIGGER_FALLING ¶: Trigger Falling Mode Falling edge trigger pending

enumerator HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING ¶: Trigger Rising & Falling Mode Both rising and falling edge triggers pending

ETH handles types definitions ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group2

Typedefs

typedef struct hal_eth_handle_s hal_eth_handle_t ¶

HAL ETH handle type definition.

HAL ETH handle structure type

struct hal_eth_tx_channel_handle_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Tx Channel Handle Structure definition.

Public Members

ETH_DMA_Channel_TypeDef * p_dma_instance ¶: Tx/Rx DMA Instances Register base address

ETH_MTL_Queue_TypeDef * p_mtl_instance ¶: Tx/Rx MTL Instances Register base address

volatile hal_eth_channel_state_t channel_state ¶: ETH channel state information related to channel handle management and also related to Tx operations

volatile uint32_t channel_lock_state ¶: ETH channel lock state for managing atomic access and preventing concurrent operations

hal_eth_tx_descriptor_list_t tx_desc_list ¶: DMA Channel Tx descriptor wrapper: holds all Tx descriptors list addresses and current descriptor index

hal_eth_fifo_event_config_t fifo_event_config ¶: Request FIFO event Configuration for the Channel

uint32_t event_cnt ¶: counter of fifo events

hal_eth_tx_complete_cb_t p_tx_complete_cb ¶: ETH Tx Complete Callback

hal_eth_channel_cb_t p_ch_event_cb ¶: ETH DMA Tx Event Callback

struct hal_eth_rx_channel_handle_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Rx Channel Handle Structure definition.

Public Members

void * p_dma_instance ¶: Tx/Rx DMA Instances Register base address

void * p_mtl_instance ¶: Tx/Rx MTL Instances Register base address

volatile hal_eth_channel_state_t channel_state ¶: ETH channel state information related to channel handle management and also related to Tx operations

volatile uint32_t channel_lock_state ¶: ETH channel lock state for managing atomic access and preventing concurrent operations

hal_eth_rx_descriptor_list_t rx_desc_list ¶: DMA Channel Rx descriptor wrapper: holds all Rx descriptors list addresses and current descriptor index

uint32_t rx_buff_size_byte ¶

Rx buffers specified in bytes The maximum buffer size is limited to 16 Kbytes. this field is an arg of

See also

hal_eth_rx_allocate_cb_t

hal_eth_fifo_event_config_t fifo_event_config ¶: Request FIFO event Configuration for the Channel

uint32_t event_cnt ¶: counter of fifo events

hal_eth_rx_complete_cb_t p_rx_complete_cb ¶: ETH Rx Complete Callback

hal_eth_rx_allocate_cb_t p_rx_allocate_cb ¶: ETH Rx Get Buffer Function

hal_eth_channel_cb_t p_ch_event_cb ¶: ETH DMA Rx Event Callback

struct hal_eth_handle_s ¶

#include <stm32c5xx_hal_eth.h>

ETH Handle Structure definition.

Public Members

hal_eth_t instance ¶: Peripheral instance

hal_eth_tx_channel_handle_t tx_channels [ ( 1U ) ] ¶: Tx Channels Handles

hal_eth_rx_channel_handle_t rx_channels [ ( 1U ) ] ¶: Rx Channels Handles

volatile hal_eth_state_t global_state ¶: ETH state information related to global Handle management

const void * p_user_data ¶: User data pointer

hal_eth_cb_t p_data_cb ¶: ETH Data Event Callback

hal_eth_cb_t p_error_cb ¶: ETH Error Callback

hal_eth_cb_t p_event_cb ¶: ETH Event Callback

hal_eth_cb_t p_pmt_cb ¶: ETH Power Management Callback

hal_eth_cb_t p_eee_cb ¶: ETH EEE Callback

hal_eth_wakeup_cb_t p_wake_up_cb ¶: ETH Wake UP Callback

hal_eth_cache_cb_t p_cache_invalidate_cb ¶: ETH Cache Invalidate (Peripheral to CPU direction) Callback. This callback are called AFTER peripheral/DMA writes.

hal_eth_cache_cb_t p_cache_flush_cb ¶: ETH Cache Flush (CPU to Peripheral direction) Callback. This callback are called BEFORE peripheral/DMA reads.

hal_os_semaphore_t semaphore ¶: ETH OS semaphore

volatile uint32_t last_error_codes ¶: Last error codes on ETH peripheral side

ETH DMA descriptor lists types definitions ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group3

struct hal_eth_tx_descriptor_list_t ¶

#include <stm32c5xx_hal_eth.h>

DMA Transmit Descriptors Wrapper structure definition.

Public Members

uint32_t * p_desc_list_addr ¶: Tx Descriptors Base address

uint32_t total_desc_cnt ¶: TX total Number of descriptors

uint32_t desc_len_byte ¶: TX Desc len in byte

uint32_t curr_desc_id ¶: TX current available Desc ID

uint32_t built_desc_id ¶: TX built Desc ID

uint32_t buff_in_use ¶: Buffers in Use

struct hal_eth_rx_descriptor_list_t ¶

#include <stm32c5xx_hal_eth.h>

DMA Receive Descriptors Wrapper structure definition.

Public Members

uint32_t * p_desc_list_addr ¶: Rx Descriptors base address

uint32_t total_desc_cnt ¶: RX total Number of descriptors

uint32_t desc_len_byte ¶: RX Desc len in byte

uint32_t curr_desc_id ¶: RX current available Desc

uint32_t built_desc_id ¶: RX Built Desc

uint32_t buff_in_use ¶: Rx Buffers in Use

ETH common types definitions ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group4

struct hal_eth_fifo_event_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH FIFO Event Configuration structure definition.

Public Members

hal_eth_fifo_event_mode_t event_mode ¶: ETH FIFO Event Mode

uint32_t event_params ¶

Event parameter. The value could be one of the following :

Number of buffers to transfer by the DMA to trig the interruption when mode=HAL_ETH_FIFO_EVENT_CYCLIC.
or anything (to be ignored by the driver) when mode=HAL_ETH_FIFO_EVENT_ALWAYS or mode=HAL_ETH_FIFO_EVENT_NONE

struct hal_eth_tx_cb_pkt_data_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Tx Callback Data structure definition.

Public Members

uint32_t status ¶: ETH Transmission Status. This parameter can be a combination of ETH Tx channel status

uint32_t errors ¶: ETH Transmission Errors. This parameter can be a combination of ETH Tx channel errors

void * p_data ¶: Specifies Application packet pointer

struct hal_eth_rx_cb_pkt_data_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Rx Callback Packet Data structure definition.

Public Members

uint32_t status ¶: ETH Reception Status. This parameter can be a combination of ETH Rx channel status

uint32_t errors ¶: ETH Reception Errors. This parameter can be a combination of ETH Rx channel errors

void * p_data ¶: Specifies Application packet pointer

uint32_t vlan_tag_ids ¶: ETH Reception VLAN Tag ID. This parameter can be a value from 0x0 to 0xFFFF

ETH callbacks types definitions ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group5

Typedefs

typedef hal_status_t ( * hal_eth_tx_complete_cb_t ) ( hal_eth_handle_t * , uint32_t , void * , hal_eth_tx_cb_pkt_data_t ) ¶

Pointer to a function for handling Ethernet Tx completion events.

Function Signature

                   hal_status_t callback(hal_eth_handle_t *heth, uint32_t channel, void *p_buf,
                      hal_eth_tx_cb_pkt_data_t tx_pkt_data);

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle.
`uint32_t`	[in]	channel	Channel number.
`void *`	[in]	p_buf	Pointer to the transmitted buffer.
`hal_eth_tx_cb_pkt_data_t *`	[in]	tx_pkt_data	Packet-specific data for the Tx callback.

See also

HAL_ETH_ExecDataHandler

See also

hal_eth_tx_cb_pkt_data_t

See also

hal_eth_handle_t

Note

The p_tx_complete_cb callback is invoked in the following scenarios:

Peripheral De-Initialization: When HAL_ETH_DeInit is called to de-initialize the Ethernet peripheral, all allocated buffers and their metadata are released, and the transmission path is stopped.
Channel Stop: When HAL_ETH_StopChannel is called to stop the channel, all allocated buffers and their metadata are released, and the transmission path is stopped.
Data Handling: When HAL_ETH_ExecDataHandler is called to process transmitted data, transmitted frames and their metadata are returned to the application.

Note

If the application does not complete the callback execution successfully, the driver’s behavior will vary depending on the context:

Peripheral De-Initialization or Channel Stop: If the failure occurs during peripheral de-initialization or while stopping a channel, the driver will continue processing data for the affected channel and will release all resources associated with it. The application can choose to treat any unreleased resources as unusable for future Ethernet HAL driver operations.
Data Handling: If the failure occurs during data handling, the driver will suspend data processing for the affected channel. The index of this channel will be included in the list of output channels for which data handling was not completed (as returned by p_output_channel_mask parameter of HAL_ETH_ExecDataHandler. To resume data handling on the affected channel, invoke the HAL_ETH_ExecDataHandler API.

Retval HAL_OK :: Callback executed successfully.
Retval HAL_ERROR :: An error occurred during callback execution.

typedef hal_status_t ( * hal_eth_rx_complete_cb_t ) ( hal_eth_handle_t * , uint32_t , void * , uint32_t , hal_eth_rx_cb_pkt_data_t ) ¶

Pointer to a function for handling Ethernet Rx completion events.

Function Signature

                   hal_status_t callback(hal_eth_handle_t *heth, uint32_t channel, void *p_buf, uint32_t size,
                      hal_eth_rx_cb_pkt_data_t rx_pkt_data);

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle.
`uint32_t`	[in]	channel	Channel number.
`void *`	[in]	p_buf	Pointer to the received buffer.
`uint32_t`	[in]	size	Size of the received data in bytes.
`hal_eth_rx_cb_pkt_data_t *`	[in]	rx_pkt_data	Packet-specific data for the Rx callback.

See also

HAL_ETH_StopChannel

See also

HAL_ETH_ExecDataHandler

See also

hal_eth_rx_cb_pkt_data_t

See also

hal_eth_handle_t

Note

The p_rx_complete_cb callback is invoked in the following scenarios:

Peripheral De-Initialization: When HAL_ETH_DeInit is called to de-initialize the Ethernet peripheral, all allocated buffers and their metadata are released, and the reception path is stopped.
Channel Stop: When HAL_ETH_StopChannel is called to stop the channel, all allocated buffers and their metadata are released, and the reception path is stopped.
Data Handling: When HAL_ETH_ExecDataHandler is called to process received data, received frames and their metadata are returned to the application.

Note

If the application does not complete the callback execution successfully, the driver’s behavior will vary depending on the context:

Peripheral De-Initialization or Channel Stop: If the failure occurs during peripheral de-initialization or while stopping a channel, the driver will continue processing data for the affected channel and will return ownership (give back) of all resources associated with that channel to the application. The application can choose to treat any unreleased resources as unusable for future Ethernet HAL driver operations.
Data Handling: If the failure occurs during data handling, the driver will halt data processing for the affected channel. The index of this channel will be included in the list of output channels for which data handling was not completed (as returned by p_output_channel_mask parameter of HAL_ETH_ExecDataHandler. To resume data handling on the affected channel, invoke the HAL_ETH_ExecDataHandler API.

Retval HAL_OK :: Callback executed successfully.
Retval HAL_ERROR :: An error occurred during callback execution.

typedef void ( * hal_eth_rx_allocate_cb_t ) ( hal_eth_handle_t * , uint32_t , uint32_t , void * * , void * * ) ¶

Pointer to a function for allocating buffers for Ethernet Rx operations.

Function Signature

                   void callback(hal_eth_handle_t *heth, uint32_t channel, uint32_t size, void **p_buf, void **p_data);

                  

Buffer Allocation Behavior:

For the channel start scenario, if the application does not succeed in allocating a buffer for reception, the driver will stop building the list of initial buffers for the affected channel. The maximum number of buffers to be requested, as specified by the application during channel configuration, will be reduced to the number of buffers that were successfully allocated.
- Example: If the maximum number of buffers is set to 10 but the application is only able to allocate 3 buffers, the driver will use 3 as the new maximum for that channel.
For the data handling scenario, if the application does not succeed in allocating buffers for reception, the driver will halt data handling for the affected channel. The index of this channel will appear in the list of output channels where data handling was not completed. To resume data handling on the affected channel, call the HAL_ETH_ExecDataHandler() API.

Reception Path Requirements:

The driver requires at least 1 buffer to start the reception path; otherwise, the reception process will not be started.
The allocated memory must meet all constraints specified by the driver, such as memory address alignment and minimum size. These constraints are provided by the HAL_ETH_GetChannelAllocNeeds API, which must be called before making the allocation request.

Buffer Count Query:

The application can check the number of initial buffers that the driver will be using for the reception path by calling HAL_ETH_GetChannelBufferInUseCount() API immediately after starting the channel.

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle. hal_eth_handle_t
`uint32_t`	[in]	channel	Channel number.
`uint32_t`	[in]	size	Required buffer size in bytes.
`void **`	[out]	p_buf	Pointer to the allocated buffer.
`void **`	[out]	p_data	Pointer to the allocated buffer metadata.

See also

HAL_ETH_StartChannel

See also

HAL_ETH_ExecDataHandler

See also

HAL_ETH_GetChannelBufferInUseCount

See also

HAL_ETH_GetChannelAllocNeeds

See also

hal_eth_handle_t

Note

The p_rx_allocate_cb callback is invoked in the following scenarios:

Channel Start: When HAL_ETH_StartChannel() is called, the callback allocates initial buffers and prepares the reception path.
Data Handling: When HAL_ETH_ExecDataHandler() is called, the callback requests memory for upcoming reception requests.

typedef void ( * hal_eth_cb_t ) ( hal_eth_handle_t * , uint32_t ) ¶

Function pointer type for Ethernet event or error callbacks.

This type defines a pointer to a callback function that is invoked to handle generic Ethernet events or errors. The callback allows the application to respond to various Ethernet-related notifications, such as low power status changes, data events or peripheral error conditions.

Function Signature

                   void callback(hal_eth_handle_t *heth, uint32_t events);

                  

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle structure.
`uint32_t`	[in]	events	32-bit value containing a combination of event flags (bitwise ORed).

Associated Function Pointers This callback type is used to implement the following Ethernet driver callbacks:

p_data_cb: ETH Data Event Callback. The callback returns a bitwise ORed value for all channels that have a data event. The list of channels is provided in ETH Tx and Rx channel identifiers.
p_error_cb: ETH Error Callback The following Errors are supported:

Event	Description
HAL_ETH_ERROR_NONE	No error.
HAL_ETH_ERROR_FBE	Fatal Bus Error.
HAL_ETH_ERROR_CDE	Context Descriptor Error.
HAL_ETH_ERROR_FBE_DMA_TX_RD	Bus Fault Error during read transfer by Tx DMA
HAL_ETH_ERROR_FBE_DMA_TX_WR	Bus Fault Error during write transfer by Tx DMA
HAL_ETH_ERROR_FBE_DMA_TX_AC	Bus Fault Error during descriptor access by Tx DMA
HAL_ETH_ERROR_FBE_DMA_RX_RD	Bus Fault Error during read transfer by Rx DMA
HAL_ETH_ERROR_FBE_DMA_RX_WR	Bus Fault Error during write transfer by Rx DMA
HAL_ETH_ERROR_FBE_DMA_RX_AC	Bus Fault Error during descriptor access by Rx DMA

p_event_cb: ETH Event Callback. The following Peripheral Events are supported:

Event	Description
HAL_ETH_EVENT_MAC_RWT	Receive Watchdog Timeout Event.
HAL_ETH_EVENT_MAC_EXCOL	Excessive Collisions Event.
HAL_ETH_EVENT_MAC_LCOL	Late Collision Event.
HAL_ETH_EVENT_MAC_EXDEF	Excessive Deferral Event.
HAL_ETH_EVENT_MAC_LCARR	Loss of Carrier Event.
HAL_ETH_EVENT_MAC_NCARR	No Carrier Event.
HAL_ETH_EVENT_MAC_TJT	Transmit Jabber Timeout Event.

p_pmt_cb: ETH Power Management Callback The following Peripheral PMT Events are supported:

Event	Description
HAL_ETH_EVENT_PMT_MAGIC_PACKET	Magic Packet Received.
HAL_ETH_EVENT_PMT_RWK_PACKET	Remote wake-up Packet Received.

p_eee_cb: ETH EEE (Energy Efficient Ethernet) Callback The following Peripheral EEE/LPI Events are supported:

Event	Description
HAL_ETH_EVENT_LPI_PLS_DOWN	PHY Link Status is Down.
HAL_ETH_EVENT_LPI_PLS_UP	PHY Link Status is Up.
HAL_ETH_EVENT_LPI_TX_LPI_ST	Transmit LPI State Active.
HAL_ETH_EVENT_LPI_RX_LPI_ST	Receive LPI State Active.
HAL_ETH_EVENT_LPI_TX_LPI_EN	Transmit LPI State Entry performed.
HAL_ETH_EVENT_LPI_RX_LPI_EN	Receive LPI State Entry performed.
HAL_ETH_EVENT_LPI_TX_LPI_EX	Transmit LPI State Entry performed.
HAL_ETH_EVENT_LPI_RX_LPI_EX	Receive LPI State Entry performed.

See also

hal_eth_handle_t

See also

HAL_ETH_DataCallback

See also

HAL_ETH_ErrorCallback

See also

HAL_ETH_EventCallback

See also

HAL_ETH_PMTCallback

See also

HAL_ETH_EEECallback

Note

The interpretation of events value depends on the context in which the callback is invoked. Typically, it can be a bitmask or an enumerated value defined elsewhere in the driver.
The callback function is invoked in handler mode; therefore, it must execute quickly and must not perform any blocking operations.
If additional processing is required, it is recommended to defer such operations to a separate task or thread.

typedef void ( * hal_eth_wakeup_cb_t ) ( const hal_eth_handle_t * ) ¶

Function pointer type for Ethernet wakeup event callbacks.

This type defines a pointer to a callback function that is invoked to handle Ethernet wakeup events. The callback allows the application to respond when the Ethernet peripheral wakes up from a low-power state.

Function Signature

                   void callback(hal_eth_handle_t *heth);

                  

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle structure

See also

hal_eth_handle_t

See also

HAL_ETH_WakeUpCallback

Note

The callback function is invoked in handler mode; therefore, it must execute quickly and must not perform any blocking operations.
If additional processing is required, it is recommended to defer such operations to a separate task or thread.

typedef void ( * hal_eth_channel_cb_t ) ( hal_eth_handle_t * , uint32_t , uint32_t ) ¶

Function pointer type for Ethernet Tx/Rx channel event callbacks.

This type defines a pointer to a callback function that is invoked to handle events related to specific Ethernet transmit (Tx) or receive (Rx) channels. The callback allows the application to respond to channel-specific notifications, such as data transfer completions status or error conditions.

Function Signature

                   void callback(hal_eth_handle_t *heth, uint32_t channel, uint32_t events);

                  

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle structure
`uint32_t`	[in]	channel	Channel number (Tx or Rx) on which the event occurred.
`uint32_t`	[in]	events	32-bit value containing a combination of event flags (bitwise ORed).

Event	Description
HAL_ETH_CH_EVENT_DMA_RBU	Receive Buffer Unavailable.
HAL_ETH_CH_EVENT_DMA_TBU	Transmit Buffer Unavailable.
HAL_ETH_CH_EVENT_DMA_RWT	Receive Watchdog Timeout.
HAL_ETH_CH_EVENT_MTL_RX_OF	MTL Receive Queue Overflow.
HAL_ETH_CH_EVENT_MTL_TX_OF	MTL Transmit Queue Underflow.

See also

hal_eth_handle_t

See also

ETH channel event codes

See also

HAL_ETH_TxEventCallback

See also

HAL_ETH_RxEventCallback

Note

The following events are supported:

Note

The callback function can be invoked in handler mode; therefore, it must execute quickly and must not perform any blocking operations.
If additional processing is required, it is recommended to defer such operations to a separate task or thread.

typedef void ( * hal_eth_cache_cb_t ) ( hal_eth_handle_t * , uint32_t , void * , uint32_t ) ¶

Function pointer type for Ethernet cache flush/invalidate callbacks.

This type defines a pointer to a callback function that is invoked to handle cache maintenance operations (flush or invalidate) for the Ethernet driver shared memory associated with specific transmit (Tx) or receive (Rx) channel. The callback allows the application to ensure data coherency between the CPU and DMA by performing appropriate cache maintenance operations on the buffer.

Function Signature

                   void callback(hal_eth_handle_t *heth, uint32_t channel, void *p_buf, uint32_t size);

                  

Parameters:

Type	Dir	Name	Description
`hal_eth_handle_t *`	[in]	heth	Pointer to the Ethernet handle structure
`uint32_t`	[in]	channel	Channel number (Tx or Rx) for which the cache operation is performed.
`void *`	[in]	p_buf	Pointer to the data buffer that requires cache flush or invalidate.
`uint32_t`	[in]	size	Size of the data buffer in bytes.

Associated Function Pointers This callback type is used to implement the following Ethernet driver callbacks:

p_cache_invalidate_cb: ETH Cache Invalidate (Peripheral to CPU direction).
p_cache_flush_cb: ETH Cache Flush (CPU to Peripheral direction).

See also

hal_eth_handle_t

See also

HAL_ETH_CacheInvalidateCallback

See also

HAL_ETH_CacheFlushCallback

Note

Proper cache maintenance is essential to ensure data integrity when using cached memory.
Synchronized memory regions must be aligned to cache line boundaries, as specified by the channel configuration alignment requirements provided by the user.
The callback function can be invoked in handler mode; therefore, it must execute quickly and must not perform any blocking operations.
Cache maintenance operations must be completed before returning control to the callee, ensuring that synchronized memory is ready for the next execution.
The Invalidate() operation must be performed when ownership of the driver’s shared memory is transferred to the CPU.
The Flush() operation must be performed when ownership of the driver’s shared memory is transferred to the hardware. For optimal performance, consider using a CleanInvalidate instruction, as there will be no further CPU data reuse (read) until the driver’s shared memory is updated (write-back) by the Ethernet DMA hardware.

ETH peripheral configuration structures ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group6

struct hal_eth_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Peripheral Configuration structure definition.

Public Members

uint8_t mac_addr [ 6 ] ¶: MAC Address of used Hardware: must be pointer on an array of 6 bytes

hal_eth_media_interface_t media_interface ¶: Selects the Ethernet Media interface.

struct hal_eth_link_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Peripheral Auto-Negotiation Link Configuration structure definition. Auto-negotiation is a process between PHY layer devices that enables them to automatically exchange information about their capabilities, such as speed, duplex mode, and flow control. This allows both devices to select the highest performance mode supported by both ends of the link. The MAC is responsible for final Auto-Negotiation link configuration resolution after a link is established, and is responsible for correct flow control, energy efficient ethernet actions thereafter.

Public Members

hal_eth_mac_speed_t speed ¶: Sets the Ethernet speed: 10/100/1000 Mbps

hal_eth_mac_duplex_mode_t duplex_mode ¶: Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode

ETH MAC - DMA - MTL Sub-Blocks configuration structures ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group7

struct hal_eth_mac_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH MAC Configuration structure definition.

Public Members

hal_eth_link_config_t link_config ¶: Sets the Ethernet Link configuration

hal_eth_mac_loopback_ctrl_t loopback_mode ¶: Enables or disables the loopback mode

hal_eth_mac_src_addr_ctrl_t src_addr_ctrl ¶: Selects the Source Address Insertion or Replacement Control

hal_eth_mac_inter_pkt_gap_t inter_pkt_gap_value ¶: Sets the minimum IPG between Packet during transmission

hal_eth_mac_back_off_limit_t back_off_limit ¶: Selects the BackOff limit value

hal_eth_mac_preeamble_length_t preamble_length ¶: Selects or not the Preamble Length for Transmit packets (Full Duplex mode)

hal_eth_mac_gpkt_sz_limit_ctrl_t giant_pkt_size_limit_ctrl ¶: Enables or disables the Giant Packet Size Limit Control.

hal_eth_mac_2k_pkt_len_ctrl_t support_2K_pkt ¶: Enables or disables the IEEE 802.3as Support for 2K length Packets

hal_eth_mac_crc_strip_pkt_ctrl_t crc_strip_type_pkt ¶: Enables or disables the CRC stripping for Type packets.

hal_eth_mac_auto_pad_crc_s_ctrl_t auto_pad_crc_strip ¶: Enables or disables the Automatic MAC Pad/CRC Stripping.

hal_eth_mac_tx_jabber_tim_ctrl_t tx_jabber ¶: Enables or disables Jabber timer on Tx path.

hal_eth_mac_cs_before_tr_ctrl_t cs_before_transmit ¶: Enables or disables the Carrier Sense Before Transmission in Full Duplex mode

hal_eth_mac_cs_during_tr_ctrl_t cs_during_transmit ¶: Enables or disables the Carrier Sense During Transmission in the Half Duplex mode

hal_eth_mac_retry_tr_ctrl_t retry_transmission ¶: Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.

hal_eth_mac_rx_wd_tim_ctrl_t rx_watchdog ¶: Enables or disables the Watchdog timer on Rx path.

hal_eth_mac_rx_jumbo_pkt_ctrl_t rx_jumbo_pkt ¶: Enables or disables receiving Jumbo Packet When enabled, the MAC allows jumbo packets of 9,018 bytes without reporting a giant packet error

hal_eth_mac_rx_csum_pkt_ctrl_t rx_csum_offload ¶: Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers

hal_eth_mac_rx_receive_own_ctrl_t rx_receive_own ¶: Enables or disables the Receive Own in Half Duplex mode

hal_eth_mac_rx_crc_pkt_chk_ctrl_t crc_checking_rx_pkts ¶: Enable or disables the CRC Checking for Received Packets.

hal_eth_mac_deferral_check_ctrl_t deferral_check ¶: Enables or disables the deferral check function in Half Duplex mode.

hal_eth_mac_uc_slow_proto_ctrl_t uc_slow_proto_detect ¶: Enable or disables the Detection of Slow Protocol Packets with unicast address.

hal_eth_mac_slow_proto_ctrl_t slow_proto_detect ¶: Enable or disables the Slow Protocol Detection.

uint32_t giant_pkt_size_limit ¶: Specifies the packet size that the MAC will declare it as Giant, If it’s size is greater than the value programmed in this field in This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte).

hal_eth_mac_ex_int_pkt_gap_ctrl_t ext_inter_pkt_gap_ctrl ¶: Enable or disables the extended inter packet gap.

uint32_t ext_inter_pkt_gap ¶: Sets the Extended IPG between Packet during transmission. This parameter can be a value from 0x0 to 0xFF

hal_eth_mac_prog_wd_ctrl_t programmable_wd ¶: Enable or disables the Programmable Watchdog.

hal_eth_mac_rx_wd_timeout_t rx_wd_timeout_byte ¶: This field is used as watchdog timeout for a received packet

uint32_t tx_pause_time ¶: This field holds the value to be used in the Pause Time field in the transmit control packet. This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF.

hal_eth_mac_zero_q_pause_ctrl_t zero_quanta_pause ¶: Enable or disables the automatic generation of Zero Quanta Pause Control packets.

hal_eth_mac_pause_low_thr_t pause_low_threshold ¶: This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet

hal_eth_mac_tr_flow_ctrl_t tr_flow_ctrl ¶: Enables or disables the MAC to transmit Pause packets in Full Duplex mode or the MAC back pressure operation in Half Duplex mode

hal_eth_mac_uc_pause_pkt_ctrl_t uc_pause_pkt_detect ¶: Enables or disables the MAC to detect Pause packets with unicast address of the station

hal_eth_mac_receive_flow_ctrl_t receive_flow_ctrl ¶: Enables or disables the MAC to decodes the received Pause packet and disables its transmitter for a specified (Pause) time

struct hal_eth_dma_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH DMA Configuration Structure definition.

Public Members

hal_eth_dma_addr_align_ctrl_t addr_aligned_beats ¶: Enables or disables the Peripheral Bus Master interface address aligned burst transfers on Read and Write channels

hal_eth_dma_burst_len_mode_t burst_mode ¶: Sets the Peripheral Bus Master interface burst transfers length mode

hal_eth_dma_mixed_burst_ctrl_t mixed_burst ¶: Sets the maximum outstanding request on the System Bus read interface

hal_eth_dma_rebuild_inc_ctrl_t rebuild_inc_burst ¶: Sets the maximum outstanding request on the System Bus read interface

hal_eth_dma_tr_prio_ctrl_t tr_priority ¶: Sets Transmit priority over Receive

struct hal_eth_dma_tx_channel_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH DMA Tx Configuration Structure definition.

Public Members

hal_eth_dma_tx_pbl_x8_mode_ctrl_t tx_pbl_x8_mode ¶: Enables or disables the PBL multiplication by eight.

hal_eth_dma_tx_burst_length_t tx_dma_burst_length ¶: Indicates the maximum number of beats to be transferred in one Tx DMA transaction

hal_eth_dma_tx_sec_pkt_op_ctrl_t tx_second_pkt_operate ¶: Enables or disables the Operate on second Packet mode, which allows the DMA to process a second Packet of Transmit data even before obtaining the status for the first one.

struct hal_eth_dma_rx_channel_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH DMA Rx Configuration Structure definition.

Public Members

hal_eth_dma_rx_burst_length_t rx_dma_burst_length ¶: Indicates the maximum number of beats to be transferred in one Rx DMA transaction

uint32_t rx_buffer_len_byte ¶: Provides the length of Rx buffers size in byte unit

struct hal_eth_mtl_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH MTL Configuration Structure definition.

Public Members

hal_eth_mtl_tx_fwd_status_ctrl_t tx_fwd_status ¶: Enables or disables forwarding Tx Packet Status to the application.

struct hal_eth_mtl_tx_queue_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH MTL Tx Queue Configuration Structure definition.

Public Members

hal_eth_mtl_tx_ops_mode_t queue_op_mode ¶: Specifies the Tx Queue operating mode

hal_eth_mtl_tx_queue_size_t queue_size_byte ¶: Specifies the Tx Queue Size

hal_eth_mtl_tx_transmit_mode_t transmit_queue_mode ¶: Specifies the Transmit Queue operating mode

struct hal_eth_mtl_rx_queue_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH MTL Rx Queue Configuration Structure definition.

Public Members

hal_eth_mtl_rx_ops_mode_t queue_op_mode ¶: Specifies the Rx Queue operating mode

hal_eth_mtl_rx_queue_size_t queue_size_byte ¶: Specifies the Rx Queue Size

hal_eth_mtl_rx_drop_cs_err_ctrl_t drop_tcp_ip_csum_error_pkt ¶: Enables or disables Dropping of TCPIP Checksum Error Packets

hal_eth_mtl_rx_fwd_err_pkt_ctrl_t fwd_error_pkt ¶: Enables or disables forwarding Error Packets.

hal_eth_mtl_rx_fwd_usz_pkt_ctrl_t fwd_undersized_good_pkt ¶: Enables or disables forwarding Undersized Good Packets.

hal_eth_mtl_rx_queue_mode_t receive_queue_mode ¶: Specifies the Receive Queue operating mode

ETH channels configuration structures ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group8

struct hal_eth_tx_channel_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Tx Channel Configuration Structure definition.

Public Members

uint32_t max_app_buffers_num ¶: Provides the Maximum number of Application Buffers to be hold in the DMA FIFO

uint32_t req_desc_size_align_byte ¶

Provides the Application requested memory size alignment in bytes. The application can request specific memory size alignment to implement proper CACHE maintenance

See also

hal_eth_cache_cb_t callback.

If the requested size alignment is zero then the driver request the alignment according to its own constraints.
Otherwise, the driver will use size alignment value which respect both descriptor size alignment and requested size alignment conditions.

hal_eth_dma_tx_channel_config_t dma_channel_config ¶: DMA Tx Channel Configuration

hal_eth_mtl_tx_queue_config_t mtl_queue_config ¶: MTL Tx Queue Configuration

hal_eth_fifo_event_config_t fifo_event_config ¶: FIFO event Configuration

struct hal_eth_rx_channel_config_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Rx Channel Configuration Structure definition.

Public Members

uint32_t max_app_buffers_num ¶: Provides the Maximum number of Application Buffers to be hold in the DMA FIFO

uint32_t req_desc_size_align_byte ¶

Provides the Application requested descriptor memory size alignment in bytes. The application can request specific descriptor size alignment to implement proper CACHE maintenance

See also

hal_eth_cache_cb_t callback.

If the requested size alignment is zero then the driver will not align the descriptor size.
Otherwise, the driver will use size alignment value which respect both descriptor size alignment and requested size aligenement conditions.

hal_eth_dma_rx_channel_config_t dma_channel_config ¶: DMA Rx Channel Configuration

hal_eth_mtl_rx_queue_config_t mtl_queue_config ¶: MTL Rx Queue Configuration

hal_eth_fifo_event_config_t fifo_event_config ¶: FIFO event Configuration

struct hal_eth_channel_alloc_needs_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Channel Memory Allocation Requirements Structure definition.

Public Members

uint32_t mem_size_byte ¶: Provides the minimal Size required by the driver

uint32_t mem_addr_align_byte ¶: Provides the minimum alignment for memory to be used by the driver

struct hal_eth_buffer_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Buffers List structure definition.

Public Members

void * p_buffer ¶: The ETH Frame buffer memory

uint32_t len_byte ¶: The ETH Frame buffer length in bytes

ETH channels process and I/O structures ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group9

struct hal_eth_tx_pkt_config_t ¶

#include <stm32c5xx_hal_eth.h>

Transmit Packet Configuration structure definition.

Public Members

uint32_t attributes ¶: Tx packet HW features capabilities. This parameter can be a combination of Ethernet Tx Packet Control Attributes

hal_eth_tx_pkt_src_addr_ctrl_t src_addr_ctrl ¶: Specifies the source address insertion control

hal_eth_tx_pkt_crc_pad_ctrl_t crc_pad_ctrl ¶: Specifies the CRC and Pad insertion and replacement control

hal_eth_tx_pkt_csum_ctrl_t csum_ctrl ¶: Specifies the checksum insertion control

uint16_t vlan_tag_id ¶: Sets VLAN Tag ID only when VLAN is enabled. This parameter can be a value from 0x0 to 0xFFFF

hal_eth_tx_pkt_vlan_ctrl_t vlan_ctrl ¶: Specifies VLAN Tag insertion control only when VLAN is enabled

uint32_t inner_vlan_tag_id ¶: Sets Inner VLAN Tag ID only when Inner VLAN is enabled. This parameter can be a value from 0x0 to 0x3FFFF

hal_eth_tx_pkt_inner_vlan_ctrl_t inner_vlan_ctrl ¶: Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled

void * p_data ¶: Specifies Application packet pointer to save for completion notification

hal_eth_tx_pkt_notify_ctrl_t notify ¶: Enable or Disable notification for this packet transmit request

ETH peripheral power management structures ¶

Note

This section is not available for STM32C562xx.

group ETH_Exported_Types_Group10

struct hal_eth_rwk_pkt_filter_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Remote Wakeup Packet Filter structure definition.

This structure defines a single remote wakeup packet filter used by the Ethernet peripheral. Each filter can be configured to match specific packet patterns and control the filter logic using a combination of mask, offset, CRC, and command bits.

The 4-bit command field uses the following constants to control filter behavior:

HAL_ETH_RWK_FLT_CMD_ENABLE : Enable or disable the filter.
HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS : AND logic with the previous filter for extended pattern matching.
HAL_ETH_RWK_FLT_CMD_INVERSE_MODE : Inverse mode for CRC16 hash function (reject on match).
HAL_ETH_RWK_FLT_CMD_MULTICAST : Apply filter to multicast or unicast packets.

See also

HAL_ETH_RWK_FLT_CMD_ENABLE

See also

HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS

See also

HAL_ETH_RWK_FLT_CMD_INVERSE_MODE

See also

HAL_ETH_RWK_FLT_CMD_MULTICAST

See also

HAL_ETH_SetRemoteWakeUpPcktFilter

Public Members

uint32_t byte_mask ¶

Filter 32-bit Mask.

Each bit in the mask corresponds to one byte in the detected packet.

If a bit is set to 1, the corresponding byte is included in the CRC16 calculation.
The MSB (31st bit) must be zero.
Bits [30:0] represent the byte mask.
If bit j is set, the CRC block processes the (offset + j)th byte of the incoming packet. Otherwise, that byte is ignored.

uint8_t commands ¶

Filter 4-bit command stored in bits [3:0].

The 4-bit command controls the filter operation:

Bit 3 (HAL_ETH_RWK_FLT_CMD_MULTICAST): Address type. Set for multicast, reset for unicast.
Bit 2 (HAL_ETH_RWK_FLT_CMD_INVERSE_MODE): Inverse mode. Set to reject packets with matching CRC16.
Bit 1 (HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS): AND logic with previous filter for extended patterns.
Bit 0 (HAL_ETH_RWK_FLT_CMD_ENABLE): Enable filter. If not set, the filter is disabled.

Use the defined constants to set or clear these bits.

uint8_t offsets ¶

Filter 8-bit Offset pattern.

Defines the offset (within the packet) from which the filter examines the bytes.

This 8-bit value is the offset for the filter’s first byte to be examined.
The minimum allowed offset is 12 (refers to the 13th byte of the packet).
An offset value of 0 refers to the first byte of the packet.

uint16_t crc16 ¶

Filter CRC-16 value.

Contains the CRC-16 value calculated from the pattern and the byte mask.

The 16-bit CRC calculation uses the polynomial: G(x) = x^16 + x^15 + x^2 + 1.
Each filter compares the computed CRC16 with this value for packet matching.
The mask and offset together determine which bytes are used in the CRC16 calculation.

struct hal_eth_rwk_filter_block_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Remote Wakeup Packet Filter Block structure definition.

This structure represents a block of remote wakeup packet filters for the Ethernet peripheral. Each block contains a fixed number of filters, as defined by HAL_ETH_RWK_FILT_PER_BLOCK.

The hardware arranges remote wake-up filters in blocks, with each block containing four filters. Each filter is described by hal_eth_rwk_pkt_filter_t and can be individually configured.

Register Layout for Each Block:

                  | Register Name      | Description                                             |
|--------------------|--------------------------------------------------------|
| BYTE MASK (0)      | Filter #0 byte mask  [30:0]                            |
| BYTE MASK (1)      | Filter #1 byte mask  [30:0]                            |
| BYTE MASK (2)      | Filter #2 byte mask  [30:0]                            |
| BYTE MASK (3)      | Filter #3 byte mask  [30:0]                            |
| FILT_CMDS [0..3]   | FILT_3 CMD | FILT_2 CMD | FILT_1 CMD | FILT_0 CMD      |
| FILT_OFFSET [0..3] | FILT_3 OFFSET | FILT_2 OFFSET | FILT_1 OFFSET | FILT_0 OFFSET |
| FILT_CRC [1..0]    | FILT_1 CRC 16bits | FILT_0 CRC 16bits                  |
| FILT_CRC [3..2]    | FILT_3 CRC 16bits | FILT_2 CRC 16bits                  |

                 

The number of filters per block is defined by HAL_ETH_RWK_FILT_PER_BLOCK.
The maximum number of filter blocks is defined by HAL_ETH_RWK_FILT_BLOCK_NUM.
Each filter in the block uses the command constants:

See also

hal_eth_rwk_pkt_filter_t

See also

HAL_ETH_RWK_FILT_PER_BLOCK

See also

HAL_ETH_RWK_FILT_BLOCK_NUM

See also

HAL_ETH_RWK_FLT_CMD_ENABLE

See also

HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS

See also

HAL_ETH_RWK_FLT_CMD_INVERSE_MODE

See also

HAL_ETH_RWK_FLT_CMD_MULTICAST

See also

HAL_ETH_SetRemoteWakeUpPcktFilter

Public Members

hal_eth_rwk_pkt_filter_t filter [ ( 4U ) ] ¶

Array of remote wakeup packet filters in this block.

Each filter is defined by hal_eth_rwk_pkt_filter_t and can be individually configured. The number of filters in the block is given by HAL_ETH_RWK_FILT_PER_BLOCK.

struct hal_eth_rwk_filter_lut_t ¶

#include <stm32c5xx_hal_eth.h>

ETH Remote Wakeup Packet Filters Lookup Table (LUT) structure definition.

This structure represents the lookup table (LUT) for all remote wakeup packet filter blocks supported by the Ethernet peripheral. Each LUT contains one or more filter blocks, and each block contains multiple filters.

The number of filter blocks in the LUT is defined by HAL_ETH_RWK_FILT_BLOCK_NUM. Each block is represented by hal_eth_rwk_filter_block_t, which contains HAL_ETH_RWK_FILT_PER_BLOCK filters of type hal_eth_rwk_pkt_filter_t.

LUT Layout for N Blocks:

                  |--------------------------|-----------------------------------------------|
|      Filter Block #0     | Data for block 0 (see @ref hal_eth_rwk_filter_block_t) |
|--------------------------|-----------------------------------------------|
|      Filter Block #1     | Data for block 1                              |
|--------------------------|-----------------------------------------------|
|           ...            | ...                                           |
|--------------------------|-----------------------------------------------|
|      Filter Block #N     | Data for block N                              |
|--------------------------|-----------------------------------------------|

                 