HAL I3C constants

Error code definition

group I3C_ERROR_CODE_DEFINITION

Defines

HAL_I3C_ERROR_NONE (0x00000000U)

0x0 No error

HAL_I3C_CTRL_ERROR_0 ( LL_I3C_CONTROLLER_ERROR_CE0 | I3C_SER_PERR)

0x10 \ Controller detected an illegally formatted CCC

HAL_I3C_CTRL_ERROR_1 ( LL_I3C_CONTROLLER_ERROR_CE1 | I3C_SER_PERR)

0x11 \ Controller detected that transmitted data on the bus is different from expected

HAL_I3C_CTRL_ERROR_2 ( LL_I3C_CONTROLLER_ERROR_CE2 | I3C_SER_PERR)

0x12 \ Controller detected an unacknowledged broadcast address 7’h7E

HAL_I3C_CTRL_ERROR_3 ( LL_I3C_CONTROLLER_ERROR_CE3 | I3C_SER_PERR)

0x13 Controller detected the new controller did not drive bus after controller-role hand-off

HAL_I3C_TGT_ERROR_0 ( LL_I3C_TARGET_ERROR_TE0 | I3C_SER_PERR)

0x18 \ Target detected an invalid broadcast address 7’h7E + W

HAL_I3C_TGT_ERROR_1 ( LL_I3C_TARGET_ERROR_TE1 | I3C_SER_PERR)

0x19 \ Target detected a parity error on a CCC code via a parity check (vs. T bit)

HAL_I3C_TGT_ERROR_2 ( LL_I3C_TARGET_ERROR_TE2 | I3C_SER_PERR)

0x1A \ Target detected a parity error on a write data via a parity check (vs. T bit)

HAL_I3C_TGT_ERROR_3 ( LL_I3C_TARGET_ERROR_TE3 | I3C_SER_PERR)

0x1B \ Target detected a parity error on the assigned address during dynamic address \ arbitration via a parity check (vs. PAR bit)

HAL_I3C_TGT_ERROR_4 ( LL_I3C_TARGET_ERROR_TE4 | I3C_SER_PERR)

0x1C \ Target detected a 7’h7E + R missing after Sr during dynamic address arbitration

HAL_I3C_TGT_ERROR_5 ( LL_I3C_TARGET_ERROR_TE5 | I3C_SER_PERR)

0x1D \ Target detected an illegally formatted CCC

HAL_I3C_TGT_ERROR_6 ( LL_I3C_TARGET_ERROR_TE6 | I3C_SER_PERR)

0x1E \ Target detected that transmitted data on the bus is different from expected

HAL_I3C_TGT_ERROR_STALL LL_I3C_SER_STALL

0x20 \ Target detected that SCL was stable for more than 125 microsecond during \ an I3C SDR data read (during a direct CCC read, a private read, or an IB)

HAL_I3C_ERROR_DOVR LL_I3C_SER_DOVR

0x40 \ Rx FIFO over-run or Tx FIFO under-run

HAL_I3C_ERROR_COVR LL_I3C_SER_COVR

0x80 \ S FIFO over-run or C FIFO under-run

HAL_I3C_ERROR_ADDRESS_NACK LL_I3C_SER_ANACK

0x100 \ Address not acknowledged

HAL_I3C_ERROR_DATA_NACK LL_I3C_SER_DNACK

0x200 \ Data not acknowledged

HAL_I3C_ERROR_DATA_HAND_OFF LL_I3C_SER_DERR

0x400 \ Data error during Controller-Role hand-off. Active controller keeps \ controller-role

HAL_I3C_ERROR_DMA 0x00010000U

0x10000 \ DMA transfer error

HAL_I3C_ERROR_DYNAMIC_ADDR 0x00020000U

0x20000 \ Dynamic address error

Stall feature definition

group I3C_CTRL_STALL_FEATURE_DEFINITION

Optional controller clock stall insertion points on the I3C/I2C bus.

Each define enables a programmable pause on a specific protocol phase to allow targets extra time (e.g. internal processing, data fetch) before the controller continues toggling SCL. These bits map to timing register fields (TIMINGR2) and must be used sparingly to avoid throughput degradation.

Defines

HAL_I3C_CTRL_STALL_ACK LL_I3C_CTRL_STALL_ACK

Inserts a stall after each address or data byte ACK/NACK extend target processing time.

HAL_I3C_CTRL_STALL_CCC LL_I3C_CTRL_STALL_CCC

Inserts a stall on the parity (T) bit phase of a direct/broadcast CCC so targets can decode the opcode before data phase.

HAL_I3C_CTRL_STALL_TX LL_I3C_CTRL_STALL_TX

Inserts a stall on the parity (T) bit of transmitted data allowing target additional time to latch received byte.

HAL_I3C_CTRL_STALL_RX LL_I3C_CTRL_STALL_RX

Inserts a stall before the controller samples target data (read path) so target can prepare next byte.

HAL_I3C_CTRL_STALL_I2C_ACK LL_I3C_CTRL_STALL_I2C_ACK

Inserts a stall after address ACK/NACK in legacy I2C read/write so target can prepare for next phase.

HAL_I3C_CTRL_STALL_I2C_TX LL_I3C_CTRL_STALL_I2C_TX

Inserts a stall after data ACK/NACK in legacy I2C write allowing target to process/write incoming byte.

HAL_I3C_CTRL_STALL_I2C_RX LL_I3C_CTRL_STALL_I2C_RX

Inserts a stall after data ACK/NACK in legacy I2C read allowing target to load the next byte to transmit.

HAL_I3C_CTRL_STALL_ALL LL_I3C_CTRL_STALL_ALL

Enable all stall points.

HAL_I3C_CTRL_STALL_NONE LL_I3C_CTRL_STALL_NONE

Disable all stall insertion (default high throughput).