HAL TIM Types

HAL TIM Types

STM32C562xx STM32C5A3xx STM32C542xx

group TIM_Exported_Types

Typedefs

typedef struct hal_tim_handle_s hal_tim_handle_t

HAL TIM Time Base Handle type definition.

typedef void ( * hal_tim_cb_t ) ( hal_tim_handle_t * )

HAL TIM generic callback pointer definition

typedef void ( * hal_tim_channel_cb_t ) ( hal_tim_handle_t * , hal_tim_channel_t )

HAL TIM callback pointer definition with channel parameter

typedef void ( * hal_tim_break_cb_t ) ( hal_tim_handle_t * , hal_tim_break_input_id_t )

HAL TIM callback pointer definition with break input parameter

Enums

enum hal_tim_t

HAL TIM instance.

Values:

enumerator HAL_TIM1

enumerator HAL_TIM2

enumerator HAL_TIM5

enumerator HAL_TIM6

enumerator HAL_TIM7

enumerator HAL_TIM8

enumerator HAL_TIM12

enumerator HAL_TIM15

enumerator HAL_TIM16

enumerator HAL_TIM17

enum hal_tim_state_t

HAL TIM Global States definition.

Values:

enumerator HAL_TIM_STATE_RESET

Peripheral not yet initialized

enumerator HAL_TIM_STATE_INIT

Peripheral initialized but not yet configured

enumerator HAL_TIM_STATE_IDLE

Peripheral initialized and a global config applied

enumerator HAL_TIM_STATE_ACTIVE

Counter is running

enumerator HAL_TIM_STATE_ACTIVE_SILENT

enum hal_tim_channel_state_t

TIM Channel States definition.

Values:

enumerator HAL_TIM_CHANNEL_STATE_RESET

TIM Channel initial state

enumerator HAL_TIM_OC_CHANNEL_STATE_IDLE

TIM Channel ready for use as output channel

enumerator HAL_TIM_OC_CHANNEL_STATE_ACTIVE

An internal process is ongoing on the TIM output channel

enumerator HAL_TIM_OC_CHANNEL_STATE_ACTIVE_SILENT

An internal process is ongoing on the TIM output channel in DMA silent mode

enumerator HAL_TIM_IC_CHANNEL_STATE_IDLE

TIM Channel ready for use as input channel

enumerator HAL_TIM_IC_CHANNEL_STATE_ACTIVE

An internal process is ongoing on the TIM input channel

enumerator HAL_TIM_IC_CHANNEL_STATE_ACTIVE_SILENT

An internal process is ongoing on the TIM input channel in DMA silent mode

enum hal_tim_channel_t

HAL TIM Channels identifier definition.

Values:

enumerator HAL_TIM_CHANNEL_1

Timer input/output channel 1

enumerator HAL_TIM_CHANNEL_2

Timer input/output channel 2

enumerator HAL_TIM_CHANNEL_3

Timer input/output channel 3

enumerator HAL_TIM_CHANNEL_4

Timer input/output channel 4

enumerator HAL_TIM_CHANNEL_5

Timer output channel 5

enumerator HAL_TIM_CHANNEL_6

Timer output channel 6

enumerator HAL_TIM_CHANNEL_7

Timer output channel 7

enumerator HAL_TIM_CHANNEL_1N

Timer complementary output channel 1

enumerator HAL_TIM_CHANNEL_2N

Timer complementary output channel 2

enumerator HAL_TIM_CHANNEL_3N

Timer complementary output channel 3

enumerator HAL_TIM_CHANNEL_4N

Timer complementary output channel 4

enum hal_tim_counter_mode_t

HAL TIM Counter Mode.

Values:

enumerator HAL_TIM_COUNTER_UP

Counter used as up-counter Counter used as upcounter

enumerator HAL_TIM_COUNTER_DOWN

Counter used as down-counter 0x00000010 DIR (Direction) Counter used as downcounter

enumerator HAL_TIM_COUNTER_CENTER_DOWN

Center-aligned mode 1 0x00000020 The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

enumerator HAL_TIM_COUNTER_CENTER_UP

Center-aligned mode 2 0x00000040 The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

enumerator HAL_TIM_COUNTER_CENTER_UP_DOWN

Center-aligned mode 3 0x00000060 CMS[1:0] bits (Center-aligned mode selection) The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

enum hal_tim_dts_prescaler_t

TIM DTS Clock Prescaler.

Values:

enumerator HAL_TIM_DTS_DIV1

tDTS=tTIM_KER_CK tDTS=tTIM_KER_CK

enumerator HAL_TIM_DTS_DIV2

tDTS=2*tTIM_KER_CK 0x00000100 tDTS=2*tTIM_KER_CK

enumerator HAL_TIM_DTS_DIV4

tDTS=4*tTIM_KER_CK 0x00000200 tDTS=4*tTIM_KER_CK

enumerator HAL_TIM_DTS_DIV8

tDTS=8*tTIM_KER_CK tDTS=8*tTIM_KER_CK

enum hal_tim_dts2_prescaler_t

TIM DTS2 Clock Prescaler.

Values:

enumerator HAL_TIM_DTS2_DIV1

tDTS2=tDTS tDTS2=tDTS

enumerator HAL_TIM_DTS2_DIV4

tDTS2=4*tDTS 0x01000000 tDTS2=4*tDTS

enumerator HAL_TIM_DTS2_DIV16

tDTS2=16*tDTS 0x02000000 tDTS2=16*tDTS

enumerator HAL_TIM_DTS2_DIV64

tDTS2=64*tDTS tDTS2=64*tDTS

enumerator HAL_TIM_DTS2_DIV256

tDTS2=256*tDTS 0x04000000 tDTS2=256*tDTS

enumerator HAL_TIM_DTS2_DIV1024

tDTS2=1024*tDTS tDTS2=1024*tDTS

enumerator HAL_TIM_DTS2_DIV4096

tDTS2=4096*tDTS tDTS2=4096*tDTS

enumerator HAL_TIM_DTS2_DIV16384

tDTS2=16384*tDTS tDTS2=16384*tDTS

enumerator HAL_TIM_DTS2_DIV65536

tDTS2=65536*tDTS 0x08000000 tDTS2=65536*tDTS

enumerator HAL_TIM_DTS2_DIV262144

tDTS2=262144*tDTS tDTS2=262144*tDTS

enum hal_tim_clk_src_t

HAL TIM Clock Source definition.

Values:

enumerator HAL_TIM_CLK_INTERNAL

Internal clock source (timer kernel clock) The timer is clocked by the internal clock provided from the RCC

enumerator HAL_TIM_CLK_EXTERNAL_MODE1

External clock source mode 1 Counter counts at each rising or falling edge on a selected input

enumerator HAL_TIM_CLK_EXTERNAL_MODE2

External clock source mode 2 0x00004000 ECE (External clock enable) Counter counts at each rising or falling edge on the external trigger input ETR

enumerator HAL_TIM_CLK_ENCODER_X1_TI1

Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P

enumerator HAL_TIM_CLK_ENCODER_X1_TI2

Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC2P Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P

enumerator HAL_TIM_CLK_ENCODER_X2_TI1

Quadrature encoder mode 1: x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level 0x00000001 Quadrature encoder mode 1: x2 mode, Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

enumerator HAL_TIM_CLK_ENCODER_X2_TI2

Quadrature encoder mode 2: x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level 0x00000002 Quadrature encoder mode 2: x2 mode, Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

enumerator HAL_TIM_CLK_ENCODER_X4_TI12

Quadrature encoder mode 3: x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input Quadrature encoder mode 3: x4 mode, Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input

enumerator HAL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1

Quadrature encoder with built-in debouncer: x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level 0x00020000 Quadrature encoder with built-in debouncer: x2 mode, Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

enumerator HAL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12

Quadrature encoder with built-in debouncer: x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input Quadrature encoder with built-in debouncer:x4 mode, Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input

enumerator HAL_TIM_CLK_ENCODER_CLK_PLUS_X2

Encoder mode: Clock plus direction, x2 mode Encoder mode: Clock plus direction, x2 mode

enumerator HAL_TIM_CLK_ENCODER_CLK_PLUS_X1

Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P Encoder mode:Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P

enumerator HAL_TIM_CLK_ENCODER_DIR_CLK_X2

Encoder mode: Directional Clock, x2 mode Encoder mode: Directional Clock, x2 mode

enumerator HAL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12

Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P

enum hal_tim_trig_sel_t

HAL TIM Trigger Selection.

Values:

enumerator HAL_TIM_TRIG_ITR0

Internal Trigger 0 (ITR0) Internal Trigger 0 (ITR0) is used as trigger input

enumerator HAL_TIM_TRIG_ITR1

Internal Trigger 1 (ITR1) 0x00000010 Internal Trigger 1 (ITR1) is used as trigger input

enumerator HAL_TIM_TRIG_ITR2

Internal Trigger 2 (ITR2) 0x00000020 Internal Trigger 2 (ITR2) is used as trigger input

enumerator HAL_TIM_TRIG_ITR5

Internal Trigger 5 (ITR5) Internal Trigger 5 (ITR5) is used as trigger input

enumerator HAL_TIM_TRIG_ITR6

Internal Trigger 6 (ITR6) Internal Trigger 6 (ITR6) is used as trigger input

enumerator HAL_TIM_TRIG_ITR7

Internal Trigger 7 (ITR7) Internal Trigger 7 (ITR7) is used as trigger input

enumerator HAL_TIM_TRIG_ITR8

Internal Trigger 8 (ITR8) Internal Trigger 8 (ITR8) is used as trigger input

enumerator HAL_TIM_TRIG_ITR9

Internal Trigger 9 (ITR9) Internal Trigger 9 (ITR9) is used as trigger input

enumerator HAL_TIM_TRIG_ITR10

Internal Trigger 10 (ITR10) Internal Trigger 10 (ITR10) is used as trigger input

enumerator HAL_TIM_TRIG_ITR11

Internal Trigger 11 (ITR11) Internal Trigger 11 (ITR11) is used as trigger input

enumerator HAL_TIM_TRIG_TI1F_ED

Timer Input 1 Edge Detector (TI1F_ED) 0x00000040 TI1 Edge Detector (TI1F_ED) is used as trigger input

enumerator HAL_TIM_TRIG_TI1FP1

Filtered Timer Input 1 (TI1FP1) Filtered Timer Input 1 (TI1FP1) is used as trigger input

enumerator HAL_TIM_TRIG_TI2FP2

Filtered Timer Input 2 (TI2FP2) Filtered Timer Input 2 (TI12P2) is used as trigger input

enumerator HAL_TIM_TRIG_ETRF

Filtered External Trigger input (ETRF) Filtered external Trigger (ETRF) is used as trigger input

enum hal_tim_update_generation_status_t

HAL TIM Update Event Generation Status.

Values:

enumerator HAL_TIM_UPDATE_GENERATION_DISABLED

Update event is not generated

enumerator HAL_TIM_UPDATE_GENERATION_ENABLED

Update event is generated as per configured update event source

enum hal_tim_update_src_t

Update Event Source.

Values:

enumerator HAL_TIM_UPDATE_REGULAR

Update event is generated when:

• The counter reaches overflow/underflow

• The TIMx_EGR.UG bit is set by software

• An internal/external trigger is active (through the slave mode controller) Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

enumerator HAL_TIM_UPDATE_COUNTER

Update event is generated only when the counter reaches overflow/underflow 0x00000004 URS (Update request source) Only counter overflow/underflow generates an update request

enum hal_tim_update_flag_remap_status_t

HAL TIM Update Flag Remap Status.

Values:

enumerator HAL_TIM_UPDATE_FLAG_REMAP_DISABLED

UIF status bit is not copied to TIMx_CNT register bit 31

enumerator HAL_TIM_UPDATE_FLAG_REMAP_ENABLED

UIF status bit is copied to TIMx_CNT register bit 31

enum hal_tim_auto_reload_preload_status_t

HAL TIM Auto-Reload Preload Status.

Values:

enumerator HAL_TIM_AUTO_RELOAD_PRELOAD_DISABLED

TIMx_ARR register is not preloaded

enumerator HAL_TIM_AUTO_RELOAD_PRELOAD_ENABLED

TIMx_ARR register is preloaded

enum hal_tim_filter_t

HAL TIM Digital Filter.

Values:

enumerator HAL_TIM_FDIV1

No filter, sampling is done at fDTS

enumerator HAL_TIM_FDIV1_N2

fSAMPLING=fTIM_KER_CK, N=2

enumerator HAL_TIM_FDIV1_N4

fSAMPLING=fTIM_KER_CK, N=4

enumerator HAL_TIM_FDIV1_N8

fSAMPLING=fTIM_KER_CK, N=8

enumerator HAL_TIM_FDIV2_N6

fSAMPLING=fDTS/2, N=6

enumerator HAL_TIM_FDIV2_N8

fSAMPLING=fDTS/2, N=8

enumerator HAL_TIM_FDIV4_N6

fSAMPLING=fDTS/4, N=6

enumerator HAL_TIM_FDIV4_N8

fSAMPLING=fDTS/4, N=8

enumerator HAL_TIM_FDIV8_N6

fSAMPLING=fDTS/8, N=6

enumerator HAL_TIM_FDIV8_N8

fSAMPLING=fDTS/8, N=8

enumerator HAL_TIM_FDIV16_N5

fSAMPLING=fDTS/16, N=5

enumerator HAL_TIM_FDIV16_N6

fSAMPLING=fDTS/16, N=6

enumerator HAL_TIM_FDIV16_N8

fSAMPLING=fDTS/16, N=8

enumerator HAL_TIM_FDIV32_N5

fSAMPLING=fDTS/32, N=5

enumerator HAL_TIM_FDIV32_N6

fSAMPLING=fDTS/32, N=6

enumerator HAL_TIM_FDIV32_N8

fSAMPLING=fDTS/32, N=8

enum hal_tim_oc_compare_unit_t

HAL TIM Output Compare Unit identifier definition.

Values:

enumerator HAL_TIM_OC_COMPARE_UNIT_1

Timer output compare unit 1 Timer compare unit 1

enumerator HAL_TIM_OC_COMPARE_UNIT_2

Timer output compare unit 2 Timer compare unit 2

enumerator HAL_TIM_OC_COMPARE_UNIT_3

Timer output compare unit 3 Timer compare unit 3

enumerator HAL_TIM_OC_COMPARE_UNIT_4

Timer output compare unit 4 Timer compare unit 4

enumerator HAL_TIM_OC_COMPARE_UNIT_5

Timer output compare unit 5 Timer compare unit 5

enumerator HAL_TIM_OC_COMPARE_UNIT_6

Timer output compare unit 6 Timer compare unit 6

enumerator HAL_TIM_OC_COMPARE_UNIT_7

Timer output compare unit 7 Timer compare unit 7

enum hal_tim_oc_mode_t

HAL TIM Output Channel Mode.

Values:

enumerator HAL_TIM_OC_FROZEN

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

enumerator HAL_TIM_OC_ACTIVE_ON_MATCH

Set channel to active level on match 0x00000010 OCyREF is forced high on compare match

enumerator HAL_TIM_OC_INACTIVE_ON_MATCH

Set channel to inactive level on match 0x00000020 OCyREF is forced low on compare match

enumerator HAL_TIM_OC_TOGGLE

Toggle mode OCyREF toggles on compare match

enumerator HAL_TIM_OC_PWM1

PWM mode 1 In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active

enumerator HAL_TIM_OC_PWM2

PWM mode 2 In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

enumerator HAL_TIM_OC_FORCED_ACTIVE

Force active level OCyREF is forced high

enumerator HAL_TIM_OC_FORCED_INACTIVE

Force inactive level 0x00000040 OCyREF is forced low

enumerator HAL_TIM_OC_RETRIGERRABLE_OPM1

Retrigerrable OPM mode 1 0x00010000 Retrigerrable OPM mode 1

enumerator HAL_TIM_OC_RETRIGERRABLE_OPM2

Retrigerrable OPM mode 2 Retrigerrable OPM mode 2

enumerator HAL_TIM_OC_COMBINED_PWM1

Combined PWM mode 1 Combined PWM mode 1

enumerator HAL_TIM_OC_COMBINED_PWM2

Combined PWM mode 2 Combined PWM mode 2

enumerator HAL_TIM_OC_COMBINED_PWM3

Combined PWM mode 3 0x00020000 Combined PWM mode 3

enumerator HAL_TIM_OC_COMBINED_PWM4

Combined PWM mode 4 Combined PWM mode 4

enumerator HAL_TIM_OC_ASYMMETRIC_PWM1

Asymmetric PWM mode 1 Asymmetric PWM mode 1

enumerator HAL_TIM_OC_ASYMMETRIC_PWM2

Asymmetric PWM mode 2 Asymmetric PWM mode 2

enumerator HAL_TIM_OC_ASYMMETRIC_PWM3

Asymmetric PWM mode 3 Asymmetric PWM mode 3

enumerator HAL_TIM_OC_ASYMMETRIC_PWM4

Asymmetric PWM mode 4 Asymmetric PWM mode 4

enumerator HAL_TIM_OC_ASYMMETRIC_PWM5

Asymmetric PWM mode 5 Asymmetric PWM mode 5

enumerator HAL_TIM_OC_ASYMMETRIC_PWM6

Asymmetric PWM mode 6 Asymmetric PWM mode 6

enumerator HAL_TIM_OC_ASYMMETRIC_PWM7

Asymmetric PWM mode 7 Asymmetric PWM mode 7

enumerator HAL_TIM_OC_ASYMMETRIC_PWM8

Asymmetric PWM mode 8 Asymmetric PWM mode 8

enumerator HAL_TIM_OC_ASYMMETRIC_PWM9

Asymmetric PWM mode 9 Asymmetric PWM mode 9

enumerator HAL_TIM_OC_ASYMMETRIC_PWM10

Asymmetric PWM mode 10 Asymmetric PWM mode 10

enumerator HAL_TIM_OC_PULSE_ON_COMPARE

Pulse on compare (CH3 and CH4 only) Pulse on Compare mode

enumerator HAL_TIM_OC_DIRECTION_OUTPUT

Direction output (CH3 and CH4 only) Direction output mode

enum hal_tim_oc_polarity_t

HAL TIM Output Channel Polarity.

Values:

enumerator HAL_TIM_OC_HIGH

Output Channel (complementary output channel) active high OCx active high

enumerator HAL_TIM_OC_LOW

Output Channel (complementary output channel) active low 0x00000002 CC1P (Capture/compare 1 output polarity) OCx active low

enum hal_tim_oc_idle_state_t

HAL TIM Output Channel Idle State.

Values:

enumerator HAL_TIM_OC_IDLE_STATE_RESET

Output Idle state: OCx=0/OCxN=0 when MOE=0 OCx/OCxN=0 (after a dead-time if OC is implemented) when MOE=0

enumerator HAL_TIM_OC_IDLE_STATE_SET

Output Idle state: OCx=1/OCxN=1 when MOE=0 0x00000100 OIS1 (Output idle state 1 (tim_oc1 output)) OCx/OCxN=1 (after a dead-time if OC is implemented) when MOE=0

enum hal_tim_oc_override_state_t

HAL TIM Output Channel Override State.

Values:

enumerator HAL_TIM_OC_OVERRIDE_RESET

Output Override: OCx=0/OCxN=0 when OOC=1 OCx/OCxN=0 when OOC=1

enumerator HAL_TIM_OC_OVERRIDE_SET

Output Override: OCx=1/OCxN=1 when OOC=1 0x00000001 OOS1 (Output override state for output tim_oc1n) OCx/OCxN=1 when OOC=1

enum hal_tim_oc_break_mode_t

HAL TIM Output Channel Break Mode.

Values:

enumerator HAL_TIM_OC_BREAKMODE_IMMEDIATE

Output break mode: Immediate break Immediate break

enumerator HAL_TIM_OC_BREAKMODE_DELAY1

Output break mode: Delayed 1 break 0x00000001 Delayed 1 break

enumerator HAL_TIM_OC_BREAKMODE_DELAY2

Output break mode: Delayed 2 break 0x00000002 Delayed 2 break

enum hal_tim_oc_output_override_status_t

HAL TIM Output Channel Override Status.

Values:

enumerator HAL_TIM_OC_OVERRIDE_DISABLED

Output override is disabled

enumerator HAL_TIM_OC_OVERRIDE_ENABLED

Output override is enabled

enum hal_tim_oc_compare_preload_status_t

HAL TIM Output Compare Preload Status.

Values:

enumerator HAL_TIM_OC_COMPARE_PRELOAD_DISABLED

Output Compare preload is disabled

enumerator HAL_TIM_OC_COMPARE_PRELOAD_ENABLED

Output Compare preload is enabled

enum hal_tim_oc_compare_fast_mode_status_t

HAL TIM Output Channel Fast Mode Status.

Values:

enumerator HAL_TIM_OC_COMPARE_FAST_MODE_DISABLED

Output Compare fast mode is disabled

enumerator HAL_TIM_OC_COMPARE_FAST_MODE_ENABLED

Output Compare fast mode is enabled

enum hal_tim_pulse_prescaler_t

HAL TIM Pulse generator prescaler.

Values:

enumerator HAL_TIM_PULSE_DIV1

Pulse prescaler: tPWG = tTIM_KER_CK Pulse on compare pulse width prescaler 1

enumerator HAL_TIM_PULSE_DIV2

Pulse prescaler 2: tPWG = 2*tTIM_KER_CK 0x01000000 Pulse on compare pulse width prescaler 2

enumerator HAL_TIM_PULSE_DIV4

Pulse prescaler 4: tPWG = 4*tTIM_KER_CK 0x02000000 Pulse on compare pulse width prescaler 4

enumerator HAL_TIM_PULSE_DIV8

Pulse prescaler 8: tPWG = 8*tTIM_KER_CK Pulse on compare pulse width prescaler 8

enumerator HAL_TIM_PULSE_DIV16

Pulse prescaler 16: tPWG = 16*tTIM_KER_CK 0x04000000 Pulse on compare pulse width prescaler 16

enumerator HAL_TIM_PULSE_DIV32

Pulse prescaler 32: tPWG = 32*tTIM_KER_CK Pulse on compare pulse width prescaler 32

enumerator HAL_TIM_PULSE_DIV64

Pulse prescaler 64: tPWG = 64*tTIM_KER_CK Pulse on compare pulse width prescaler 64

enumerator HAL_TIM_PULSE_DIV128

Pulse prescaler 128: tPWG = 128*tTIM_KER_CK Pulse on compare pulse width prescaler 128

enum hal_tim_dithering_pattern_t

HAL TIM Dithering pattern.

Values:

enumerator HAL_TIM_DITHERING_0_16

0 duty cycle and / or period change over 16 consecutive periods

enumerator HAL_TIM_DITHERING_1_16

1 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_2_16

2 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_3_16

3 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_4_16

4 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_5_16

5 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_6_16

6 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_7_16

7 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_8_16

8 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_9_16

9 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_10_16

10 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_11_16

11 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_12_16

12 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_13_16

13 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_14_16

14 duty cycle and / or period changes over 16 consecutive periods

enumerator HAL_TIM_DITHERING_15_16

15 duty cycle and / or period changes over 16 consecutive periods

enum hal_tim_dithering_status_t

HAL TIM Dithering status.

Values:

enumerator HAL_TIM_DITHERING_DISABLED

Dithering is disabled

enumerator HAL_TIM_DITHERING_ENABLED

Dithering is enabled

enum hal_tim_ic_capture_unit_t

HAL TIM Input Capture Unit.

Values:

enumerator HAL_TIM_IC_CAPTURE_UNIT_1

Input capture unit 1 0x00000001 CC1E (Capture/compare 1 output enable) Timer input/output channel 1

enumerator HAL_TIM_IC_CAPTURE_UNIT_2

Input capture unit 2 0x00000010 CC2E (Capture/compare 2 output enable) Timer input/output channel 2

enumerator HAL_TIM_IC_CAPTURE_UNIT_3

Input capture unit 3 0x00000100 CC3E (Capture/compare 3 output enable) Timer input/output channel 3

enumerator HAL_TIM_IC_CAPTURE_UNIT_4

Input capture unit 4 0x00001000 CC4E (Capture/compare 4 output enable) Timer input/output channel 4

enum hal_tim_ic_polarity_t

HAL TIM Input Channel Polarity.

Values:

enumerator HAL_TIM_IC_RISING

Rising edges are detected on input channel The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

enumerator HAL_TIM_IC_FALLING

Falling edges are detected on input channel 0x00000002 CC1P (Capture/compare 1 output polarity) The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

enumerator HAL_TIM_IC_RISING_FALLING

Both rising and falling edges are detected on input channel The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

enum hal_tim_ic_capture_unit_src_t

HAL TIM Input Capture Source.

Values:

enumerator HAL_TIM_IC_DIRECT

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively ICx is mapped on TIx

enumerator HAL_TIM_IC_INDIRECT_RISING

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively with trigger on rising edge ICx is mapped on TIy The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

enumerator HAL_TIM_IC_INDIRECT_FALLING

TIM Input 1, 2, 3 or 4 edge is selected to be connected to IC2, IC1, IC4 or IC3, respectively with trigger on falling edge ICx is mapped on TIy 0x00000002 CC1P (Capture/compare 1 output polarity) The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

enumerator HAL_TIM_IC_INDIRECT_RISING_FALLING

TIM Input 1, 2, 3 or 4 rising edge is selected to be connected to IC2, IC1, IC4 or IC3, respectively with trigger on both edges ICx is mapped on TIy The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

enumerator HAL_TIM_IC_TRC

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC ICx is mapped on TRC

enum hal_tim_ic_capture_unit_prescaler_t

HAL TIM Input Capture Unit Prescaler.

Values:

enumerator HAL_TIM_IC_DIV1

Capture performed each time an edge is detected on the capture input No prescaler, capture is done each time an edge is detected on the capture input

enumerator HAL_TIM_IC_DIV2

Capture performed once every 2 events Capture is done once every 2 events

enumerator HAL_TIM_IC_DIV4

Capture performed once every 4 events Capture is done once every 4 events

enumerator HAL_TIM_IC_DIV8

Capture performed once every 8 events Capture is done once every 8 events

enum hal_tim_ic_xor_gate_position_t

HAL TIM Input Channel XOR Gate Position.

Values:

enumerator HAL_TIM_IC_XOR_GATE_POS_DIRECT

XOR gate placed before TI1 filter XOR gate placed before TI1 filter

enumerator HAL_TIM_IC_XOR_GATE_POS_FILTERED

XOR gate placed after TI1, TI2 and TI3 filters, edge detector placed on XOR output 0x08000000 XORPS (XOR gate position selection) XOR gate placed after TI1, TI2 and TI3 filters, edge detector placed on XOR output

enum hal_tim_ic_xor_gate_input_inversion_status_t

HAL TIM Input Channel XOR Gate Input Signal Inversion status.

Values:

enumerator HAL_TIM_IC_XOR_GATE_INPUT_INV_DISABLED

ICx is non-inverted on XOR gate input

enumerator HAL_TIM_IC_XOR_GATE_INPUT_INV_ENABLED

ICx is inverted on XOR gate input

enum hal_tim_ic_xor_gate_status_t

HAL TIM Input Channel XOR Gate status.

Values:

enumerator HAL_TIM_IC_XOR_GATE_DISABLED

XOR gate is disabled

enumerator HAL_TIM_IC_XOR_GATE_ENABLED

XOR gate is enabled

enum hal_tim_ic_channel_level_t

HAL TIM Input Channel Signal level.

Values:

enumerator HAL_TIM_IC_CHANNEL_LEVEL_LOW

Input channel signal level is low ICx signal is low

enumerator HAL_TIM_IC_CHANNEL_LEVEL_HIGH

Input channel signal level is high 0x10000000 TI1FS (tim_in1f status) ICx signal is high

enum hal_tim_one_pulse_mode_status_t

TIM One-Pulse Mode status.

Values:

enumerator HAL_TIM_ONE_PULSE_MODE_DISABLED

One-Pulse Mode is disabled

enumerator HAL_TIM_ONE_PULSE_MODE_ENABLED

One-Pulse Mode is enabled

enum hal_tim_encoder_index_dir_t

TIM Encoder Index Direction (index_dir).

Values:

enumerator HAL_TIM_ENCODER_INDEX_UP_DOWN

Index resets the counter whatever the direction Index resets the counter whatever the direction

enumerator HAL_TIM_ENCODER_INDEX_UP

Index resets the counter when up-counting only 0x00000002 Index resets the counter when up-counting only

enumerator HAL_TIM_ENCODER_INDEX_DOWN

Index resets the counter when down-counting only 0x00000004 Index resets the counter when down-counting only

enum hal_tim_encoder_index_blank_mode_t

TIM Encoder Index Blanking selection.

Values:

enumerator HAL_TIM_ENCODER_INDEX_BLANK_ALWAYS

Index always active Index always active

enumerator HAL_TIM_ENCODER_INDEX_BLANK_TI3

Index disabled when TI3 input is active, as per CC3P bitfield 0x00000008 Index disabled when TI3 input is active, as per CC3P bitfield

enumerator HAL_TIM_ENCODER_INDEX_BLANK_TI4

Index disabled when TI4 input is active, as per CC4P bitfield 0x00000010 Index disabled when TI4 input is active, as per CC4P bitfield

enum hal_tim_encoder_index_pos_sel_t

TIM Encoder Index Positioning selection.

Values:

enumerator HAL_TIM_ENCODER_INDEX_POS_DOWN_DOWN

In quadrature encoder mode, the index event resets the counter when AB = 00 Index resets the counter when AB = 00

enumerator HAL_TIM_ENCODER_INDEX_POS_DOWN_UP

In quadrature encoder mode, the index event resets the counter when AB = 01 0x00000040 Index resets the counter when AB = 01

enumerator HAL_TIM_ENCODER_INDEX_POS_UP_DOWN

In quadrature encoder mode, the index event resets the counter when AB = 10 0x00000080 Index resets the counter when AB = 10

enumerator HAL_TIM_ENCODER_INDEX_POS_UP_UP

In quadrature encoder mode, the index event resets the counter when AB = 11 Index resets the counter when AB = 11

enumerator HAL_TIM_ENCODER_INDEX_POS_DOWN

In directional clock mode or clock plus direction mode, the index event resets the counter when clock is 0 Index resets the counter when clock is 0

enumerator HAL_TIM_ENCODER_INDEX_POS_UP

In directional clock mode or clock plus direction mode, the index event resets the counter when clock is 1 0x00000040 Index resets the counter when clock is 1

enum hal_tim_encoder_index_sel_t

TIM Encoder Index selection.

Values:

enumerator HAL_TIM_ENCODER_INDEX_ALL

Index is always active

enumerator HAL_TIM_ENCODER_INDEX_FIRST_ONLY

The first Index only resets the counter 0x00000020 FIDX (First index) The first Index only resets the counter

enum hal_tim_encoder_index_status_t

TIM Encoder Index status.

Values:

enumerator HAL_TIM_ENCODER_INDEX_DISABLED

Index input is disabled

enumerator HAL_TIM_ENCODER_INDEX_ENABLED

Index input is enabled

enum hal_tim_ext_trig_polarity_t

HAL TIM External Trigger Polarity.

Values:

enumerator HAL_TIM_EXT_TRIG_NONINVERTED

ETR input is active at high level or rising edge ETR is non-inverted, active at high level or rising edge

enumerator HAL_TIM_EXT_TRIG_INVERTED

ETR input is active at low level or falling edge 0x00008000 ETP (External trigger polarity) ETR is inverted, active at low level or falling edge

enum hal_tim_ext_trig_prescaler_t

HAL TIM External Trigger Prescaler.

Values:

enumerator HAL_TIM_EXT_TRIG_DIV1

No prescaler is used ETR prescaler OFF

enumerator HAL_TIM_EXT_TRIG_DIV2

Prescaler for External Trigger: Capture performed once every 2 events 0x00001000 ETR frequency is divided by 2

enumerator HAL_TIM_EXT_TRIG_DIV4

Prescaler for External Trigger: Capture performed once every 4 events 0x00002000 ETR frequency is divided by 4

enumerator HAL_TIM_EXT_TRIG_DIV8

Prescaler for External Trigger: Capture performed once every 8 events 0x00003000 ETPS[1:0] bits (External trigger prescaler) ETR frequency is divided by 8

enum hal_tim_ext_trig_sync_prescaler_t

HAL TIM External Trigger Synchronous Prescaler.

Values:

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV1

No prescaler is used ETR synchronous prescaler OFF

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV2

Prescaler for External Trigger: Capture performed once every 2 events 0x04000000 ETR frequency is divided by 2

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV3

Prescaler for External Trigger: Capture performed once every 3 events 0x08000000 ETR frequency is divided by 3

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV4

Prescaler for External Trigger: Capture performed once every 4 events ETR frequency is divided by 4

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV5

Prescaler for External Trigger: Capture performed once every 5 events 0x10000000 ETR frequency is divided by 5

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV6

Prescaler for External Trigger: Capture performed once every 6 events ETR frequency is divided by 6

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV7

Prescaler for External Trigger: Capture performed once every 7 events ETR frequency is divided by 7

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV8

Prescaler for External Trigger: Capture performed once every 8 events ETR frequency is divided by 8

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV9

Prescaler for External Trigger: Capture performed once every 9 events 0x20000000 ETR frequency is divided by 9

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV10

Prescaler for External Trigger: Capture performed once every 10 events ETR frequency is divided by 10

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV11

Prescaler for External Trigger: Capture performed once every 11 events ETR frequency is divided by 11

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV12

Prescaler for External Trigger: Capture performed once every 12 events ETR frequency is divided by 12

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV13

Prescaler for External Trigger: Capture performed once every 13 events ETR frequency is divided by 13

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV14

Prescaler for External Trigger: Capture performed once every 14 events ETR frequency is divided by 14

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV15

Prescaler for External Trigger: Capture performed once every 15 events ETR frequency is divided by 15

enumerator HAL_TIM_EXT_TRIG_SYNC_DIV16

Prescaler for External Trigger: Capture performed once every 16 events 0x3C000000 SETPS[3:0] bits (Synchronous External Trigger Prescaler) ETR frequency is divided by 16

enum hal_tim_ext_trig_src_t

HAL TIM External Trigger Source.

Note

The pattern of the enum constants is: HAL_TIM_EXT_TRIG_TIMx_<source>

Values:

enumerator HAL_TIM_EXT_TRIG_TIM1_GPIO

TIM1 external trigger is connected to TIM1_ETR tim1_etr_in is connected to TIM1_ETR

enumerator HAL_TIM_EXT_TRIG_TIM1_COMP1_OUT

TIM1 external trigger is connected to comp1_out 0x00004000 tim1_etr_in is connected to comp1_out

enumerator HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD1

TIM1 external trigger is connected to adc1_awd1 tim1_etr_in is connected to adc1_awd1

enumerator HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD2

TIM1 external trigger is connected to adc1_awd2 0x00010000 tim1_etr_in is connected to adc1_awd2

enumerator HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD3

TIM1 external trigger is connected to adc1_awd3 tim1_etr_in is connected to adc1_awd3

enumerator HAL_TIM_EXT_TRIG_TIM2_GPIO

TIM2 external trigger is connected to TIM2_ETR tim2_etr_in is connected to TIM2_ETR

enumerator HAL_TIM_EXT_TRIG_TIM2_COMP1_OUT

TIM2 external trigger is connected to comp1_out 0x00004000 tim2_etr_in is connected to comp1_out

enumerator HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD1

TIM2 external trigger is connected to adc1_awd1 tim2_etr_in is connected to adc1_awd1

enumerator HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD2

TIM2 external trigger is connected to adc1_awd2 0x00010000 tim2_etr_in is connected to adc1_awd2

enumerator HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD3

TIM2 external trigger is connected to adc1_awd3 tim2_etr_in is connected to adc1_awd3

enumerator HAL_TIM_EXT_TRIG_TIM2_LSE

TIM2 external trigger is connected to LSE tim2_etr_in is connected to LSE

enumerator HAL_TIM_EXT_TRIG_TIM2_MCO1

TIM2 external trigger is connected to MCO1 tim2_etr_in is connected to MCO1

enumerator HAL_TIM_EXT_TRIG_TIM2_TIM5_ETR

TIM2 external trigger is connected to TIM5_ETR tim2_etr_in is connected to TIM5_ETR

enumerator HAL_TIM_EXT_TRIG_TIM5_GPIO

TIM5 external trigger is connected to TIM5_ETR tim5_etr_in is connected to TIM5_ETR

enumerator HAL_TIM_EXT_TRIG_TIM5_COMP1_OUT

TIM5 external trigger is connected to comp1_out 0x00004000 tim5_etr_in is connected to comp1_out

enumerator HAL_TIM_EXT_TRIG_TIM5_TIM2_ETR

TIM5 external trigger is connected to TIM2_ETR 0x00020000 tim5_etr_in is connected to TIM2_ETR

enumerator HAL_TIM_EXT_TRIG_TIM8_GPIO

TIM8 external trigger is connected to TIM8_ETR tim8_etr_in is connected to TIM8_ETR

enumerator HAL_TIM_EXT_TRIG_TIM8_COMP1_OUT

TIM8 external trigger is connected to comp1_out 0x00004000 tim8_etr_in is connected to comp1_out

enumerator HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD1

TIM8 external trigger is connected to adc2_awd1 tim8_etr_in is connected to adc2_awd1

enumerator HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD2

TIM8 external trigger is connected to adc2_awd2 0x00010000 tim8_etr_in is connected to adc2_awd2

enumerator HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD3

TIM8 external trigger is connected to adc2_awd3 tim8_etr_in is connected to adc2_awd3

enum hal_tim_channel_src_t

HAL TIM Input sources.

Note

The pattern of the enum constants is: HAL_TIM_INPUT_TIMx_TIy_<source>

Values:

enumerator HAL_TIM_INPUT_TIM1_TI1_GPIO

TIM1 TI1 is connected to TIM1_CH1 tim1_ti1 is connected to TIM1_CH1

enumerator HAL_TIM_INPUT_TIM1_TI1_COMP1_OUT

TIM1 TI1 is connected to comp1_out 0x00000001 tim1_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM1_TI2_GPIO

TIM1 TI2 is connected to TIM1_CH2 tim1_ti2 is connected to TIM1_CH2

enumerator HAL_TIM_INPUT_TIM1_TI3_GPIO

TIM1 TI3 is connected to TIM1_CH3 tim1_ti3 is connected to TIM1_CH3

enumerator HAL_TIM_INPUT_TIM1_TI4_GPIO

TIM1 TI4 is connected to TIM1_CH4 tim1_ti4 is connected to TIM1_CH4

enumerator HAL_TIM_INPUT_TIM2_TI1_GPIO

TIM2 TI1 is connected to TIM2_CH1 tim2_ti1 is connected to TIM2_CH1

enumerator HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT

TIM2 TI1 is connected to comp1_out 0x00000001 tim2_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM2_TI1_LSI

TIM2 TI1 is connected to LSI tim2_ti1 is connected to LSI

enumerator HAL_TIM_INPUT_TIM2_TI1_LSE

TIM2 TI1 is connected to LSE 0x00000004 tim2_ti1 is connected to LSE

enumerator HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG

TIM2 TI1 is connected to rtc_wut_trg tim2_ti1 is connected to rtc_wut_trg

enumerator HAL_TIM_INPUT_TIM2_TI1_TIM5_CH1

TIM2 TI1 is connected to TIM5_CH1 tim2_ti1 is connected to TIM5_CH1

enumerator HAL_TIM_INPUT_TIM2_TI1_FDCAN1_RXEOF_EVT

TIM2 TI1 is connected to fdcan1_rxeof_evt tim2_ti1 is connected to fdcan1_rxeof_evt

enumerator HAL_TIM_INPUT_TIM2_TI2_GPIO

TIM2 TI2 is connected to TIM2_CH2 tim2_ti2 is connected to TIM2_CH2

enumerator HAL_TIM_INPUT_TIM2_TI2_HSE_RTC

TIM2 TI2 is connected to hse_1M_ck tim2_ti2 is connected to hse_1M_ck

enumerator HAL_TIM_INPUT_TIM2_TI2_MCO1

TIM2 TI2 is connected to MCO1 0x00000400 tim2_ti2 is connected to MCO1

enumerator HAL_TIM_INPUT_TIM2_TI2_MCO2

TIM2 TI2 is connected to MCO2 tim2_ti2 is connected to MCO2

enumerator HAL_TIM_INPUT_TIM2_TI2_FDCAN1_TXEOF_EVT

TIM2 TI2 is connected to fdcan1_txeof_evt tim2_ti2 is connected to fdcan1_txeof_evt

enumerator HAL_TIM_INPUT_TIM2_TI3_GPIO

TIM2 TI3 is connected to TIM2_CH3 tim2_ti3 is connected to TIM2_CH3

enumerator HAL_TIM_INPUT_TIM2_TI4_GPIO

TIM2 TI4 is connected to TIM2_CH4 tim2_ti4 is connected to TIM2_CH4

enumerator HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT

TIM2 TI4 is connected to comp1_out 0x01000000 tim2_ti4 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM5_TI1_GPIO

TIM5 TI1 is connected to TIM5_CH1 tim5_ti1 is connected to TIM5_CH1

enumerator HAL_TIM_INPUT_TIM5_TI1_COMP1_OUT

TIM5 TI1 is connected to comp1_out 0x00000001 tim5_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM5_TI2_GPIO

TIM5 TI2 is connected to TIM5_CH2 tim5_ti2 is connected to TIM5_CH2

enumerator HAL_TIM_INPUT_TIM5_TI3_GPIO

TIM5 TI3 is connected to TIM5_CH3 tim5_ti3 is connected to TIM5_CH3

enumerator HAL_TIM_INPUT_TIM5_TI4_GPIO

TIM5 TI4 is connected to TIM5_CH4 tim5_ti4 is connected to TIM5_CH4

enumerator HAL_TIM_INPUT_TIM8_TI1_GPIO

TIM8 TI1 is connected to TIM8_CH1 tim8_ti1 is connected to TIM8_CH1

enumerator HAL_TIM_INPUT_TIM8_TI1_COMP1_OUT

TIM8 TI1 is connected to comp1_out 0x00000001 tim8_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM8_TI2_GPIO

TIM8 TI2 is connected to TIM8_CH2 tim8_ti2 is connected to TIM8_CH2

enumerator HAL_TIM_INPUT_TIM8_TI3_GPIO

TIM8 TI3 is connected to TIM8_CH3 tim8_ti3 is connected to TIM8_CH3

enumerator HAL_TIM_INPUT_TIM8_TI4_GPIO

TIM8 TI4 is connected to TIM8_CH4 tim8_ti4 is connected to TIM8_CH4

enumerator HAL_TIM_INPUT_TIM12_TI1_GPIO

TIM12 TI1 is connected to TIM12_CH1 tim12_ti1 is connected to TIM12_CH1

enumerator HAL_TIM_INPUT_TIM12_TI1_COMP1_OUT

TIM12 TI1 is connected to comp1_out 0x00000001 tim12_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM12_TI1_MCO1

TIM12 TI1 is connected to MCO1 tim12_ti1 is connected to MCO1

enumerator HAL_TIM_INPUT_TIM12_TI1_MCO2

TIM12 TI1 is connected to MCO2 0x00000004 tim12_ti1 is connected to MCO2

enumerator HAL_TIM_INPUT_TIM12_TI1_HSE_RTC

TIM12 TI1 is connected to hse_1M_ck tim12_ti1 is connected to hse_1M_ck

enumerator HAL_TIM_INPUT_TIM12_TI1_I3C1_IBI_ACK

TIM12 TI1 is connected to i3c1_ibi_ack tim12_ti1 is connected to i3c1_ibi_ack

enumerator HAL_TIM_INPUT_TIM12_TI2_GPIO

TIM12 TI2 is connected to TIM12_CH2 tim12_ti2 is connected to TIM12_CH2

enumerator HAL_TIM_INPUT_TIM15_TI1_GPIO

TIM15 TI1 is connected to TIM15_CH1 tim15_ti1 is connected to TIM15_CH1

enumerator HAL_TIM_INPUT_TIM15_TI1_COMP1_OUT

TIM15 TI1 is connected to comp1_out 0x00000001 tim15_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM15_TI1_LSE

TIM15 TI1 is connected to LSE tim15_ti1 is connected to LSE

enumerator HAL_TIM_INPUT_TIM15_TI2_GPIO

TIM15 TI2 is connected to TIM15_CH2 tim15_ti2 is connected to TIM15_CH2

enumerator HAL_TIM_INPUT_TIM16_TI1_GPIO

TIM16 TI1 is connected to TIM16_CH1 tim16_ti1 is connected to TIM16_CH1

enumerator HAL_TIM_INPUT_TIM16_TI1_COMP1_OUT

TIM16 TI1 is connected to comp1_out 0x00000001 tim16_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM16_TI1_LSI

TIM16 TI1 is connected to LSI tim16_ti1 is connected to LSI

enumerator HAL_TIM_INPUT_TIM16_TI1_LSE

TIM16 TI1 is connected to LSE 0x00000004 tim16_ti1 is connected to LSE

enumerator HAL_TIM_INPUT_TIM16_TI1_RTC_WUT_TRG

TIM16 TI1 is connected to rtc_wut_trg tim16_ti1 is connected to rtc_wut_trg

enumerator HAL_TIM_INPUT_TIM16_TI1_MCO1

TIM16 TI1 is connected to MCO1 tim16_ti1 is connected to MCO1

enumerator HAL_TIM_INPUT_TIM16_TI1_MCO2

TIM16 TI1 is connected to MCO2 tim16_ti1 is connected to MCO2

enumerator HAL_TIM_INPUT_TIM17_TI1_GPIO

TIM17 TI1 is connected to TIM17_CH1 tim17_ti1 is connected to TIM17_CH1

enumerator HAL_TIM_INPUT_TIM17_TI1_COMP1_OUT

TIM17 TI1 is connected to comp1_out 0x00000001 tim17_ti1 is connected to comp1_out

enumerator HAL_TIM_INPUT_TIM17_TI1_HSE_RTC

TIM17 TI1 is connected to hse_1M_ck 0x00000004 tim17_ti1 is connected to hse_rtc_ck

enumerator HAL_TIM_INPUT_TIM17_TI1_MCO1

TIM17 TI1 is connected to MCO1 tim17_ti1 is connected to MCO1

enumerator HAL_TIM_INPUT_TIM17_TI1_MCO2

TIM17 TI1 is connected to MCO2 tim17_ti1 is connected to MCO2

enumerator HAL_TIM_INPUT_TIM17_TI1_I3C1_IBI_ACK

TIM17 TI1 is connected to i3c1_ibi_ack tim17_ti1 is connected to i3c1_ibi_ack

enum hal_tim_slave_mode_t

HAL TIM Slave mode.

Values:

enumerator HAL_TIM_SLAVE_DISABLED

Slave mode disabled Slave mode disabled

enumerator HAL_TIM_SLAVE_RESET

Reset Mode Rising edge of the selected trigger input (TRGI) reinitializes the counter 0x00000004 Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

enumerator HAL_TIM_SLAVE_GATED

Gated Mode The counter clock is enabled when the trigger input (TRGI) is high Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

enumerator HAL_TIM_SLAVE_TRIGGER

Trigger Mode The counter starts at a rising edge of the trigger TRGI Trigger Mode - The counter starts at a rising edge of the trigger TRGI

enumerator HAL_TIM_SLAVE_COMBINED_RESET_TRIGGER

Combined reset + trigger mode Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter 0x00010000 Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

enumerator HAL_TIM_SLAVE_COMBINED_GATED_RESET

Combined gated + reset mode The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset as soon as the trigger becomes low. Both start and stop of the counter are controlled. Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of the counter are controlled.

enum hal_tim_trigger_output_source_t

HAL TIM Master Mode Selection of Trigger Output source.

Values:

enumerator HAL_TIM_TRGO_RESET

TIMx_EGR.UG bit is used as trigger output (TRGO) UG bit from the TIMx_EGR register is used as trigger output

enumerator HAL_TIM_TRGO_ENABLE

TIMx_CR1.CEN bit is used as trigger output (TRGO) 0x00000010 Counter Enable signal (CNT_EN) is used as trigger output

enumerator HAL_TIM_TRGO_UPDATE

Update event is used as trigger output (TRGO) 0x00000020 Update event is used as trigger output

enumerator HAL_TIM_TRGO_CC1IF

Capture or a compare match 1 is used as trigger output (TRGO) CC1 capture or a compare match is used as trigger output

enumerator HAL_TIM_TRGO_OC1

OC1REFC signal is used as trigger output (TRGO) 0x00000040 OC1REFC signal is used as trigger output

enumerator HAL_TIM_TRGO_OC2

OC2REFC signal is used as trigger output (TRGO) OC2REFC signal is used as trigger output

enumerator HAL_TIM_TRGO_OC3

OC3REFC signal is used as trigger output (TRGO) OC3REFC signal is used as trigger output

enumerator HAL_TIM_TRGO_OC4

OC4REFC signal is used as trigger output (TRGO) OC4REFC signal is used as trigger output

enumerator HAL_TIM_TRGO_ENCODER_CLK

Encoder clock is used as trigger output (TRGO) 0x02000000 Encoder clock signal is used as trigger output

enum hal_tim_trigger_output2_source_t

HAL TIM Master Mode Selection of Trigger Output 2 source.

Values:

enumerator HAL_TIM_TRGO2_RESET

TIMx_EGR.UG bit is used as trigger output (TRGO2) UG bit from the TIMx_EGR register is used as trigger output 2

enumerator HAL_TIM_TRGO2_ENABLE

TIMx_CR1.CEN bit is used as trigger output (TRGO2) 0x00100000 Counter Enable signal (CNT_EN) is used as trigger output 2

enumerator HAL_TIM_TRGO2_UPDATE

Update event is used as trigger output (TRGO2) 0x00200000 Update event is used as trigger output 2

enumerator HAL_TIM_TRGO2_CC1F

Capture or a compare match 1 is used as trigger output (TRGO2) CC1 capture or a compare match is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC1

OC1REFC signal is used as trigger output (TRGO2) 0x00400000 OC1REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC2

OC2REFC signal is used as trigger output (TRGO2) OC2REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC3

OC3REFC signal is used as trigger output (TRGO2) OC3REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC4

OC4REFC signal is used as trigger output (TRGO2) OC4REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC5

OC5REFC signal is used as trigger output (TRGO2) 0x00800000 OC5REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC6

OC6REFC signal is used as trigger output (TRGO2) OC6REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC7

OC7REFC signal is used as trigger output (TRGO2) 0x01000000 OC7REFC signal is used as trigger output 2

enumerator HAL_TIM_TRGO2_OC4_RISING_FALLING

OC4REFC rising or falling edges generate pulses on TRGO2 OC4REFC rising or falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC6_RISING_FALLING

OC6REFC rising or falling edges generate pulses on TRGO2 OC6REFC rising or falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC7_RISING_FALLING

OC7REFC rising or falling edges generate pulses on TRGO2 OC7REFC rising or falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC4_RISING_OC6_RISING

OC4REFC or OC6REFC rising edges generate pulses on TRGO2 OC4REFC or OC6REFC rising edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC4_RISING_OC7_RISING

OC4REFC or OC7REFC rising edges generate pulses on TRGO2 OC4REFC or OC7REFC rising edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC5_RISING_OC6_RISING

OC5REFC or OC6REFC rising edges generate pulses on TRGO2 OC5REFC or OC6REFC rising edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC5_RISING_OC7_RISING

OC5REFC or OC7REFC rising edges generate pulses on TRGO2 OC5REFC or OC7REFC rising edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC6_RISING_OC7_RISING

OC6REFC or OC7REFC rising edges generate pulses on TRGO2 OC6REFC or OC7REFC rising edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC4_RISING_OC6_FALLING

OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 OC4REFC rising or OC6REFC falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC4_RISING_OC7_FALLING

OC4REFC rising or OC7REFC falling edges generate pulses on TRGO2 OC4REFC rising or OC7REFC falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC5_RISING_OC6_FALLING

OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 OC5REFC rising or OC6REFC falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC5_RISING_OC7_FALLING

OC5REFC rising or OC7REFC falling edges generate pulses on TRGO2 OC5REFC rising or OC7REFC falling edges are used as trigger output 2

enumerator HAL_TIM_TRGO2_OC6_RISING_OC7_FALLING

OC6REFC rising or OC7REFC falling edges generate pulses on TRGO2 OC6REFC rising or OC7REFC falling edges are used as trigger output 2

enum hal_tim_slave_mode_preload_status_t

HAL TIM Slave Mode Preload Status.

Values:

enumerator HAL_TIM_SLAVE_MODE_PRELOAD_DISABLED

Slave mode selection (SMS[3:0]) isn’t preloaded

enumerator HAL_TIM_SLAVE_MODE_PRELOAD_ENABLED

Slave mode selection (SMS[3:0]) is preloaded

enum hal_tim_slave_mode_preload_src_t

Slave Mode Preload Source.

Values:

enumerator HAL_TIM_SLAVE_MODE_PRELOAD_UPDATE

The transfer is triggered by the timer’s Update event The SMS preload transfer is triggered by the Timer’s Update event

enumerator HAL_TIM_SLAVE_MODE_PRELOAD_INDEX

The transfer is triggered by the Index event 0x02000000 SMSPS (SMS preload source) The SMS preload transfer is triggered by the Index event

enum hal_tim_master_slave_mode_status_t

TIM Master/Slave Mode.

Values:

enumerator HAL_TIM_MASTER_SLAVE_MODE_DISABLED

No action

enumerator HAL_TIM_MASTER_SLAVE_MODE_ENABLED

Master/Slave mode is selected

enum hal_tim_adc_synchronization_status_t

HAL TIM ADC Synchronization Status.

Values:

enumerator HAL_TIM_ADC_SYNCHRONIZATION_DISABLED

The timer operates independently from the ADC

enumerator HAL_TIM_ADC_SYNCHRONIZATION_ENABLED

The timer operation is synchronized with the ADC clock to provide jitter-free sampling point

enum hal_tim_ocref_clr_status_t

HAL TIM Output Compare Clear (ocrefclr) Status.

Values:

enumerator HAL_TIM_OCREFCLEAR_DISABLED

enumerator HAL_TIM_OCREFCLEAR_ENABLED

enum hal_tim_ocref_clr_src_t

HAL TIM Output Compare Clear (ocrefclr) Sources.

Note

The pattern of the enum constants is: HAL_TIM_OCREF_CLR_TIMx_<source>

Values:

enumerator HAL_TIM_OCREF_CLR_TIM1_ETR

TIM1 OCREF clear input is connected to tim1_etrf 0x00000008 OCCS (OCREF clear selection) tim1_ocref_clr is connected to tim_etrf

enumerator HAL_TIM_OCREF_CLR_TIM1_COMP1_OUT

TIM1 OCREF clear input is connected to comp1_out tim1_ocref_clr is connected to comp1_out

enumerator HAL_TIM_OCREF_CLR_TIM2_ETR

TIM2 OCREF clear input is connected to tim2_etrf 0x00000008 OCCS (OCREF clear selection) tim2_ocref_clr is connected to tim_etrf

enumerator HAL_TIM_OCREF_CLR_TIM2_COMP1_OUT

TIM2 OCREF clear input is connected to comp1_out tim2_ocref_clr is connected to comp1_out

enumerator HAL_TIM_OCREF_CLR_TIM5_ETR

TIM5 OCREF clear input is connected to tim5_etrf 0x00000008 OCCS (OCREF clear selection) tim5_ocref_clr is connected to tim_etrf

enumerator HAL_TIM_OCREF_CLR_TIM5_COMP1_OUT

TIM5 OCREF clear input is connected to comp1_out tim5_ocref_clr is connected to comp1_out

enumerator HAL_TIM_OCREF_CLR_TIM8_ETR

TIM8 OCREF clear input is connected to tim8_etrf 0x00000008 OCCS (OCREF clear selection) tim8_ocref_clr is connected to tim_etrf

enumerator HAL_TIM_OCREF_CLR_TIM8_COMP1_OUT

TIM8 OCREF clear input is connected to comp1_out tim8_ocref_clr is connected to comp1_out

enumerator HAL_TIM_OCREF_CLR_TIM15_COMP1_OUT

TIM15 OCREF clear input is connected to comp1_out tim15_ocref_clr is connected to comp1_out

enumerator HAL_TIM_OCREF_CLR_TIM16_COMP1_OUT

TIM16 OCREF clear input is connected to comp1_out tim16_ocref_clr is connected to comp1_out

enumerator HAL_TIM_OCREF_CLR_TIM17_COMP1_OUT

TIM17 OCREF clear input is connected to comp1_out tim17_ocref_clr is connected to comp1_out

enum hal_tim_dma_index_t

TIM DMA Handle Index.

Values:

enumerator HAL_TIM_DMA_ID_UPD

Index of the DMA handle used for Update DMA requests

enumerator HAL_TIM_DMA_ID_CC1

Index of the DMA handle used for Capture/Compare 1 DMA requests

enumerator HAL_TIM_DMA_ID_CC2

Index of the DMA handle used for Capture/Compare 2 DMA requests

enumerator HAL_TIM_DMA_ID_CC3

Index of the DMA handle used for Capture/Compare 3 DMA requests

enumerator HAL_TIM_DMA_ID_CC4

Index of the DMA handle used for Capture/Compare 4 DMA requests

enumerator HAL_TIM_DMA_ID_COM

Index of the DMA handle used for Commutation DMA requests

enumerator HAL_TIM_DMA_ID_TRGI

Index of the DMA handle used for Trigger DMA requests

enum hal_tim_dmaburst_base_addr_reg_t

HAL TIM DMA Burst Base Address.

Values:

enumerator HAL_TIM_DMABURST_BASE_ADDR_CR1

TIMx_CR1 register is the DMA base address for DMA burst TIMx_CR1 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CR2

TIMx_CR2 register is the DMA base address for DMA burst 0x00000001 TIMx_CR2 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_SMCR

TIMx_SMCR register is the DMA base address for DMA burst 0x00000002 TIMx_SMCR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_DIER

TIMx_DIER register is the DMA base address for DMA burst TIMx_DIER register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_SR

TIMx_SR register is the DMA base address for DMA burst 0x00000004 TIMx_SR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_EGR

TIMx_EGR register is the DMA base address for DMA burst TIMx_EGR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCMR1

TIMx_CCMR1 register is the DMA base address for DMA burst TIMx_CCMR1 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCMR2

TIMx_CCMR2 register is the DMA base address for DMA burst TIMx_CCMR2 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCER

TIMx_CCER register is the DMA base address for DMA burst 0x00000008 TIMx_CCER register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CNT

TIMx_CNT register is the DMA base address for DMA burst TIMx_CNT register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_PSC

TIMx_PSC register is the DMA base address for DMA burst TIMx_PSC register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_ARR

TIMx_ARR register is the DMA base address for DMA burst TIMx_ARR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_RCR

TIMx_RCR register is the DMA base address for DMA burst TIMx_RCR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR1

TIMx_CCR1 register is the DMA base address for DMA burst TIMx_CCR1 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR2

TIMx_CCR2 register is the DMA base address for DMA burst TIMx_CCR2 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR3

TIMx_CCR3 register is the DMA base address for DMA burst TIMx_CCR3 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR4

TIMx_CCR4 register is the DMA base address for DMA burst 0x00000010 TIMx_CCR4 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_BDTR

TIMx_BDTR register is the DMA base address for DMA burst TIMx_BDTR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR5

TIMx_CCR5 register is the DMA base address for DMA burst TIMx_CCR5 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR6

TIMx_CCR6 register is the DMA base address for DMA burst TIMx_CCR6 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCMR3

TIMx_CCMR3 register is the DMA base address for DMA burst TIMx_CCMR3 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_DTR2

TIMx_DTR2 register is the DMA base address for DMA burst TIMx_DTR2 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_ECR

TIMx_ECR register is the DMA base address for DMA burst TIMx_ECR register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_TISEL

TIMx_TISEL register is the DMA base address for DMA burst TIMx_TISEL register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_AF1

TIMx_AF1 register is the DMA base address for DMA burst TIMx_AF1 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_AF2

TIMx_AF2 register is the DMA base address for DMA burst TIMx_AF2 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCR7

TIMx_CCR7 register is the DMA base address for DMA burst TIMx_CCR7 register is the DMA base address for DMA burst

enumerator HAL_TIM_DMABURST_BASE_ADDR_CCMR4

TIMx_CCMR4 register is the DMA base address for DMA burst TIMx_CCMR4 register is the DMA base address for DMA burst

enum hal_tim_dmaburst_source_t

HAL TIM DMA Burst triggering sources.

Values:

enumerator HAL_TIM_DMABURST_UPD

DMA burst is triggered by the update event 0x00010000 Transfer source is update event

enumerator HAL_TIM_DMABURST_CC1

DMA burst is triggered by the capture/compare match 1 event 0x00020000 Transfer source is CC1 event

enumerator HAL_TIM_DMABURST_CC2

DMA burst is triggered by the capture/compare match 2 event Transfer source is CC2 event

enumerator HAL_TIM_DMABURST_CC3

DMA burst is triggered by the capture/compare match 3 event 0x00040000 Transfer source is CC3 event

enumerator HAL_TIM_DMABURST_CC4

DMA burst is triggered by the capture/compare match 4 event Transfer source is CC4 event

enumerator HAL_TIM_DMABURST_COM

DMA burst is triggered by the commutation event Transfer source is COM event

enumerator HAL_TIM_DMABURST_TRGI

DMA burst is triggered by the trigger event Transfer source is trigger event

enum tim_dmaburst_source_t

TIM DMA Burst triggering sources.

Note

DMA Burst sources mapped on hal_tim_dmaburst_source_t for internal usage.

Values:

enumerator TIM_DMABURST_NONE

DMA burst is not used

enumerator TIM_DMABURST_UPD

DMA burst is triggered by the update event

enumerator TIM_DMABURST_CC1

DMA burst is triggered by the capture/compare match 1 event

enumerator TIM_DMABURST_CC2

DMA burst is triggered by the capture/compare match 2 event event

enumerator TIM_DMABURST_CC3

DMA burst is triggered by the capture/compare match 3 event event

enumerator TIM_DMABURST_CC4

DMA burst is triggered by the capture/compare match 4 event event

enumerator TIM_DMABURST_COM

DMA burst is triggered by the commutation event

enumerator TIM_DMABURST_TRGI

DMA burst is triggered by the trigger event

enum hal_tim_dmaburst_length_t

HAL TIM DMA Burst Length.

Values:

enumerator HAL_TIM_DMABURST_1TRANSFER

The transfer is done to 1 register starting from the DMA burst base address Transfer is done to 1 register starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_2TRANSFERS

The transfer is done to 2 registers starting from the DMA burst base address 0x00000100 Transfer is done to 2 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_3TRANSFERS

The transfer is done to 3 registers starting from the DMA burst base address 0x00000200 Transfer is done to 3 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_4TRANSFERS

The transfer is done to 4 registers starting from the DMA burst base address Transfer is done to 4 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_5TRANSFERS

The transfer is done to 5 registers starting from the DMA burst base address 0x00000400 Transfer is done to 5 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_6TRANSFERS

The transfer is done to 6 registers starting from the DMA burst base address Transfer is done to 6 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_7TRANSFERS

The transfer is done to 7 registers starting from the DMA burst base address Transfer is done to 7 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_8TRANSFERS

The transfer is done to 8 registers starting from the DMA burst base address Transfer is done to 1 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_9TRANSFERS

The transfer is done to 9 registers starting from the DMA burst base address 0x00000800 Transfer is done to 9 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_10TRANSFERS

The transfer is done to 10 registers starting from the DMA burst base address Transfer is done to 10 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_11TRANSFERS

The transfer is done to 11 registers starting from the DMA burst base address Transfer is done to 11 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_12TRANSFERS

The transfer is done to 12 registers starting from the DMA burst base address Transfer is done to 12 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_13TRANSFERS

The transfer is done to 13 registers starting from the DMA burst base address Transfer is done to 13 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_14TRANSFERS

The transfer is done to 14 registers starting from the DMA burst base address Transfer is done to 14 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_15TRANSFERS

The transfer is done to 15 registers starting from the DMA burst base address Transfer is done to 15 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_16TRANSFERS

The transfer is done to 16 registers starting from the DMA burst base address Transfer is done to 16 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_17TRANSFERS

The transfer is done to 17 registers starting from the DMA burst base address 0x00001000 Transfer is done to 17 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_18TRANSFERS

The transfer is done to 18 registers starting from the DMA burst base address Transfer is done to 18 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_19TRANSFERS

The transfer is done to 19 registers starting from the DMA burst base address Transfer is done to 19 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_20TRANSFERS

The transfer is done to 20 registers starting from the DMA burst base address Transfer is done to 20 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_21TRANSFERS

The transfer is done to 21 registers starting from the DMA burst base address Transfer is done to 21 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_22TRANSFERS

The transfer is done to 22 registers starting from the DMA burst base address Transfer is done to 22 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_23TRANSFERS

The transfer is done to 23 registers starting from the DMA burst base address Transfer is done to 23 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_24TRANSFERS

The transfer is done to 24 registers starting from the DMA burst base address Transfer is done to 24 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_25TRANSFERS

The transfer is done to 25 registers starting from the DMA burst base address Transfer is done to 25 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_26TRANSFERS

The transfer is done to 26 registers starting from the DMA burst base address Transfer is done to 26 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_27TRANSFERS

The transfer is done to 27 registers starting from the DMA burst base address Transfer is done to 27 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_28TRANSFERS

The transfer is done to 28 registers starting from the DMA burst base address Transfer is done to 28 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_29TRANSFERS

The transfer is done to 29 registers starting from the DMA burst base address Transfer is done to 29 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_30TRANSFERS

The transfer is done to 30 registers starting from the DMA burst base address Transfer is done to 30 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_31TRANSFERS

The transfer is done to 31 registers starting from the DMA burst base address Transfer is done to 31 registers starting from the DMA burst base address

enumerator HAL_TIM_DMABURST_32TRANSFERS

The transfer is done to 32 registers starting from the DMA burst base address 0x00001F00 DBL[4:0] bits (DMA burst length) Transfer is done to 32 registers starting from the DMA burst base address

enum hal_tim_dmaburst_direction_t

HAL TIM DMA Burst Direction.

Values:

enumerator HAL_TIM_DMABURST_READ

DMA Burst read operation to transfer Data from the TIM peripheral to the memory

enumerator HAL_TIM_DMABURST_WRITE

DMA Burst write operation to transfer Data from the memory to the TIM peripheral

enum hal_tim_break_input_id_t

HAL TIM Break Input.

Values:

enumerator HAL_TIM_BREAK_INPUT_1

Timer break input 1 TIMx_BKIN input

enumerator HAL_TIM_BREAK_INPUT_2

Timer break input 2 TIMx_BKIN2 input

enum hal_tim_break_input_polarity_t

HAL TIM Break Input Polarity.

Values:

enumerator HAL_TIM_BREAK_INPUT_LOW

Break input is active low Break input BRK is active low

enumerator HAL_TIM_BREAK_INPUT_HIGH

Break input is active high 0x00002000 BKP (Break polarity) Break input BRK is active high

enum hal_tim_break_input_mode_t

HAL TIM Break Input Function Mode.

Values:

enumerator HAL_TIM_BREAK_INPUT_MODE_INPUT

Break input in input mode Break input BRK in input mode

enumerator HAL_TIM_BREAK_INPUT_MODE_BIDIRECTIONAL

Break input in bidirectional mode. In bidirectional mode the Break input is configured both in input mode and in open drain output mode. Any active Break event will assert a low logic level on the Break input to indicate an internal break event to external devices.

enum hal_tim_break_input_status_t

HAL TIM Break Input status.

Values:

enumerator HAL_TIM_BREAK_INPUT_DISABLED

Break input is disabled

enumerator HAL_TIM_BREAK_INPUT_ENABLED

Break input is enabled

enum hal_tim_break_input_src_polarity_t

HAL TIM Break Input Source Polarity.

Values:

enumerator HAL_TIM_BREAK_INPUT_SRC_NONINVERTED

Break input source polarity is not inverted BRK BKIN input is active high

enumerator HAL_TIM_BREAK_INPUT_SRC_INVERTED

Break input source polarity is inverted 0x00000200 BKINP (TIMx_BKIN input polarity) BRK BKIN input is active low

enum hal_tim_break_input_src_status_t

HAL TIM Break Input Source Status.

Values:

enumerator HAL_TIM_BREAK_INPUT_SRC_DISABLED

Break input source is disabled

enumerator HAL_TIM_BREAK_INPUT_SRC_ENABLED

Break input source is enabled

enum hal_tim_break_main_output_status_t

HAL TIM Main Output status.

Values:

enumerator HAL_TIM_BREAK_MAIN_OUTPUT_DISABLED

Main output is disabled

enumerator HAL_TIM_BREAK_MAIN_OUTPUT_ENABLED

Main output is enabled

enum hal_tim_break_automatic_output_status_t

HAL TIM Automatic Output status.

Values:

enumerator HAL_TIM_BREAK_AUTOMATIC_OUTPUT_DISABLED

Main output can only be enabled by software

enumerator HAL_TIM_BREAK_AUTOMATIC_OUTPUT_ENABLED

Main output can be enabled by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

enum hal_tim_break_delay_t

HAL TIM Break Delay.

Values:

enumerator HAL_TIM_BREAK_DELAY1

Delayed 1 break Delayed 1 break

enumerator HAL_TIM_BREAK_DELAY2

Delayed 2 break Delayed 2 break

enum hal_tim_off_state_run_t

Off-state selection for run (ossr) mode.

Values:

enumerator HAL_TIM_OFF_STATE_RUN_DISABLE

When inactive, OCx/OCxN outputs are disabled (forced to Hi-Z state) When inactive, OCx/OCxN outputs are disabled

enumerator HAL_TIM_OFF_STATE_RUN_ENABLE

When inactive, OCx/OCxN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 0x00000800 OSSR (Off-state selection for Run mode) When inactive, OCx/OCxN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

enum hal_tim_off_state_idle_t

Off-state selection for idle (ossi) mode.

Values:

enumerator HAL_TIM_OFF_STATE_IDLE_DISABLE

When inactive, OCx/OCxN outputs are disabled (forced to Hi-Z state) When inactive, OCx/OCxN outputs are disabled

enumerator HAL_TIM_OFF_STATE_IDLE_ENABLE

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime 0x00000400 OSSI (Off-state selection for idle mode) When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

enum hal_tim_output_disable_status_t

HAL TIM output disable status.

Values:

enumerator HAL_TIM_OUTPUT_IDLE_STATE

Break was triggered (or MOE was written to 0), tim_ocx and tim_ocxn are forced to their Output idle state (OIS) Break was triggered (or MOE was written to 0) and OIS states are forced on tim_ocx and tim_ocxn outputs

enumerator HAL_TIM_OUTPUT_DISABLED_STATE

Break2 was triggered, tim_ocx and tim_ocxn outputs are forced to their inactive level 0x02000000 ODS (Output disable status) Break2 was triggered, tim_ocx and tim_ocxn outputs are inactive

enum hal_tim_deadtime_preload_status_t

HAL TIM deadtime preload status.

Values:

enumerator HAL_TIM_DEADTIME_PRELOAD_DISABLED

Deadtime preload is disabled

enumerator HAL_TIM_DEADTIME_PRELOAD_ENABLED

Deadtime preload is enabled

enum hal_tim_asymmetrical_deadtime_status_t

HAL TIM asymmetrical deadtime status.

Values:

enumerator HAL_TIM_ASYMMETRICAL_DEADTIME_DISABLED

Asymmetrical deadtime is disabled

enumerator HAL_TIM_ASYMMETRICAL_DEADTIME_ENABLED

Asymmetrical deadtime is enabled

enum hal_tim_lock_level_t

HAL TIM write protection levels definition.

Values:

enumerator HAL_TIM_LOCK_OFF

LOCK OFF - No bit is write protected LOCK OFF - No bit is write protected

enumerator HAL_TIM_LOCK_1

LOCK Level 1 0x00000100 LOCK Level 1

enumerator HAL_TIM_LOCK_2

LOCK Level 2 0x00000200 LOCK Level 2

enumerator HAL_TIM_LOCK_3

LOCK Level 3 0x00000300 LOCK[1:0] bits (Lock configuration) LOCK Level 3

enum hal_tim_commutation_src_t

HAL TIM Commutation trigger selection.

Values:

enumerator HAL_TIM_COMMUTATION_SOFTWARE

Capture/compare control bits are updated by setting the COMG bit only Capture/compare control bits are updated by setting the COMG bit only

enumerator HAL_TIM_COMMUTATION_SOFTWARE_AND_TRIGGER

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input 0x00000004 CCUS (Capture/compare control update selection) Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

enum hal_tim_commutation_status_t

HAL TIM Commutation status.

Values:

enumerator HAL_TIM_COMMUTATION_DISABLED

Commutation is disabled

enumerator HAL_TIM_COMMUTATION_ENABLED

Commutation is enabled

enum hal_tim_cc_dmareq_src_t

HAL TIM Capture/Compare DMA Request Source.

Values:

enumerator HAL_TIM_CC_DMAREQ_CC

CCx DMA request sent when CCx event occurs CCx DMA request sent when CCx event occurs

enumerator HAL_TIM_CC_DMAREQ_UPD

CCx DMA requests sent when update event occurs 0x00000008 CCDS (Capture/compare DMA selection) CCx DMA requests sent when update event occurs

enum hal_tim_sw_event_id_t

HAL TIM Software Event definition.

Values:

enumerator HAL_TIM_SW_EVENT_UPD

Reinitialize the counter and generates an update of the registers 0x00000001 UG (Update generation) Update generation

enumerator HAL_TIM_SW_EVENT_CC1

A capture/compare event is generated on channel 1 0x00000002 CC1G (Capture/compare 1 generation) Capture/Compare 1 generation

enumerator HAL_TIM_SW_EVENT_CC2

A capture/compare event is generated on channel 2 0x00000004 CC2G (Capture/compare 2 generation) Capture/Compare 2 generation

enumerator HAL_TIM_SW_EVENT_CC3

A capture/compare event is generated on channel 3 0x00000008 CC3G (Capture/compare 3 generation) Capture/Compare 3 generation

enumerator HAL_TIM_SW_EVENT_CC4

A capture/compare event is generated on channel 4 0x00000010 CC4G (Capture/compare 4 generation) Capture/Compare 4 generation

enumerator HAL_TIM_SW_EVENT_COM

A commutation event is generated 0x00000020 COMG (Capture/compare control update generation) Commutation generation

enumerator HAL_TIM_SW_EVENT_TRGI

A trigger event is generated 0x00000040 TG (Trigger generation) Trigger generation

enumerator HAL_TIM_SW_EVENT_BRK

A break event is generated 0x00000080 BG (Break generation) Break generation

enumerator HAL_TIM_SW_EVENT_BRK2

A break 2 event is generated 0x00000100 B2G (Break 2 generation) Break 2 generation

struct hal_tim_clock_sel_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Clock selection.

Public Members

hal_tim_clk_src_t clock_source

TIM clock source.

Specifies the source of the clock feeding the timer’s prescaler.

hal_tim_trig_sel_t trigger

Input Trigger source.

Specifies the trigger input to be used to synchronize the counter when HAL_TIM_CLK_EXTERNAL_MODE1 is selected as clock source.

struct hal_tim_config_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Time Base Configuration Structure definition.

Note

: The update event period is calculated as follows: update_event = TIM_CLK/((prescaler + 1)*(period + 1)*(repetition + 1))

Public Members

uint32_t prescaler

Specifies the prescaler value used to divide the timer kernel clock.

This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

hal_tim_counter_mode_t counter_mode

Specifies the counter mode

uint32_t period

Specifies the period value to be loaded into the active Auto-Reload Register.

For a counter with a 16-bit resolution, this parameter can be a number between Min_Data = 0x0001 and Max_Data = 0xFFFF (or 0xFFFEF if dithering is activated). In non-dithering mode, only bits 15:0 hold the period value. In dithering mode, the integer part of the period is in bits 19:4 and bits 3:0 hold the dithering part.

For a counter with a 32-bit resolution, this parameter can be a number between Min_Data = 0x00000001 and Max_Data = 0xFFFFFFFF (or 0xFFFFFFEF if dithering is activated). The register holds the period value in non-dithering mode. In dithering mode, the integer part is in ARR[31:4] and ARR[3:0] bitfield contains the dithered part.

uint32_t repetition_counter

Specifies the repetition counter value for instances that support it.

If the repetition counter is used, the update event (UEV) is generated after upcounting repeats the number of times programmed in the repetition counter register (RCR).

Otherwise, the update event is generated at each counter overflow. The value is encoded on 8 or 16 bits depending on the instance.

hal_tim_clock_sel_t clock_sel

TIM clock selection.

Specifies the source of the clock feeding the timer’s prescaler. Also specifies the trigger input to be used to synchronize the counter in case the clock source is external mode 1.

struct hal_tim_oc_compare_unit_config_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Output Channel Configuration Structure definition.

Public Members

hal_tim_oc_mode_t mode

Specifies the output channel mode

uint32_t pulse

Specifies the pulse value to be loaded into the Capture/Compare Register.

For a 16 bits counter,this parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFFEF if dithering is activated in which case bits[3:0] represent the dithered part and bits[19:4] the integer part). For a 32 bits counter,this parameter can be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF (or 0xFFFFFFEF if dithering is activated in which case bits[3:0] represent the dithered part and bits[31:4] the integer part).

struct hal_tim_oc_channel_config_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Output Channel Configuration Structure definition.

Public Members

hal_tim_oc_polarity_t polarity

Specifies the output channel (CHx or CHxN) polarity

hal_tim_oc_idle_state_t idle_state

Specifies the output channel (CHx or CHxN) state during Idle state.

This parameter is only valid for timer instances supporting break feature.

hal_tim_oc_override_state_t override_state

Specifies the output channel (CHx or CHxN) state when it is disabled.

This parameter is only valid for timer instances supporting the break feature and is not applicable to internal channels.

hal_tim_oc_break_mode_t break_mode

Specifies the output channel (CHx or CHxN) break mode.

This parameter is only valid for timer instances supporting the break feature and is not applicable to internal channels.

struct hal_tim_ic_channel_config_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Input Channel Configuration Structure definition.

Public Members

hal_tim_channel_src_t source

Specifies the input source

hal_tim_ic_polarity_t polarity

Specifies the active edge of the input signal

hal_tim_filter_t filter

Specifies the input channel filter

struct hal_tim_ic_capture_unit_config_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Input Channel Capture Configuration Structure definition.

Public Members

hal_tim_ic_capture_unit_src_t source

Specifies the signal to capture

hal_tim_ic_capture_unit_prescaler_t prescaler

Specifies the input capture prescaler

struct hal_tim_encoder_index_config_t

#include <stm32c5xx_hal_tim.h>

TIM Index configuration Structure definition.

Note

Index input (ETR input polarity, prescaler and filter) is configured separately

Public Members

hal_tim_encoder_index_dir_t dir

Specifies in which counter direction the index event resets the counter

hal_tim_encoder_index_pos_sel_t pos

Specifies in which AB input configuration the index event resets the counter

hal_tim_encoder_index_blank_mode_t blanking

Specifies whether or not the index event is conditioned by TI3 or TI4 input

hal_tim_encoder_index_sel_t idx

Specifies whether index is always active or only once

struct hal_tim_ext_trig_config_t

#include <stm32c5xx_hal_tim.h>

TIM ETR configuration Structure definition.

Public Members

hal_tim_ext_trig_src_t source

Specifies the external trigger input source

hal_tim_ext_trig_polarity_t polarity

Specifies the external trigger input polarity

hal_tim_filter_t filter

Specifies the external trigger input filter

hal_tim_ext_trig_prescaler_t prescaler

Specifies the external trigger input prescaler

hal_tim_ext_trig_sync_prescaler_t sync_prescaler

Specifies the external trigger input synchronous prescaler

struct hal_tim_slave_config_t

#include <stm32c5xx_hal_tim.h>

TIM Slave mode controller configuration Structure definition.

Public Members

hal_tim_slave_mode_t mode

Specifies the slave mode

hal_tim_trig_sel_t trigger

Specifies the slave mode controller trigger input

struct hal_tim_trigger_output2_config_t

#include <stm32c5xx_hal_tim.h>

TIM Trigger Output 2 configuration Structure definition.

Public Members

hal_tim_trigger_output2_source_t trgo2_src

Specifies the trigger-output2 source

uint32_t postscaler

Specifies the trigger-output2 postscaler.

The number of events on tim_trgo2 is divided by (TGO2PSC[4:0] + 1).

struct hal_tim_dmaburst_config_t

#include <stm32c5xx_hal_tim.h>

TIM DMA Burst operation specification Structure definition.

Public Members

hal_tim_dmaburst_base_addr_reg_t address

Specifies the DMA burst base address

hal_tim_dmaburst_source_t source

Specifies the DMA burst source

hal_tim_dmaburst_length_t length

Specifies the DMA burst length

struct hal_tim_break_input_config_t

#include <stm32c5xx_hal_tim.h>

TIM Break input(s) configuration Structure definition.

Note

2 break inputs can be configured (BKIN and BKIN2) with configurable filter, polarity and mode (input or bidirectional).

Public Members

hal_tim_break_input_polarity_t polarity

Specifies the break input polarity

hal_tim_filter_t filter

Specifies the break input filter

hal_tim_break_input_mode_t mode

Specifies whether the break input is bidirectional or not. (only for instances that support it)

struct hal_tim_off_states_config_t

#include <stm32c5xx_hal_tim.h>

Off-state configuration for RUN and IDLE modes.

Public Members

hal_tim_off_state_run_t off_state_run

Specifies the state of the output channel when the main output is enabled

hal_tim_off_state_idle_t off_state_idle

Specifies the state of the output channel when the main output is disabled

struct hal_tim_pulse_generator_config_t

#include <stm32c5xx_hal_tim.h>

HAL TIM Pulse Generator Configuration Structure definition.

Public Members

hal_tim_pulse_prescaler_t prescaler

Specifies the pulse width prescaler

uint32_t pulse_width

Specifies the pulse width. This parameter can be a number between 0x00 and 0xFF

struct hal_tim_handle_s

#include <stm32c5xx_hal_tim.h>

HAL TIM Time Base Handle Structure definition.

Public Members

hal_tim_t instance

HAL TIM instance

volatile hal_tim_state_t global_state

TIM global state

hal_dma_handle_t * hdma [ ( 7U ) ]

DMA Handlers array. ( hal_tim_dma_index_t)

volatile tim_dmaburst_source_t dmaburst_source

DMA Burst source

volatile hal_tim_channel_state_t channel_states [ ( 11U ) ]

TIM channels state array

const void * p_user_data

User Data Pointer

volatile uint32_t last_error_codes

Store last error code

hal_tim_cb_t error_callback

TIM Error callback

hal_tim_cb_t stop_callback

TIM Update DMA stop callback

hal_tim_channel_cb_t channel_stop_callback

TIM capture/Compare DMA stop callback

hal_tim_cb_t update_callback

TIM Update callback

hal_tim_cb_t update_half_cplt_callback

TIM Update Half Complete callback

hal_tim_cb_t trigger_callback

TIM Trigger callback

hal_tim_cb_t trigger_half_cplt_callback

TIM Trigger Half Complete callback

hal_tim_channel_cb_t input_capture_callback

TIM Input Capture callback

hal_tim_channel_cb_t input_capture_half_cplt_callback

TIM Input Capture Half Complete callback

hal_tim_channel_cb_t compare_match_callback

TIM Compare Match callback

hal_tim_channel_cb_t compare_match_half_cplt_callback

TIM Compare Match Half Complete callback

hal_tim_cb_t commutation_callback

TIM Commutation callback

hal_tim_cb_t commutation_half_cplt_callback

TIM Commutation Half Complete callback

hal_tim_cb_t break_callback

TIM Break callback

hal_tim_cb_t break2_callback

TIM Break2 callback

hal_tim_cb_t system_break_callback

TIM System Break callback

hal_tim_break_cb_t software_break_callback

TIM Software Break callback

hal_tim_cb_t encoder_index_callback

TIM Encoder Index callback

hal_tim_cb_t direction_change_callback

TIM Direction Change callback

hal_tim_cb_t index_error_callback

TIM Index Error callback

hal_tim_cb_t transition_error_callback

TIM Transition Error callback