LL DBGMCU Constants

DBGMCU Device ID definition

group DBGMCU_DEV_ID

Defines

LL_DBGMCU_DEV_ID_C53X_C542 0x044FU

STM32C5 series device STM32C53x/542

LL_DBGMCU_DEV_ID_C55X_C562 0x044EU

STM32C5 series device STM32C55x/562

LL_DBGMCU_DEV_ID_C59X_C5A3 0x045AU

STM32C5 series device STM32C59x/5A3

DBGMCU Device revision ID definition

group DBGMCU_REV_ID

Defines

LL_DBGMCU_REV_ID_A 0x1000U

STM32C5 device revision A

LL_DBGMCU_REV_ID_Z 0x1001U

STM32C5 device revision Z

LL_DBGMCU_REV_ID_Y 0x1003U

STM32C5 device revision Y

DBGMCU Debug during low power mode

group DBGMCU_DEBUG_LOW_POWER_MODE

Defines

LL_DBGMCU_SLEEP_MODE_DEBUG DBGMCU_CR_DBG_SLEEP

Debug during Sleep mode

LL_DBGMCU_STOP_MODE_DEBUG DBGMCU_CR_DBG_STOP

Debug during Stop mode

LL_DBGMCU_STANDBY_MODE_DEBUG DBGMCU_CR_DBG_STANDBY

Debug during Standby mode

LL_DBGMCU_LP_MODE_DEBUG_ALL

(DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | \

DBGMCU_CR_DBG_STANDBY)


Debug during Low power mode (Sleep, Stop and Standby modes)

DBGMCU APB1_GRP1 STOP IP

group DBGMCU_LL_EC_APB1_GRP1_STOP_IP

Defines

LL_DBGMCU_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP

The counter clock of TIM2 is stopped when the core is in debug mode

LL_DBGMCU_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP

The counter clock of TIM5 is stopped when the core is in debug mode

LL_DBGMCU_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP

The counter clock of TIM6 is stopped when the core is in debug mode

LL_DBGMCU_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP

The counter clock of TIM7 is stopped when the core is in debug mode

LL_DBGMCU_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP

The counter clock of TIM12 is stopped when the core is in debug mode

LL_DBGMCU_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP

The window watchdog counter clock is stopped when the core is in debug mode

LL_DBGMCU_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP

The independent watchdog counter clock is stopped when the core is in debug mode

LL_DBGMCU_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP

The I2C1 SMBus timeout is frozen while the core is in debug mode

LL_DBGMCU_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP

The I2C2 SMBus timeout is frozen while the core is in debug mode

LL_DBGMCU_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP

The I3C1 timeout is frozen while the core is in debug mode

DBGMCU APB2_GRP1 STOP IP

group DBGMCU_LL_EC_APB2_GRP1_STOP_IP

Defines

LL_DBGMCU_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP

The counter clock of TIM1 is stopped when the core is in debug mode

LL_DBGMCU_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP

The counter clock of TIM8 is stopped when the core is in debug mode

LL_DBGMCU_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP

The counter clock of TIM15 is stopped when the core is in debug mode

LL_DBGMCU_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP

The counter clock of TIM16 is stopped when the core is in debug mode

LL_DBGMCU_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP

The counter clock of TIM17 is stopped when the core is in debug mode

DBGMCU APB3_GRP1 STOP IP

group DBGMCU_LL_EC_APB3_GRP1_STOP_IP

Defines

LL_DBGMCU_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP

The counter clock of LPTIM1 is stopped when the core is in debug mode

LL_DBGMCU_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP

The counter clock of RTC is stopped when the core is in debug mode

DBGMCU AHB1_GRP1 STOP IP

group DBGMCU_LL_EC_AHB1_GRP1_STOP_IP

Defines

LL_DBGMCU_LPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP

The counter clock of LPDMA1 channel 0 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP

The counter clock of LPDMA1 channel 1 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP

The counter clock of LPDMA1 channel 2 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP

The counter clock of LPDMA1 channel 3 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP

The counter clock of LPDMA1 channel 4 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP

The counter clock of LPDMA1 channel 5 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP

The counter clock of LPDMA1 channel 6 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP

The counter clock of LPDMA1 channel 7 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA2_CH0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP

The counter clock of LPDMA2 channel 0 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA2_CH1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP

The counter clock of LPDMA2 channel 1 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA2_CH2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP

The counter clock of LPDMA2 channel 2 is stopped when the core is in debug mode

LL_DBGMCU_LPDMA2_CH3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP

The counter clock of LPDMA2 channel 3 is stopped when the core is in debug mode