STM32CubeMX
Appendix C STM32 microcontrollers power consumption parameters ¶
• T AMAX : highest maximum ambient temperature value found during the sequence.
Figure 387. Description of the Results area
5.3.4 Power sequence step parameters glossary
The parameters that characterize power sequence steps are the following (refer to Appendix C: STM32 microcontrollers power consumption parameters for more details):
• Power modes
To save energy, it is recommended to switch the microcontroller operating mode from running mode, where a maximum power is required, to a low-power mode requiring limited resources.
• V CORE range (STM32L1) or Power scale (STM32F4)
These parameters are set by software to control the power supply range for digital peripherals.
• Memory Fetch Type
This field proposes the possible memory locations for application C code execution. It can be either RAM, FLASH or FLASH with ART ON or OFF (only for families that feature a proprietary Adaptive real-time (ART) memory accelerator which increases the program execution speed when executing from flash memory).
The performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory. In terms of power consumption, it is equivalent to program execution from RAM. In addition, STM32CubeMX uses the same selection choice to cover both settings, RAM and flash memory with ART ON.
• Clock Configuration
This operation sets the AHB bus frequency or the CPU frequency that will be used for computing the microcontroller power consumption. When there is only one possible choice, the frequencies are automatically configured.
The clock configuration drop-down list allows to configure the application clocks:
– the internal or external oscillator sources: MSI, HSI, LSI, HSE or LSE
– the oscillator frequency
– other determining parameters, among them PLL ON, LSE Bypass, AHB prescaler value, LCD with duty
• Peripherals
The peripheral list shows the peripherals available for the selected power mode. The power consumption is given assuming that peripherals are only clocked (e.g. not in use by a running program). Each peripheral can be enabled or disabled, their individual power consumption is displayed in a tooltip. An overall consumption due to peripheral analog and digital parts is provided in the step Results area (see Figure 388).
Figure 388. Overall peripheral consumption
The user can select the peripherals relevant for the application:
– none ( Disable All)
– some (using peripheral dedicated checkbox)
Only the selected and enabled peripherals are taken into account when computing the power consumption.
• Step duration
The user can change the default step duration value. When building a sequence, the user can either create steps according to the application actual power sequence or define them as a percentage spent in each mode. For example, if an application spends 30% in Run mode, 20% in Sleep and 50% in Stop, the user must configure a 3-step sequence consisting in 30 ms in Run, 20 ms in Sleep and 50 ms in Stop.
• Additional consumption
This field allows entering an additional consumption resulting from specific user configuration (e.g. MCU providing power supply to other connected devices).
5.3.5 Battery glossary
• Capacity (mAh)
Amount of energy that can be delivered in a single battery discharge.
• Self-discharge (% / month)
This percentage, over a specified period, represents the loss of battery capacity when the battery is not used (open-circuit conditions), as a result of internal leakage.
• Nominal voltage (V)
Voltage supplied by a fully charged battery.
• Max. continuous current (mA)
This current corresponds to the maximum current that can be delivered during the battery lifetime period without damaging the battery.
• Max. pulse current (mA)
This is the maximum pulse current that can be delivered exceptionally, for instance when the application is switched on during the starting phase.
5.3.6 SMPS feature
Some microcontrollers (e.g. STM32L496xxxxP) allow the user to connect an external switched mode power supply (SMPS) to further reduce power consumption.
For such microcontrollers, the Power Consumption Calculator tool offers the following features:
• Selection of SMPS for the current project
From the left panel, check the Use SMPS box to use SMPS (see Figure 389). By default, ST SMPS model is used.
• Selection of another SMPS model by clicking the Change button
This opens the SMPS database management window in which the user can add a new SMPS model (see Figure 390). The user can then select a different SMPS model for the current sequence (see Figure 391, Figure 392 and Figure 393)
• Check for invalid SMPS transitions in the current sequence by enabling the SMPS checker
To do this, select the checkbox to enable the checker and click the Help button to open the reference state diagram (see Figure 394).
• Configuration of SMPS mode for each step (see Figure 395)
If the SMPS checker is enabled, only the SMPS modes valid for the current step are proposed.
Figure 389. Selecting SMPS for the current project
Figure 390. SMPS database - Adding new SMPS models
Figure 392. Current project configuration updated with new SMPS model
Figure 394. SMPS transition checker and state diagram helper window
Figure 395. Configuring the SMPS mode for each step
5.3.7 Bluetooth Low-Energy ® /ZigBee ® support (STM32WB series only)
The Power Consumption tool allows the user to take into account the consumption related to the RF peripheral and corresponding Bluetooth Low-Energy functional mode, combined with the usage of the SMPS feature.
The Bluetooth Low-Energy mode can be selected from the left panel and configured to reflect the application relevant settings. For each new step enabling BLE, the peripheral consumption part is updated accordingly (see Figure 397). A similar approach is used for ZigBee (see Figure 398).
Figure 397. RF Bluetooth Low-Energy mode configuration (STM32WB series only)
Figure 398. ZigBee configuration (STM32WB series only)
5.3.8 Sub-GHz support (STM32WL series only)
Sub-GHz usage can be enabled from the left panel and configured to reflect the application relevant settings. For each new step enabling ZigBee, the peripheral consumption part is updated accordingly (see Figure 399).
5.3.9 Example feature (STM32MPUs and STM32H7 dual-core only)
Under the section Sequence Examples, the PCC tool allows to access examples: each of them comes with an explanatory slide set and a ready-made sequence to load in PCC (see Figure 400).
Figure 400. Power Consumption Calculator - Example set
Clicking “Load Example N” loads the sequence corresponding to example N (see Figure 401).
Figure 401. Power Consumption Calculator - Example sequence loading
Clicking “Example N Presentation” displays the explanations for that example.
The example can be changed anytime: the new sequence can be added to the current sequence, or replace it (see Figure 402).
Figure 402. Power Consumption Calculator - Example sequence new selection
Note: The examples are provided for a given part number and may require adjustments when used for a different part number. Also, after loading, it is recommended to edit each step and check settings.
5.4 DDR Suite (STM32MPUs only)
DDR SDRAMs are complex high speed devices that need careful PCB design.
The STM32MP15 devices support the following DDR types:
• LPDDR2
• LPDDR3
• DDR3 / DDR3L
They are specified by the JEDEC standard (standardization of interfaces, commands, timings, packages and ballout).
STM32CubeMX has been extended to provide an exhaustive tool suite for the DDR subsystem. It proposes the following key features.
• Configuration of DDR controller and PHY registers is managed automatically based on reduced set of editable parameters.
• DDR testing is offered based on a rich list. Tests go from basic to stress. User can also develop its own tests.
DDR configuration is accessible like the other peripherals in the Pinout & Configuration view: clicking the DDR from the component panel opens the mode and configuration panels.
DDR Test suite testing and tuning features are available from the Tools view.
The DDR suite relies on two important concepts:
• the DDR timings as key inputs for the configuration of the DDR Controller and PHY
• the tuning of DDR signals to compensate board design imperfections.
5.4.1 DDR configuration
STM32CubeMX allows to set DDR system parameters and JEDEC core timings. The timing parameters are available in the DDR datasheet.
DDR type, width, and density
The DDR type, width, and density parameters must be set to proceed with the DDR configuration. This can be done in the Mode panel after selecting the DDR in the Pinout & Configuration view. See Figure 403 for an example of LPDDR2 settings.
Figure 403. DDR pinout and configuration settings
Another example: for a configuration with two “DDR3 16 bits 2 Gb” chips, settings are “DDR3/DDR3L”, “32 bits” and 4 Gb”.
Note: Contexts for DDR IP cannot be changed, DDR is tied to “Cortex-A7 nonsecure” identified as “Cortex-A7 NS” in the tool. DDR configuration
Clicking on a parameter will show additional details in the DDR configuration footer. - The DDR frequency is taken from the ‘Clock configuration’ tab, it cannot be changed in the DDR configuration.
• The ‘Relaxed Timing’ mode is used during bring-up phase for trying relaxed key DDR timings value (one t CK added to t RC , t RCD and t RP timings)
• Other parameters must be retrieved from the user DDR datasheet. • Some parameters are read-only: they are for information only and depend on the DDR type.
Clicking “generate code” automatically computes the DDR node of the device tree (DDR Controller and DDR PHY registers values) based on these parameters.
DDR3 configuration
For DDR3, the configuration is made easier with the selection of a Speed Bin Grade combination, instead of manually editing timing parameters.
Figure 404. DDR3 configuration
The Speed Bin Grade combination must match the selected DDR. If the exact combination
is not in the pick-list, select “1066E / 6-6-6” for faster DDR Speed Bin Grade, or “1066G / 8-8-8” for a relaxed configuration.
Timing edition is optional, and reserved for advanced users: select Show Advanced parameters to display the list.
5.4.2 Connection to the target and DDR register loading
To manage DDR tests and tuning, STM32CubeMX must establish a connection with the target and more specifically with U-Boot SPL using the DDR interactive protocol:
• the DDR interactive protocol is only available in the Basic boot scheme U-Boot SPL binary and supported over the UART4 peripheral instance
• when U-Boot SPL detects a connection to STM32CubeMX on UART4, it stops its initialization process and accepts commands from STM32CubeMX.
There are two connection options:
1. the U-Boot SPL binary is available in flash memory
2. the U-Boot SPL needs to be loaded in SYSRAM because the DDR has not yet been tested nor tuned (and, consequently, is not fully functional yet).
Prerequisites
• Installation of ST-Link USB driver to perform firmware upgrades: for Windows, latest version of STSW-LINK009, for Linux, use STSW-LINK007. Both can be downloaded from www.st.com.
• Installation of STM32CubeProgrammer (for SYSRAM loading only): installer can be downloaded from www.st.com.
Connection to the target
The COM port must be selected to connect to the target, as indicated in Figure 405.
Figure 405. DDR Suite - Connection to target
If U-Boot SPL loading in SysRAM is required, it can be performed through UART or USB using the STM32CubeProgrammer tool. If not automatically detected by STM32CubeMX, the STM32CubeProgrammer tool location must be specified in the Connection settings window: click to open it. U-Boot SPL file must be manually selected in the build image folder.
Once up, the connection gives the various services and target information (see Figure 406).
Figure 406. DDR Suite - Target connected
Output/Log messages
STM32CubeMX outputs DDR suite related activity logs (see Figure 407) and interactive protocol communication logs (see Figure 408). They are displayed by enabling outputs from the Window menu.
DDR register loading (optional)
Once connected in DDR interactive mode, the current DDR configuration can be loaded in
SYSRAM.
This step is optional if the used U-Boot SPL already contains the required configuration. It triggers the DDR Controller and PHY initialization with those registers, and allows the user to quickly test a configuration without generating the device tree and dedicated U-Boot SPL binary file.
5.4.3 DDR testing
Prerequisites
To proceed with DDR testing:
• The DDR suite must be in connected state
• The DDR configuration must be available in memory, either with the U-Boot SPL (with DDR register file in Device Tree) or in the DDR registers (see Section 5.4.2).
DDR test list
DDR tests are part of the U-Boot SPL (see Figure 410).
Figure 410. DDR test list from U-Boot SPL
New tests can be added by modifying the U-boot SPL.
Most of the tests come with parameters to be set prior to execution, such as: • Address: the memory address where the test is executed. All writes and reads are performed on this address. The given address has to be located in the DDR memory region [DDR base address, DDR base address + DDR size].
• On STM32MP15, DDR base address is 0xC0000000 (as an example, DDR size for 4 Gbits is 0x20000000). • Loop: number of test iterations before verdict. Same test is repeated [Loop] times. Verdict OK if all tests are OK, KO otherwise.
• Size: the byte size of the region to test. It must be a multiple of 4 (read/writes are performed on 32-bit unsigned integers), with minimal value equal to 4, and up to DDR size.
• Pattern: the 32-bit pattern to be used for read / write operations.
The DDR Suite embeds an auto-correction feature preventing users to specify wrong values.
All tests are performed with Data cache disabled and Instruction cache enabled.
DDR test results
The test verdict is reported by the U-Boot SPL: the parameters used for the tests are recalled, along with Pass/Fail status and results details (see Figure 411). The test history is available in the output and Logs panels (see Figure 412).
5.5 STM32CubeMX Memory Management Tool
The Memory Management Tool (MMT) displays the memory map and defines memory attributes applied in user projects opened/created in STM32CubeMX.
The tool is located in the “Tools” tab. It allows the user to declare memory regions (referred to as application regions or AppReg) at application level.
The HW constraints related to TrustZone, Memory Protection Unit, and the memory granularity are handled by MMT and made transparent to the user, so that the focus can be put on the memory regions. A linker file is generated according to the application regions declared and configured by the user.
The MMT key features are:
• Memory map display
• Application regions management
• Linker file generation
MMT interacts with peripherals starting from the moment the user enters its interface:
• Checks their settings
• Updates other peripherals involved in memory map configuration The peripherals are updated only when the first toggle button is ON.
Figure 413. Regions settings to peripherals ON
MMT updates the linker scripts only when the second toggle button is ON.
Figure 414. Regions settings to linker files ON
The applicative regions are saved into the user project even if the first toggle button is OFF.
Figure 415. Regions settings to peripherals OFF
Figure 416. Recommendation for the configuration of MMT
5.5.1 STM32H5, STM32U3, STM32U5, STM32WBA5, STM32WBA5M,
and STM32WBA6 with TrustZone activated
Feature: MMT usage, pinout, and configuration user interface
When the first toggle button is ON (see Figure 413), SAU, GTZC, Cortex-M33 (MPU), and FLASH configurations are under MMT control: their modes and parameters become read-only.
Feature: MMT usage and linker script
Linker files content is generated according to the configuration of application regions.
MS81244V1
Linker files contents are generated as the MMT is used.
For the following features: SAU, GTZC, Cortex-M33 MPU, and FLASH, the memory handle is not under MMT control, so the user can update their setting.
Figure 418. MMT view
Choose a supported MCU (STM32U585x in this example).
Figure 419. Start a project
Press the “Start Project” button, and then choose the “with TrustZone activated ?” option.
Choose the “Tools” tab followed by the “Memory Management” option to display the Memory Management Tool (see Figure 421).
Figure 421. Default settings
The middle panel represents the memory, split into two columns: the left one is the memory seen by the core(s), the right one the memory set up for the application.
In this example there are two projects, a secure and a nonsecure one. The application region allocated to the secure project is green, the nonsecure application region is pink. The reserved memory regions are gray.
For the new project created under STM32CubeMX the tool creates the default application region to generate a valid project.
Region information
Clicking on a particular region in the Application Regions column shows the associated details on the left hand side.
You can choose to hide the name of the reserved region, or hide the Secure/Non Secure indication close to the region name (the secure/nonsecure indication is indicated by the color).
Figure 422. Region information
Code generation configuration
The application regions settings can be applied to peripherals on the left of the screen. The concerned peripherals are shown on the associated tooltip. This can impact their availability on the pinout screen configuration.
Figure 423. Tooltip
In this example, on the Pinout & Configuration panel, CORTEX_M33, FLASH, and GTZC are set, and correspond to the region configuration on the Memory Management Tool. They are grayed out, as they cannot be modified.
When an IP is under MMT control, a tooltip provides the info shown in Figure 425.
Figure 425. IP under control
Apply Application Regions settings to linker files
When this button is on, the linker scripts for the secure and non secure applications are generated, taking into account the configuration.
Figure 426. Linker files update
This example uses the FMC. Go to the Pinout & Configuration window (see Figure 427) and enable the IP.
Figure 427. Configure an external memory
When going back to the MMT, a new region corresponding to the added FMC is created.
Figure 428. New region created
Add a new region by pressing the plus button appearing in the white space when hovering with the mouse.
To add another external memory, go to the Pinout & Configuration view, and add OCTOSPI1 to Cortex-M33 Secure. Choose Single SPI, and specify Device Size and Device Type.
Figure 430. Adding a new memory
On the MMT there is now a new entry with OCTOSPI1.
• For our example, we need half of the available 128 Mbytes.
• Press the “+” button, set a name for the region (for instance: MyExternalRAM), and put 64 MB for its size.
Figure 431. Memory assignment
Configuring a memory region using the left panel
With the left panel (see Figure 432) you can adjust items such as starting position and size. In this example, the added region must be adjusted: we want it to be allocated to the non secure project, and to start in the middle of the RAM. By adjusting those values, the expected results appear (see Figure 433). The color is now pink (nonsecure), and the region starts in the middle of the RAM (OctoSPI1).
Figure 432. Left panel configuration
Figure 433. Allocating a region
Setting up a middleware memory location
The application needs ThreadX. Go back to the “Pinout & Configuration” tab. Choose ThreadX, then use the Use Dynamic Allocation under Memory Configuration.
Figure 434. Middleware memory allocation
To finish the configuration, go back to MMT. We want ThreadX to use a dedicated application region for its heap memory allocation. To do so, simply click the RAM region, and reduce its size to 17 Kbytes using the left panel. We then add a new region to the newly freed space, and call it MyThreadXHeap.
As ThreadX has been selected, on the Pinout & Configuration you can see a tick box called ThreadX Heap section. When this box is selected, the tool ensures that ThreadX memory allocation happens only in that particular region.
Figure 435. Middleware heap configuration
For performance reasons, part of the application must run on the internal memory (much faster than the external memory). To do so, remap the added external RAM to an available internal memory region:
• Go to the Pinout & Configuration tab
• Enable ICACHE, select the Memory address remap tick box
• Select a region and set the memory size to 64 Mbytes
• Change the Remap address to 0x9000 0000
Figure 436. Remapping the memory
• Go back to the MMT tab. Region 0x9000 0000 is named with Remapped, with the amount of RAM previously selected.
Figure 437. Remapped region is renamed
• There is also a Remap – External RAM(OCTOSPI1) added at address 0x0000 0000.
Figure 438. Remapped start address
• Add a new region named “MyRemappedRAM” at that address.
Figure 439. New region remapped
The default regions cannot be removed, but can be resized. As an example, the FLASH is where the application code is hosted. You cannot untick the Default Region.
Figure 440. Resizing default region
Changing the security of an application region mapped on aliased RAM or FLASH moves it in an aliased RAM or FLASH corresponding to the new security setting. Graphically, the region moves up and down, depending on the area it will go, as the same physical memory is seen by the core at different locations.
Code generation
• Go to the project manager, set a name to your project, Choose CubeIDE as a toolchain and press GENERATE CODE
• Navigate to the generated Secure Project and open the linker definition file. Under the Memories definition you will see the defined memories with their start address and
length. This file shows only the secure regions in green. Open the nonsecure linker file and check the same location for the memory regions allocated to the nonsecure area.
Figure 442. Memory map in linker file
5.5.3 STM32H7 single core and STM32U5 without TrustZone activated
Feature: MMT usage, pinout, and configuration user interface
When the first toggle button is ON, Cortex-M33 (MPU for STM32U5) and Cortex-M7 (MPU for STM32H7) are under MMT control (see, respectively, Figure 443 and Figure 444): modes and parameters become read-only.
The middle panel (see, respectively, Figure 445 and Figure 446 for STM32U5 and STM32H7) represents the memory, split into two columns: the left one is the memory seen by the core(s), the right one the memory set-up for the application.
For the new project created under STM32CubeMX the tool creates the default application region to generate a valid project.
Figure 443. MMT usage (STM32U5)
Figure 444. MMT usage (STM32H7 single core)
Figure 445. MMT view for U5 without TrustZone
The middle panel represents the memory, split into two columns: the left one is the memory seen by the core(s), the right one the memory set-up for the application.
For the new project created under STM32CubeMX the tool creates the default application region to generate a valid project. The default data region can be updated by the user to choose another region as RAM, but there must always be a default data region ( Figure 447).
Figure 447. Default data region
FMC impact on MMT
When activating FMC and SDRAM Bank1, a tab mapping (see Figure 448) is displayed, with three options:
1. Default mapping (see Figure 449): MMT initializes as default position of SDRAM Bank1, SDRAM Bank2, and NOR PSRAM (default viewer of MMT)
2. NOR/PSRAM bank and SDRAM Bank1/2 are swapped: MMT swaps the position of SDRAM Bank1 and NOR PSRAM Bank1 (see Figure 450 and Figure 451)
3. SDRAM Bank2 remapped on FMC Bank2 and still accessible at default mapping: MMT updates the position of SDRAM Bank1 to be remapped on position of FMC Bank2 (see Figure 452 and Figure 453)
Figure 453. After remapping
ETH impact on MMT for STM32H7 single core
An example of MMT configuration of the ETH IP on the STM32H723VETx MCU
1. Activate the IP ETH:
– MMT creates three application regions within the MMT view.
– To change the start address and the size of each region, update the ETH parameters.
2. Press the radio button “Apply Application region Settings to Peripherals ON”, ETH will be partially under MMT control.
3. Press the Generate Code button to generate code for both applications.
– Apply Application Regions settings to linker files:
4. When this button is on, the linker scripts are generated, considering the configuration.
5. After the code generation, navigate to the generated folder:
– Open the linker definition file.
– Under the Memories definition you can see the memories with their start address and length, according to the configuration made in STM32CubeMX.
Figure 454. ETH MMT regions
Figure 455. ETH configuration for STM32H723VETx MCU
5.5.4 STM32WBxx
Feature: MMT usage, pinout, and configuration user interface
When the first toggle button is ON, Cortex-M33 is under MMT control: its modes and parameters become read-only (see Figure 457).
The user must select the core and the STM32Cube firmware from a list. It is possible to choose any STM32Cube firmware version (see Figure 458).
The list proposed to user contains only the firmwares found in
STM32Cube_FW_WB_Vx/Projects / STM32_Copro_Wireless_Binaries/STM32WBxx (all .bin files). Firmware Update Service (FUS) and SafeBoot firmware are not proposed, so they are not in the MMT list.
This example is based on an STM32WB5x MCU, so the list must contain only stm32wb5x_x binaries. The button “Refresh” is used to refresh the binaries list version in the repository of STM32Cube firmware (see Figure 459).
Figure 459. MMT configuration for STM32WB5x
After selecting the binary firmware, the MMT view is displayed and the reserved regions of Cortex M0+ are created.
The middle panel represents the memory, split into two columns: the left one is the memory seen by the core(s) Cortex-M4, the right one the memory set-up for the application.
For the new project created under STM32CubeMX the tool creates the default application region to generate a valid project.
5.5.5 STM32H7 Dual-core without Trust Zone activated
Feature: MMT usage, pinout, and user interface configuration
When the first toggle button is ON, Cortex-M7_BOOT (MPU) and Cortex-M7_APPLI (MPU) are under MMT control: their modes and parameters become read-only.
Figure 460. Cortex_M7 mode and configuration
Feature: MMT usage and linker script
When the two radio buttons are activated, the memory management parameters are available, and the linker file content is generated according to the configuration of application regions.
There are two possible configurations of the application regions for the code generation:
• First configuration:
• Second configuration:
The Cortex-M7 and Cortex-M4 contexts are managed by the MMT. Each context has its own application region (AppReg0 and AppReg1, respectively).
User interface
Figure 462. Default settings
The middle panel represents the memory, split into three columns: the left one is the memory seen by the cores (CM7 and CM4), the middle one the memory set-up for the application in Context Cortex-M7, the right one the memory set-up for the application in the Context Cortex-M4.
For the new project created under STM32CubeMX, the tool creates the default application region to generate a valid project.
Region information
Clicking on a particular region in the Application Regions column shows the associated details on the left hand side.
STM32CubeMX automatically adds a 4 Gbytes region for the system core, even if you are not planning to use the MMT.
An example of MMT configuration of the OPENAMP Middleware on the STM32H755XIH6TR MCU
Below are the steps for configuring the MMT with OPENAMP activated on the STM32H755XIH6TR MCU.
1. Choose a supported MCU.
Figure 463. Choose an STM32H7 dual-core product
2. Click on the Start Project button, then choose Yes on the “Memory Protection Unit for Cortex-M7” dialog box.
Figure 464. Region 0 added
Note: STM32CubeMX applies the default configuration, then adds a 4 Gbytes region called “Region 0” under the Cortex_M7 parameters. The new parameters can be checked using the Pinout and Configuration tab.
3. Select “Tools” in the toolbar
– Choose Memory Management.
– Activate the Memory Management Tool support by clicking the button “Apply Application Regions Settings to Peripherals”.
Figure 465. Activate Memory Management support
The default application regions are in exclusive mode (context sharing is unselected). A reserved region in the other context is created and mentioned as “Mx non-shared region”.
Figure 466. Default setting for new application region
4. Add a new region by pressing the “+” button that appears in the white space when hovering with the mouse.
5. Select “Context sharing (M7, M4)”, automatically another region is created with the same name, start address, and size.
6. Select the Project Manager tab.
7. Give a name to the project and press the Generate Code button.
8. OPENAMP activation
– Configure the NVIC1 and 2 and select their related HSEM global interrupts. – Activate the Middleware OPENAMP_M4.
– MMT creates two application regions for each core. The Master regions are defined by attribute mode.
Figure 468. Configure NVIC1 and NVIC2, and select their HSEM global interrupt
Figure 470. OPENAMP_M4 parameters settings
Press the Generate Code button to generate the code for both applications.
Apply Application Regions settings to linker files
When the second radio button is on, the linker scripts for the CM7 and CM4 projects are generated considering the configuration.
Figure 472. Linker files update (stm32h755xxx_flash_cm4.icf)
The middleware can be enabled or disabled:
• If disabled, it automatically chooses the configured memory along with the associated driver and sets the execution memory location in the linker file.
• If enabled, the two regions and corresponding ‘export symbol’ must be added in the generated linker file.
After the code generation, navigate to the generated folder to check the linker file updates.
Example of MMT configuration of the ETH on STM32H755XIH6TR MCU
1. Activate the IP ETH: MMT creates three application regions for each core. To change the start address and the size of each region, update the ETH parameters.
Figure 474. Configuration of ETH IP
2. Press the radio button “Apply Application region Settings to Peripherals ON”, ETH will be partially under MMT control.
3. Press the Generate Code button to generate code for both applications.
Figure 476. IP configuration
Apply Application Regions settings to linker files:
4. When this button is on, the linker scripts for the CM7 project and CM4 project are generated, considering the configuration.
5. After the code generation, navigate to the generated folder:
– Under the CM7 Project, open the linker definition file.
– Under the Memories definition you can see the defined memories with their start address and length, according to the configuration made in STM32CubeMX.
Figure 477. Defined memories under the linker file (Cortex-M7)
Figure 478. Defined memories under the linker file (Cortex-M4)
Feature: MMT usage, pinout, and configuration user interface
When the first toggle button is ON, Cortex-M7_BOOT (MPU) and Cortex-M7_APPLI (MPU) are under MMT control: their modes and parameters become read-only.
Figure 479. MMT usage
Linker files content is generated according to the configuration of application regions.
Only “Boot” and “Appli” contexts are managed by the MMT. Each context has its own application region (AppReg0 and AppReg1, respectively).
User interface
Figure 480. Default settings
The middle panel represents the memory, split into three columns: the left one is the memory seen by the core(s), the middle one the memory set-up for the application in Context Boot, the right one the memory set-up for the application in the Context Appli.
For the new project created under STM32CubeMX, the tool creates the default application region to generate a valid project.
Region information
Clicking on a particular region in the Application Regions column shows the associated details on the left hand side.
STM32CubeMX automatically adds a 4-Gbyte region for the system core, even if you are not planning to use the MMT.
1. Choose a supported MCU (the following example is based on STM32H7R3A8I6).
Figure 481. Choose an STM32H7R product
2. Click on the Start Project button, then choose “Yes” on the “Memory Protection Unit for Cortex-M7” dialog box.
STM32CubeMX applies the default configuration, then adds a 4-Gbyte region called
“Region 0” under the CORTEX_M7_BOOT parameters, and a 4-Gbyte region called “Region 0” under the CORTEX_M7_APPLI parameters. The two regions start at the same address, adjust it to avoid overlap.
The new parameters can be checked using the Pinout and Configuration tab.
Figure 483. Region0 added
3. Select the Tools tab:
a) Choose Memory Management
b) Activate the Memory Management Tool support by clicking on “Apply Application
Regions Settings to Peripherals”
Figure 484. Activate Memory Management support
4. Select the Project Manager tab
5. Give a name to the project and press the Generate Code button: a warning message is displayed.
The flash region overlap issue can be solved in different ways, the preferred one goes through the following steps:
a) Select the Pinout and configuration tab
b) Enable XSPI1 for the boot context and choose the ‘Single SPI’ mode
Figure 486. Configure the XSPI
c) Activate the Middleware EXTMEM_MANAGER for the boot context:
> MMT solves the issue
> Press the Generate Code button to generate code for both applications. The overlap message does not appear any longer.
Figure 487. EXT_MEM_MANAGER
Code generation configuration
The application regions settings can be applied to peripherals on the left-hand side of the screen. The concerned peripherals are shown on the associated tooltip. This can impact their availability on the pinout screen configuration.
Figure 488. Tooltip
In this example, on the Pinout & Configuration panel, Cortex-M7_BOOT (MPU) and Cortex-M7_APPLI (MPU) are set and correspond to the region configuration on the Memory Management Tool. They are grayed out, as they cannot be modified.
Figure 489. IP configuration
Apply Application Regions settings to linker files
When this button is on, the linker scripts for the Boot project and Appli project are generated, taking into account the configuration.
Figure 490. Linker files update
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Figure 491. Memory assignment for context Boot H7RS
EXTMEM_MANAGER when using H7Rx/H7Sx
The middleware can be used with the “Select boot code generation” disabled or enabled.
If disabled, MMT automatically chooses the configured memory along with the associated driver, and sets the execution memory location in the linker file. This is the most straightforward way of configuring an external memory.
If enabled, by activating the “Select boot code generation” you can choose “Execute in Place” or “Load and Run”
• Execute in Place chooses and configures the memory zones
• Load and Run lets the user choose source, destination memory, and addresses to jump to. The configuration is translated into the linker file. The user must provide the source and destination addresses.
Figure 492. EXTMEM_MANAGER “Select boot code generation” disabled
After the code generation, navigate to the generated folder.
• Under the boot Project, open the linker definition file. • Under the Memories definition you can see the defined memories with their start address and length, according to the configuration made in STM32CubeMX.
Figure 497. Linker files
Three option bytes can be used to configure the regions in the MMT. To see them, activate the IP FLASH on the Pinout and Configuration tab.
Figure 498. Flash option bytes
The option bytes interacting with the MMT are:
• ECC_ON_SRAM:
– Linked to the AXI SRAM4 region on the MMT
– When value is “disable” or “no update”, the AXI SRAM4 region size is set to 72 KB
– When value is set to “enable” the AXI SRAM4 region is removed
• DTCM_AXI_SHARED:
– Linked to the AXI SRAM3 region on the MMT
– When set to 0 or 3, the AXI SRAM3 region size is set to 128 KB, and the size of region named DTCM is set to 64 KB
– When set to 1, the AXI SRAM3 region size is set to 64 KB, and the size of region named DTCM is set to 128 KB
– When set to 2, the AXI SRAM3 region is removed, and the size of region named DTCM is set to 192 KB
• ITCM_AXI_SHARED:
– Linked to the AXI SRAM1 region on the MMT
– When set to 0 or 3, the AXI SRAM1 region size is set to 128 KB
– When set to 1, the AXI SRAM1 region size is set to 64 KB
– When set to 2, the AXI SRAM1 region size is removed
Figure 499. ECC_ON_SRAM enabled and DTCM_AXI_SHARED set to 2
ETH impact on MMT when using H7RS/H7SX
An example of MMT configuration of the ETH IP on the STM32H7R3A8Ix MCU
1. Activate the IP ETH:
– MMT creates three application regions for each context.
– To change the start address and the size of each region, update the ETH parameters.
2. Press the radio button “Apply Application region Settings to Peripherals ON”, ETH will be partially under MMT control.
3. Press the Generate Code button to generate code for both applications.
– Apply Application Regions settings to linker files:
4. When this button is on, the linker scripts are generated, considering the configuration.
5. After the code generation, navigate to the generated folder:
– Open the linker definition file.
– Under the Memories definition you can see the memories with their start address and length, according to the configuration made in STM32CubeMX.
Figure 500. ETH MMT regions for STM32H7R3A8Ix
Figure 501. ETH configuration for STM32H7R3A8Ix
Figure 503. Defined memory regions under the linker file of the application context
Feature: MMT usage, pinout, and configuration user interface
When the first toggle button is ON, Cortex-M0+ (MPU) is under MMT control: its modes and parameters become read-only (see Figure 504).
Figure 504. MMT usage
The middle panel represents the memory, split into two columns: the left one is the memory seen by the core Cortex-M0+, the right one the memory set-up for the application.
Figure 505. User interface
For a new project created under STM32CubeMX, the MMT creates the default application region to generate a valid project.
Apply Application Regions settings to linker files
When this button is on, the linker scripts for the project are generated, considering the configuration.
• The REGION_ROM is a default code region used in linker.
• The linker file copies the STM32Cube firmware linkers files and only MMT region is updated or added.
• OTA tag is not managed by MMT and usually exists in the linker file.
Figure 506. Linker files update
Impact on STM32WB09 RADIO
When this IP is activated, a reserved region “Blue Core Config” calculated by value of CFG_NUM_RADIO_TASKS, which varies from 1 to 128, is added.
Figure 507. Impact on RADIO (STM32WB09)
MMT usage, pinout, and configuration of the user interface
MMT interaction with peripherals starts from the moment the user enters their interfaces:
• Checks their settings
• Updates other peripherals involved in the memory map configuration
The peripherals are updated only when the first toggle button is “ON” in the panel Memory Management (under STM32CubeMx Tools).
MMT updates the scripts only when the second toggle button is ON. The linker file content is generated according to the configuration of the application regions.
The applicative regions are saved in the user project even if the first toggle button is OFF.
Feature under MMT control for secure and nonsecure domains
When the first toggle button is ON, the following features are controlled by MMT (their modes and parameters become read-only):
• CORTEXM55-FSBL (MPU)
• CORTEXM55_S (MPU)
• CORTEXM55_NS (MPU)
• SAU
• RIF (RISAF panel)
Figure 508. Feature under MMT control (secure and nonsecure domains)
Feature under MMT control for secure domains
When the first toggle button is ON the following features are controlled by MMT (their modes and parameters become read-only):
• CORTEXM55-FSBL (MPU)
• CORTEXM55_S (MPU)
• RIF (RISAF panel)
Figure 509. Feature under MMT control (secure domains only)
Application regions for secure and nonsecure domains
Only FSBL, CORTEX_M55_S, and CORTEX_M55_NS contexts are managed by the MMT. Each context has its own application region.
In the memory layout the CORTEX_M55_S and CORTEX_M55_NS use the same column for application regions.
Figure 510. Memory layout for secure and nonsecure domains
Application regions for secure domains
Only FSBL and CORTEX_M55_S contexts are managed by the MMT. Each context has its own application region.
Figure 511. Memory layout for secure domains
Description of the memory layout in STM32CubeMX user interface
The memory is split in three columns:
1. The left one is the memory seen by the core(s)
2. The middle one is the memory set-up for the application in FSBL context
3. The right one is the memory set-up for the application in the Context Appli
For the new project under STM32CubeMX, the tool creates the default application region to generate a valid project.
Region information
Clicking on a particular region in the Application Regions column shows the associated details on the left-hand side.
Figure 512. Details about the clicked region in the FSBL context
STM32CubeMX automatically adds a 4-Gbyte region for the system core, even if you are not planning to use the MMT. Each region in the memory layout has its own characteristics, detailed at the bottom of the STM32CubeMX interface.
Figure 513. Regions designation for secure and nonsecure domains
Example of using MMT with STM32N6 products
1. Choose an MCU that supports the MMT feature (the following example is based on STM32N657Z0HxQ).
Figure 515. Project creation with an STM32N6 product
2. Choose the project structure, then initiate the project creation by clicking Start Project. Upon display of the TrustZone feature available dialog box, specify the domain configuration as Secure and Non-Secure domains before confirming with OK ( Figure 516). Choose the second option if you intend to work exclusively within secure domains ( Figure 517). STM32CubeMX applies the default configuration (RAM and FLASH regions are created in the MMT view).
Figure 516. Choosing the project structure (secure and nonsecure domains)
Figure 517. Choosing the project structure (secure domains)
3. Configure the MMT
a) Click on the Tools tab
b) Choose Memory Management panel
c) Activate the Memory Management Tool support by clicking on “Apply Application
Regions Settings to Peripherals”
Figure 518. MMT configuration (secure and nonsecure domains)
Figure 519. MMT configuration (secure domains)
4. Select the Project Manager tab
5. Give a name to the project and press the Generate Code button
Changes in RIF resulting from MMT activation
By selecting “Apply Application region Settings to Peripherals ON,” the RISAF feature (located in RIF panel) is put partially under MMT.
The RAM and flash memory regions are configured with the same security, read/write, and privilege parameters. They are represented as a single RISAF region in the view corresponding to RISAF 2 (CPU AXI RAM0).
Figure 520. Mapping between MMT regions and RISAF memory configurations
Configuration of memory regions in RISAF2 (CPU AXI RAM0) tab (region 2)
Under the RISAF2 (CPU AXI RAM0) tab, region 2 has two groups of settings:
• Fixed fields (grayed out): Region ID, Region Name, Start address Offset, Region size, and Filtering are read-only and cannot be modified.
• Controllable fields (editable): The security and access parameters (Secure, Read, Write, and Privilege) are editable and are updated by the (MMT).
The values that MMT can set for the Read, Write, or Privilege fields are 2 (00000010b) and 0 (00000000b).
Figure 521. Setting up the memory region of RISAF2 (CPU AXI RAM0) tab
Setting up memory subregions for RISAF 2 (CPU AXI RAM0) region 2
The Sub-Region A has two groups of settings:
• Fixed fields (grayed out): RISAF Region ID, SubRegion name, Start address Offset, Region size, SubRegion CID (fixed to 1) are read-only and cannot be modified.
• Controllable fields (editable): the security and access parameters (Secure, Read, Write, and Privilege are editable and are updated by the MMT.
Figure 522. Setting up memory subregions of RISAF 2 (CPU AXI RAM0) tab
Figure 523. Setting up memory regions of RISAF1 (TCM) tab
On RISAF 7 (FLEXRAM) tab, when the user adds an application region in ITCM or DTCM ranges MMT adds automatically in RISAF 7 (FLEXRAM) memory regions with the same start address as in the MMT layout.
Use the configuration shown in Figure 525 for the right mapping between MMT settings and RISAF 7 (FLEXRAM) memory regions.
Figure 525. Configurations needed for RAMCFG FLEXRAM
When FLEXRAM (RAMCFG) is active, not utilizing its default settings, and the user adds an application region in ITCM or DTCM ranges, the memory split is specifically defined. Example of configurations:
• D-TCM is set to SYSCFG_DTCM_256K
• I-TCM is set to SYSCFG_ITCM_256K
When adding a 256 KB application region that overlaps the ITCM and DTCM ranges:
• The configuration of RISAF1 (TCM) remains consistent for its allocated portion.
• Any memory belonging to that region above 0x340020000 is automatically redirected
(or split) and configured under RISAF7 (FLEXRAM). This segment starts at 0x340020000 and is treated as the beginning 0x00000000 offset of the RISAF7 region.
Figure 526. Setting up memory regions of RISAF1 (TCM) and RISAF7 (FLEXRAM) tabs
When the user applies a custom FLEXRAM configuration, such as:
• D-TCM to SYSCFG_DTCM_256K, I-TCM to SYSCFG_ITCM_64K, or
• D-TCM: SYSCFG_DTCM_256K, I-TCM: SYSCFG_ITCM_128K, or
• D-TCM: SYSCFG_DTCM_256K, I-TCM: SYSCFG_ITCM_256K
a warning appears, indicating that the flash memory region overlaps with the memory area reserved to FLEXRAM.
Figure 527. Overlap with FLEXRAM
To avoid the warning, locate the flash memory region to another range, and update the configuration of FLEXRAM.
On RISAF4 (NPN master1), RISAF5 (NPN master2), and RISAF6 (CPU master) tabs RISAF4/5 are available.
Configuration: add two application regions:
• Region 1: start address 0x34200000, size 1792 KB in FSBL (S) context
• Region 2: start address 0x24200000, size 1792 KB in Appli NS context
Figure 528. Configurations of the application regions on the MMT view
The MMT adds:
• Two RISAF regions in RISAF4 (secure region, nonsecure region), see Figure 529
• Two RISAF regions in RISAF5 (secure region, nonsecure region), see Figure 530
• Two RISAF regions in RISAF6 (CPU master), see Figure 531
Figure 529. Setting up memory regions of RISAF4 (NPU master 0)
Figure 531. Setting up memory regions of RISAF6 (CPU master)
The two secure regions in RISAF4 and RISAF5 are consolidated into a larger secure region, identified and managed in RISAF6. The two nonsecure regions in RISAF4 and RISAF5 are consolidated into a larger nonsecure region, identified and managed in RISAF6.
RISAF8(CACHEAXI):
• When the IP CACHEAXI is enabled, MMT must remove the address range shown in the figures below.
• Add application region in CACHEAXI range (CACHEAXI must be disabled)
• MMT add in RISAF 8(CACHEAXI) the regions with start offset like in MMT view RISAF9(VENCRAM):
When the IP VENC is enabled MMT must delete the range illustrated in the figure below.
Figure 536. VENC enable
Figure 537. MMT view for VENCRAM
• Adding application region in VENCRAM range(user should disable VENC when it is activated)
Figure 538. Adding regions in VERCRAM
Figure 539. RISAF9 VENCRAM
• MMT add the regions in RISAF9 (VENCRAM) with start offset like in MMT view.
On RISAF14(FMC) tab the available FMC (Flexible Memory Controller) ranges include:
• FMC Bank 1
• FMC SDRAM Bank 1
• FMC SDRAM Bank 2
Configuration:
• Configure the FMC IP
• Add application regions in FMC ranges
Figure 540. Configurations of FMC added regions in MMT view
MMT adds in RISAF14 (FMC) regions with the same start address as in MMT view (no offset).
Figure 541. Setting up the memory regions for the RISAF14 (FMC) tab
EXTMEM_MANAGER
Code generation configuration
• The application regions settings can be applied to peripherals on the left-hand side of the screen. The concerned peripherals are shown on the associated tooltip.
• The MMT configuration may impact their availability on the pinout screen configuration.
• The EXTMEM_MANAGER can be used with the “Select boot code generation” parameter enabled or disabled.
– If disabled, MMT automatically chooses the configured memory along with the associated driver and sets the execution memory location in the linker file. This is the most straightforward way of configuring an external memory.
– If enabled, by activating the “Select boot code generation” you can choose “Execute in Place” or “Load and Run”
Figure 542. EXTMEM_MANAGER in the MMT view
The activation of the EXMEM_MANAGER depends upon the XSPIx activation.
1. Go to the Pinout and Configuration tab
2. Enable XSPI1 for the FSBL context and choose “Single SPI” mode
3. Activate the middleware EXTMEM_MANAGER in the FSBL context
4. Activate XSPIM and XSPI instances (XSPI1/2/3) Figure 543. Setting up the XSPI feature
Figure 544. Setting Select boot code generation parameter for EXTMEM_MANAGER
For the selection of the boot system there are two possibilities:
1. Execute In Place (Figure 545) chooses and configures the memory zones.
2. Load and Run (Figure 547) lets the user choose source, destination memory, and addresses to jump to.The configuration is translated into the linker file. The user must provide the source and destination address.
Figure 545. Selection of the boot system - Execute In Place
Figure 546. Configuration of the MMT view after enabling XIP
Figure 548. Configuration of MMT view after choosing Load and Run as boot system
Once the code is generated, follow these steps:
1. Navigate to the generated project folder.
2. In the boot Project directory, open the linker definition file (usually an .ld or .icf file).
3. In the Memories definition section you can review the memory blocks (start addresses and lengths) that reflect your configuration settings.
Figure 549. Defined linker script for XIP
Figure 550. MMT linker file after choosing Load and Run as boot system
Example of MMT configuration for the ETH IP on the STM32N645B0HxQ MCU
Configure the ETH:
• For secure domains:
– Activate the ETH: MMT creates three application regions for each context Figure 551. ETH MMT regions for STM32N647L0HxQ
– Update the start address and the size of each region, update the ETH parameters.
– Press the radio button “Apply Application region Settings to Peripherals ON”, to make ETH partially under MMT control ( Figure 552).
– Press the Generate Code button to generate code for both applications.
– Apply Application Regions settings to linker files:
Figure 552. MMT view after adding ETH memory regions
When this button is on, the linker scripts are generated, considering the configuration. After the code generation, navigate to the generated folder:
– Open the linker definition file.
Figure 553. ETH linker file (fully secure domain only)
Figure 554. ETH MMT regions (secure domains only)
– Under the Memory definition you can see the memory parts with their start address and length, according to the configuration made in STM32CubeMX. If an application region overlaps an ETH region a warning is displayed in the MMT log.
Figure 555. Warning in case of overlap between application and ETH regions
The default parameters are used for the secure context, but if the selected context is nonsecure, other nonsecure parameters are displayed.
Impact of configuring the ETH memory regions with ETH on RISAF panels
Figure 556. RISAF 3 (CPU AXI RAM1) memory regions
For secure and nonsecure domains ETH application regions are created for the selected contexts.
Figure 557. ETH application regions for secure and nonsecure domains (part 1)
Figure 558. ETH application regions for secure and nonsecure domains (part 2)
5.5.9 Notification MMT/boot path (STM32H7RS and STM32H5)
After the activation of boot path and MMT, all regions of MMT are deleted and replaced by the regions of Boot path in Appli context.
In this example, we use the boot path OEM-iRoT for STM32H7RS and for STM32H5.
Figure 559. MMT/boot path (STM32H7RS)
The linker files are copied from STM32Cube firmware of boot path, and MMT integrates all added application regions (App_User).
• Open the linker files STM32H7S3I8KX_OEMiROT_Appli_app.ld or
STM32H523CETX_FLASH.ld (respectively, left or right side of Figure 561)