HAL IWDG How to Use ¶

group IWDG_How_To_Use

The independent watchdog (IWDG) peripheral offers a high safety level, thanks to its capability to detect malfunctions due to software or hardware failures. The IWDG is clocked by an independent clock, and stays active even if the main clock fails. In addition, the watchdog function is performed on the VDD voltage domain, allowing the IWDG to remain functional even in low-power modes. The IWDG is best suited for applications that require the watchdog to run as a totally independent process outside the main application, making it very reliable to detect any unexpected behavior.

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Main features ¶

The IWDG can be started by either software or hardware (configurable through option byte).

Note: If the user has chosen to start the IWDG in hardware mode, USE_HAL_IWDG_HARDWARE_START directive must be set to take into account the APIs associated with hardware mode.
The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays active even if the main clock fails.
Once the IWDG is started, the LSI is forced ON and both cannot be disabled except by a system reset.
Once enabled the IWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the downcounter before reaching 0x000 value (i.e. a reset is generated when the counter value rolls down from 0x001 to 0x000).
A MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window.
If required by application, an Early Wakeup Interrupt time can be configured in order to be warned before IWDG expiration. The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. This mechanism requires IWDG interrupt line to be enabled in NVIC. Once enabled, EWI interrupt cannot be disabled except by a system reset.
The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY modes (IWDG reset can wake up the CPU from STANDBY).
The IWDG counter input clock is derived from LSI clock divided by a programmable prescaler.
IWDG clock (Hz) = LSI_clock / (4 * Prescaler)
IWDG timeout (ms) = 1000 * (RL[11:0]) / IWDG clock (Hz) where RL[11:0] is the counter reload value.
IWDG Counter refresh is allowed between the following limits:
- min time (ms) = 1000 * (Counter - Window) / IWDG clock (The min time represents the minimum time before refresh is allowed)
- max time (ms) = 1000 * (Counter) / IWDG clock (The max time represents the maximum time before reset)
Typical values @32kHz (LSI)
- Step range: [125us ; 8ms] (The IWDG step represents the IWDG counter period)
- Timeout range (with RL[11:0] in [2 ; 4096]): [250us ; ~131s]
Typical values @250Hz (LSI / 128)
- Step range: [16ms ; 4,096s]
- Timeout range: [~66s ; ~16777s]
LSI management
- The IWDG timeout might vary due to LSI clock frequency dispersion. STM32U5xx devices provide the capability to measure the LSI clock frequency (LSI clock is internally connected to TIM16 CH1 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy.
- Default: Constant LSI_VALUE is defined based on the nominal LSI clock frequency. This frequency being subject to variations as mentioned above, default timeout has been specifically adjusted to accommodate the LSI startup time.
- The IWDG HAL driver gives the user the possibility to calculate his own LSI frequency and use it afterwards
- Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, Refer to DBGMCU module services to freeze or unfreeze IWDG during system low power modes.

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How to use ¶

The IWDG HAL driver can be used as follows:

Select the LSI frequency using the USE_HAL_IWDG_LSI_FREQ, the choice is either static or dynamic depending on this define.
Configure the allowed refresh period (minimum and maximum time values) and early interrupt time using HAL_IWDG_Start() function. The IWDG is automatically enabled and its downcounter is started.
HAL_IWDG_Start() computes and initializes prescaler, reload, window and early wake-up registers to values corresponding to the nearest achievable minimum, maximum and early interrupt times inputs.
HAL_IWDG_GetMaxTime() , HAL_IWDG_GetMinTime() and HAL_IWDG_GetEarlyWakeupInterruptTime() functions permits to retrieve the times actually set.
HAL_IWDG_GetStep_us() and HAL_IWDG_SetMinTime() permit to tune the refresh time.
HAL_IWDG_SetEarlyWakeupInterruptTime() permits to tune the the early interrupt time.
Care must be taken to provide a maximum time value greater than 0 to prevent generation of immediate reset.
If the Early Wakeup Interrupt (EWI) feature is enabled (early interrupt time not equal to 0), an interrupt is generated when the early wakeup time is reached. When HAL_IWDG_IRQHandler() is triggered by the interrupt service routine, Early Wakeup flag is automatically cleared and HAL_IWDG_EarlyWakeupCallback() callback is executed. User can add his own code by customization of callback HAL_IWDG_EarlyWakeupCallback() .
After IWDG first initialization, HAL_IWDG_SetLSIFrequency() can be called to set a more accurate LSI value. The HAL_IWDG_Start() must be called again to re-configure the IWDG. HAL_IWDG_GetLSIFrequency() permits to retrieve the LSI value used by IWDG driver.
Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_IWDG_Refresh() function.

Callback registration: ¶

The compilation flag USE_HAL_IWDG_REGISTER_CALLBACKS allows the user to configure dynamically the driver callbacks.
Use HAL_IWDG_RegisterEarlyWakeupCallback() function to register IWDG Early Wakeup callback.
This function takes as parameters the HAL peripheral handle and a pointer to the user callback function.