LL ADC Constants

Definitions of constants used by helper macro

group ADC_LL_EC_HELPER_MACRO

Defines

LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF)

Temperature calculation error using helper macro LL_ADC_CALC_TEMPERATURE() , due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value.

ADC flags

group ADC_LL_EC_FLAG

Flags defines which can be used with LL_ADC_ReadReg function.

Defines

LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY

ADC flag instance ready

LL_ADC_FLAG_EOC ADC_ISR_EOC

ADC flag group regular end of unitary conversion

LL_ADC_FLAG_EOS ADC_ISR_EOS

ADC flag group regular end of sequence conversions

LL_ADC_FLAG_OVR ADC_ISR_OVR

ADC flag group regular overrun

LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC flag group regular end of sampling phase

LL_ADC_FLAG_JEOC ADC_ISR_JEOC

ADC flag group injected end of unitary conversion (specific to ADC instance: ADC1, ADC2)

LL_ADC_FLAG_JEOS ADC_ISR_JEOS

ADC flag group injected end of sequence conversions (specific to ADC instance: ADC1, ADC2)

LL_ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC flag analog watchdog 1 out of window event.

LL_ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC flag analog watchdog 2 out of window event.

LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC flag analog watchdog 3 out of window event.

LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL

ADC flag end of calibration (specific to ADC instance: ADC4)

LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY

ADC flag internal voltage regulator (LDO) ready

LL_ADC_FLAG_ALL ( LL_ADC_FLAG_ADRDY

\

|

LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP

\

|

LL_ADC_FLAG_JEOC | LL_ADC_FLAG_JEOS

\

|

LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3

\

|

LL_ADC_FLAG_EOCAL | LL_ADC_FLAG_LDORDY )

ADC all flags

LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST

ADC flag multimode master instance ready

LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV

ADC flag multimode slave instance ready

LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST

ADC flag multimode master group regular end of unitary conversion

LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV

ADC flag multimode slave group regular end of unitary conversion

LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST

ADC flag multimode master group regular end of sequence conversions

LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV

ADC flag multimode slave group regular end of sequence conversions

LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST

ADC flag multimode master group regular overrun

LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV

ADC flag multimode slave group regular overrun

LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST

ADC flag multimode master group regular end of sampling phase

LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV

ADC flag multimode slave group regular end of sampling phase

LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST

ADC flag multimode master group injected end of unitary conversion

LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV

ADC flag multimode slave group injected end of unitary conversion

LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST

ADC flag multimode master group injected end of sequence conversions

LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV

ADC flag multimode slave group injected end of sequence conversions

LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST

ADC flag multimode master analog watchdog 1 of the ADC master

LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV

ADC flag multimode slave analog watchdog 1 of the ADC slave

LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST

ADC flag multimode master analog watchdog 2 of the ADC master

LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV

ADC flag multimode slave analog watchdog 2 of the ADC slave

LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST

ADC flag multimode master analog watchdog 3 of the ADC master

LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

ADC flag multimode slave analog watchdog 3 of the ADC slave

LL_ADC_FLAG_LDORDY_MST ADC_CSR_LDORDY_MST

ADC flag internal voltage regulator (LDO) ready of the ADC master

LL_ADC_FLAG_LDORDY_SLV ADC_CSR_LDORDY_SLV

ADC flag internal voltage regulator (LDO) ready of the ADC slave

ADC interruptions for configuration (interruption enable or disable)

group ADC_LL_EC_IT

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Defines

LL_ADC_IT_ADRDY ADC_IER_ADRDYIE

ADC interruption instance ready

LL_ADC_IT_EOC ADC_IER_EOCIE

ADC interruption group regular end of unitary conversion (specific to ADC instance: ADC1, ADC2)

LL_ADC_IT_EOS ADC_IER_EOSIE

ADC interruption group regular end of sequence conversions (specific to ADC instance: ADC1, ADC2)

LL_ADC_IT_OVR ADC_IER_OVRIE

ADC interruption group regular overrun

LL_ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC interruption group regular end of sampling phase

LL_ADC_IT_JEOC ADC_IER_JEOCIE

ADC interruption group injected end of unitary conversion

LL_ADC_IT_JEOS ADC_IER_JEOSIE

ADC interruption group injected end of sequence conversions

LL_ADC_IT_AWD1 ADC_IER_AWD1IE

ADC interruption analog watchdog 1

LL_ADC_IT_AWD2 ADC_IER_AWD2IE

ADC interruption analog watchdog 2

LL_ADC_IT_AWD3 ADC_IER_AWD3IE

ADC interruption analog watchdog 3

LL_ADC_IT_EOCAL ADC_IER_EOCALIE

ADC interruption end of calibration (specific to ADC instance: ADC4)

LL_ADC_IT_LDORDY ADC_IER_LDORDYIE

ADC interruption voltage regulator (LDO) ready (specific to ADC instance: ADC4)

LL_ADC_IT_ALL ( LL_ADC_IT_ADRDY

\

|

LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR | LL_ADC_IT_EOSMP

\

|

LL_ADC_IT_JEOC | LL_ADC_IT_JEOS

\

|

LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3

\

|

LL_ADC_IT_EOCAL | LL_ADC_IT_LDORDY )

ADC all interruptions

ADC registers compliant with specific purpose

group ADC_LL_EC_REGISTERS

Defines

LL_ADC_DMA_REG_REGULAR_DATA

(0x00000000UL) /* ADC group regular conversion data register

(corresponding to register DR) to be used with ADC configured in independent

mode.

Without DMA transfer, register accessed by LL function

@ref

LL_ADC_REG_ReadConversionData32

() and

other functions @ref LL_ADC_REG_ReadConversionDatax() */


LL_ADC_DMA_REG_MM_REGULAR_PACK_DATA

(0x00000001UL) /* ADC multimode group regular conversion data register

(corresponding to register CDR) to be used with ADC configured in multimode

(availability depending on STM32 devices).

Register with data packing: ADC master and slave data are concatenated

in a single register, therefore constraint on data width.

Data width depends on multimode configuration (refer to literals

LL_ADC_MULTI_REG_DMA_RES_x).

Without DMA transfer, register accessed by LL function

@ref

LL_ADC_REG_ReadMultiConversionData32 () */
LL_ADC_DMA_REG_MM_REGULAR_UNPACK_DATA

(0x00000002UL) /* ADC multimode group regular conversion data register

(corresponding to register CDR2) to be used with ADC configured in multimode

(availability depending on STM32 devices).

Register without data packing: ADC master and slave data are alternatively set

in full register width 32 bits, therefore no constraint on data width.

Register intended to be used only with DMA transfer. */


ADC common - Clock source

group ADC_LL_EC_COMMON_CLOCK_SOURCE

Defines

LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)

ADC asynchronous clock without prescaler

LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 2

LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 4

LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 6

LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2)

ADC asynchronous clock with prescaler division by 8

LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 10

LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 12

LL_ADC_CLOCK_ASYNC_DIV16

(ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \

| ADC_CCR_PRESC_0)


ADC asynchronous clock with prescaler division by 16

LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)

ADC asynchronous clock with prescaler division by 32

LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 64

LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 128

LL_ADC_CLOCK_ASYNC_DIV256

(ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \

| ADC_CCR_PRESC_0)


ADC asynchronous clock with prescaler division by 256

ADC common - Measurement path to internal channels

group ADC_LL_EC_COMMON_PATH_INTERNAL

Defines

LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)

ADC measurement paths all disabled

LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)

ADC measurement path to internal channel VrefInt

LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN)

ADC measurement path to internal channel temperature sensor

LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

ADC measurement path to internal channel Vbat

LL_ADC_PATH_INTERNAL_VDDCORE ( LL_ADC_PATH_INTERNAL_VREFINT

\

|

LL_ADC_CHANNEL_DIFF_VREFINT_VDDCORE )

ADC measurement path to internal channel VddCore, specific to ADC instance: ADC4

LL_ADC_PATH_INTERNAL_DAC1CH1 (0x00000000UL)

ADC measurement path to internal channel DAC1 channel 1, specific to ADC instance: ADC4

LL_ADC_PATH_INTERNAL_DAC1CH2 (ADC_OR_CHN21SEL)

ADC measurement path to internal channel DAC1 channel 2, specific to ADC instance: ADC4

ADC instance - Calibration mode for offset and linearity

group ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY

Defines

LL_ADC_CALIB_OFFSET ( LL_ADC_CALIB_FACTOR_OFFSET_REGOFFSET )

Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes.

LL_ADC_CALIB_LINEARITY ( LL_ADC_CALIB_FACTOR_LINEARITY_REGOFFSET

Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes.

LL_ADC_CALIB_OFFSET_LINEARITY ( LL_ADC_CALIB_FACTOR_LINEARITY_REGOFFSET

\

| ADC_CR_ADCALLIN)


Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes.

ADC indexes for linear calibration

group ADC_LL_EC_CALIBRATION_LINEARITY_INDEX

Defines

LL_ADC_CALIB_OFFSET_INDEX (0x00000000UL)

Offset Calibration Index

LL_ADC_CALIB_LINEARITY_INDEX1 (ADC_CR_CALINDEX0)

Linearity Calibration Index 1

LL_ADC_CALIB_LINEARITY_INDEX2 (ADC_CR_CALINDEX1)

Linearity Calibration Index 2

LL_ADC_CALIB_LINEARITY_INDEX3 (ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0)

Linearity Calibration Index 3

LL_ADC_CALIB_LINEARITY_INDEX4 (ADC_CR_CALINDEX2)

Linearity Calibration Index 4

LL_ADC_CALIB_LINEARITY_INDEX5 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX0)

Linearity Calibration Index 5

LL_ADC_CALIB_LINEARITY_INDEX6 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1)

Linearity Calibration Index 6

LL_ADC_CALIB_LINEARITY_INDEX7

(ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 \

| ADC_CR_CALINDEX0)


Linearity Calibration Index 7

LL_ADC_CALIB_INTEROFFSET_INDEX8 (ADC_CR_CALINDEX3)

Linearity Calibration Index 8

ADC extended calibration mode

group ADC_LL_EC_CALIBRATION_EXTENDED_MODE

Defines

LL_ADC_CALIB_EXTENDED_CAL_FACTOR_MSK (0xFFFFFFFFUL)

Extended calibration mode factor mask

LL_ADC_CALIB_EXTENDED_CAL_FACTOR (0x03021100UL)

Extended calibration mode factor, refer to ref manual for value

ADC instance - Resolution

group ADC_LL_EC_RESOLUTION

Defines

LL_ADC_RESOLUTION_14B (0x00000000UL)

ADC resolution 14 bit (ADC1, ADC2 only)

LL_ADC_RESOLUTION_12B ( ADC_CFGR1_RES_0)

ADC resolution 12 bit

LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_1 )

ADC resolution 10 bit

LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)

ADC resolution 8 bit

LL_ADC_RESOLUTION_6B

(ADC_CFGR1_RES_1 \

<<

LL_ADC_RESOLUTION_ADC4_PROCESSING )

ADC resolution 6 bit (ADC4 only) (value shift out of ADC_CFGR1_RES range, post-processing when applied with ADC4)

ADC instance - Data alignment

group ADC_LL_EC_DATA_ALIGN

Defines

LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

LL_ADC_DATA_ALIGN_LEFT (ADC4_CFGR1_ALIGN)

ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)

ADC left Shift

group ADC_LL_EC_LEFT_BIT_SHIFT

Defines

LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL)

ADC conversion data not shifted (alignment right)

LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0)

ADC conversion data shift left of 1 bit (data multiplicated by 2). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1)

ADC conversion data shift left of 2 bits (data multiplicated by 4). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)

ADC conversion data shift left of 3 bits (data multiplicated by 8). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2)

ADC conversion data shift left of 4 bits (data multiplicated by 16). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)

ADC conversion data shift left of 5 bits (data multiplicated by 32). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)

ADC conversion data shift left of 6 bits (data multiplicated by 64). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_7

(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 \

| ADC_CFGR2_LSHIFT_0)


ADC conversion data shift left of 7 bits (data multiplicated by 128). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3)

ADC conversion data shift left of 8 bits (data multiplicated by 256). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)

ADC conversion data shift left of 9 bits (data multiplicated by 512). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)

ADC conversion data shift left of 10 bits (data multiplicated by 1024). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_11

(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 \

| ADC_CFGR2_LSHIFT_0)


ADC conversion data shift left of 11 bits (data multiplicated by 2048). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)

ADC conversion data shift left of 12 bits (data multiplicated by 4096). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_13

(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 \

| ADC_CFGR2_LSHIFT_0)


ADC conversion data shift left of 13 bits (data multiplicated by 8192). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_14

(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 \

| ADC_CFGR2_LSHIFT_1)


ADC conversion data shift left of 14 bits (data multiplicated by 16384). Specific to ADC instance: ADC1, ADC2.

LL_ADC_LEFT_BIT_SHIFT_15

(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 \

| ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)


ADC conversion data shift left of 15 bits (data multiplicated by 32768). Specific to ADC instance: ADC1, ADC2.

ADC instance - Low power mode

group ADC_LL_EC_LP_MODE

Defines

LL_ADC_LP_MODE_NONE (0x00000000UL)

No ADC low power mode activated

LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY)

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode() .

ADC instance - Low power mode auto power-off

group ADC_LL_EC_AUTOPOWEROFF_MODE

Defines

LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL)

ADC low power mode auto power-off disabled

LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PWRR_AUTOFF)

ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function LL_ADC_SetLPModeAutoPowerOff() . It can be combined with mode low power mode auto wait.

ADC instance - Autonomous deep power down mode

group ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE

Defines

LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL)

ADC deep power down in autonomous mode disabled

LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PWRR_DPD)

ADC deep power down in autonomous mode enabled

ADC instance - VREF protection mode

group ADC_LL_EC_VREF_PROTECTION_MODE

Defines

LL_ADC_VREF_PROT_DISABLE (0x00000000UL)

ADC Vref+ protection disabled

LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE (ADC4_PWRR_VREFPROT)

ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during one ADC4 clock cycle to avoid noise on Vref+.

LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE

(ADC4_PWRR_VREFPROT \

| ADC4_PWRR_VREFSECSMP)


ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during two ADC4 clock cycles to avoid noise on Vref+.

ADC instance - Offset number

group ADC_LL_EC_OFFSET_NB

Defines

LL_ADC_OFFSET_1 ( LL_ADC_OFR1_REGOFFSET )

ADC offset instance 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

LL_ADC_OFFSET_2 ( LL_ADC_OFR2_REGOFFSET )

ADC offset instance 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

LL_ADC_OFFSET_3 ( LL_ADC_OFR3_REGOFFSET )

ADC offset instance 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

LL_ADC_OFFSET_4 ( LL_ADC_OFR4_REGOFFSET )

ADC offset instance 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel assigned on ADC group regular or injected sequencer)

ADC instance - Offset signed saturation mode

group ADC_LL_EC_OFFSET_SIGNED_SATURATION

Defines

LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL)

ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4)

LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSAT)

ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4)

ADC instance - Offset unsigned saturation mode

group ADC_LL_EC_OFFSET_UNSIGNED_SATURATION

Defines

LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE (0x00000000UL)

ADC offset unsigned saturation is disabled (among ADC selected offset number 1, 2, 3 or 4)

LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE (ADC_OFR1_USAT)

ADC offset unsigned saturation is enabled (among ADC selected offset number 1, 2, 3 or 4)

ADC instance - Offset sign

group ADC_LL_EC_OFFSET_SIGN

Defines

LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL)

ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4)

LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS)

ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4)

ADC instance - Groups

group ADC_LL_EC_GROUPS

Defines

LL_ADC_GROUP_REGULAR (0x00000001UL)

ADC group regular (available on all STM32 devices)

LL_ADC_GROUP_INJECTED (0x00000002UL)

ADC group injected (not available on all STM32 devices)

LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

ADC both groups regular and injected

LL_ADC_GROUP_NONE (0x00000000UL)

ADC group none

ADC instance - Sampling time common to a group of channels

group ADC_LL_EC_SAMPLINGTIME_COMMON

Defines

LL_ADC_SAMPLINGTIME_COMMON_1 (ADC4_SMPR_SMP1_Pos)

Sampling time common to a group of channels: sampling time nb 1

LL_ADC_SAMPLINGTIME_COMMON_2

(ADC4_SMPR_SMP2_Pos \

|

LL_ADC_ADC4_SAMPLING_TIME_CH_MASK )

Sampling time common to a group of channels: sampling time nb 2

ADC4_SAMPLING_TIME_SMP_MASK (ADC4_SMPR_SMP2 | ADC4_SMPR_SMP1)
ADC4_SAMPLING_TIME_SMP_SHIFT_MASK (ADC4_SMPR_SMP2_Pos | ADC4_SMPR_SMP1_Pos)

ADC group regular - Trigger frequency mode

group ADC_LL_EC_REG_TRIGGER_FREQ

Defines

LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL)

ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter “tIdle”.

LL_ADC_TRIGGER_FREQ_LOW (ADC4_CFGR2_LFTRIG)

ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter “tIdle”.

ADC instance - Channel number

group ADC_LL_EC_CHANNEL

Defines

LL_ADC_CHANNEL_0 ( LL_ADC_CHANNEL_0_NB | LL_ADC_CHANNEL_0_SMP

\

|

LL_ADC_CHANNEL_0_BITFIELD )

ADC channel to GPIO pin ADCx_IN0

LL_ADC_CHANNEL_1 ( LL_ADC_CHANNEL_1_NB | LL_ADC_CHANNEL_1_SMP

\

|

LL_ADC_CHANNEL_1_BITFIELD )

ADC channel to GPIO pin ADCx_IN1

LL_ADC_CHANNEL_2 ( LL_ADC_CHANNEL_2_NB | LL_ADC_CHANNEL_2_SMP

\

|

LL_ADC_CHANNEL_2_BITFIELD )

ADC channel to GPIO pin ADCx_IN2

LL_ADC_CHANNEL_3 ( LL_ADC_CHANNEL_3_NB | LL_ADC_CHANNEL_3_SMP

\

|

LL_ADC_CHANNEL_3_BITFIELD )

ADC channel to GPIO pin ADCx_IN3

LL_ADC_CHANNEL_4 ( LL_ADC_CHANNEL_4_NB | LL_ADC_CHANNEL_4_SMP

\

|

LL_ADC_CHANNEL_4_BITFIELD )

ADC channel to GPIO pin ADCx_IN4

LL_ADC_CHANNEL_5 ( LL_ADC_CHANNEL_5_NB | LL_ADC_CHANNEL_5_SMP

\

|

LL_ADC_CHANNEL_5_BITFIELD )

ADC channel to GPIO pin ADCx_IN5

LL_ADC_CHANNEL_6 ( LL_ADC_CHANNEL_6_NB | LL_ADC_CHANNEL_6_SMP

\

|

LL_ADC_CHANNEL_6_BITFIELD )

ADC channel to GPIO pin ADCx_IN6

LL_ADC_CHANNEL_7 ( LL_ADC_CHANNEL_7_NB | LL_ADC_CHANNEL_7_SMP

\

|

LL_ADC_CHANNEL_7_BITFIELD )

ADC channel to GPIO pin ADCx_IN7

LL_ADC_CHANNEL_8 ( LL_ADC_CHANNEL_8_NB | LL_ADC_CHANNEL_8_SMP

\

|

LL_ADC_CHANNEL_8_BITFIELD )

ADC channel to GPIO pin ADCx_IN8

LL_ADC_CHANNEL_9 ( LL_ADC_CHANNEL_9_NB | LL_ADC_CHANNEL_9_SMP

\

|

LL_ADC_CHANNEL_9_BITFIELD )

ADC channel to GPIO pin ADCx_IN9

LL_ADC_CHANNEL_10 ( LL_ADC_CHANNEL_10_NB | LL_ADC_CHANNEL_10_SMP

\

|

LL_ADC_CHANNEL_10_BITFIELD )

ADC channel to GPIO pin ADCx_IN10

LL_ADC_CHANNEL_11 ( LL_ADC_CHANNEL_11_NB | LL_ADC_CHANNEL_11_SMP

\

|

LL_ADC_CHANNEL_11_BITFIELD )

ADC channel to GPIO pin ADCx_IN11

LL_ADC_CHANNEL_12 ( LL_ADC_CHANNEL_12_NB | LL_ADC_CHANNEL_12_SMP

\

|

LL_ADC_CHANNEL_12_BITFIELD )

ADC channel to GPIO pin ADCx_IN12

LL_ADC_CHANNEL_13 ( LL_ADC_CHANNEL_13_NB | LL_ADC_CHANNEL_13_SMP

\

|

LL_ADC_CHANNEL_13_BITFIELD )

ADC channel to GPIO pin ADCx_IN13

LL_ADC_CHANNEL_14 ( LL_ADC_CHANNEL_14_NB | LL_ADC_CHANNEL_14_SMP

\

|

LL_ADC_CHANNEL_14_BITFIELD )

ADC channel to GPIO pin ADCx_IN14

LL_ADC_CHANNEL_15 ( LL_ADC_CHANNEL_15_NB | LL_ADC_CHANNEL_15_SMP

\

|

LL_ADC_CHANNEL_15_BITFIELD )

ADC channel to GPIO pin ADCx_IN15

LL_ADC_CHANNEL_16 ( LL_ADC_CHANNEL_16_NB | LL_ADC_CHANNEL_16_SMP

\

|

LL_ADC_CHANNEL_16_BITFIELD )

ADC channel to GPIO pin ADCx_IN16

LL_ADC_CHANNEL_17 ( LL_ADC_CHANNEL_17_NB | LL_ADC_CHANNEL_17_SMP

\

|

LL_ADC_CHANNEL_17_BITFIELD )

ADC channel to GPIO pin ADCx_IN17

LL_ADC_CHANNEL_18 ( LL_ADC_CHANNEL_18_NB | LL_ADC_CHANNEL_18_SMP

\

|

LL_ADC_CHANNEL_18_BITFIELD )

ADC channel to GPIO pin ADCx_IN18

LL_ADC_CHANNEL_19 ( LL_ADC_CHANNEL_19_NB | LL_ADC_CHANNEL_19_SMP

\

|

LL_ADC_CHANNEL_19_BITFIELD )

ADC channel to GPIO pin ADCx_IN19

LL_ADC_CHANNEL_20 ( LL_ADC_CHANNEL_20_NB | LL_ADC_CHANNEL_20_SMP

\

|

LL_ADC_CHANNEL_20_BITFIELD )

ADC channel to GPIO pin ADCx_IN20

LL_ADC_CHANNEL_21 ( LL_ADC_CHANNEL_21_NB | LL_ADC_CHANNEL_21_SMP

\

|

LL_ADC_CHANNEL_21_BITFIELD )

ADC channel to GPIO pin ADCx_IN21

LL_ADC_CHANNEL_22 ( LL_ADC_CHANNEL_22_NB | LL_ADC_CHANNEL_22_SMP

\

|

LL_ADC_CHANNEL_22_BITFIELD )

ADC channel to GPIO pin ADCx_IN22

LL_ADC_CHANNEL_23 ( LL_ADC_CHANNEL_23_NB | LL_ADC_CHANNEL_23_SMP

\

|

LL_ADC_CHANNEL_23_BITFIELD )

ADC channel to GPIO pin ADCx_IN23

LL_ADC_CHANNEL_VREFINT ( LL_ADC_CHANNEL_0 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to VrefInt: Internal voltage reference.

LL_ADC_CHANNEL_TEMPSENSOR ( LL_ADC_CHANNEL_19 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to Temperature sensor.

LL_ADC_CHANNEL_VBAT ( LL_ADC_CHANNEL_18 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda.

LL_ADC_CHANNEL_VDDCORE ( LL_ADC_CHANNEL_12 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to VddCore. On STM32U5, ADC channel available only on ADC instance: ADC4.

LL_ADC_CHANNEL_TEMPSENSOR_ADC4 ( LL_ADC_CHANNEL_13 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to Temperature sensor. On STM32U5, ADC channel available only on ADC instance: ADC4.

LL_ADC_CHANNEL_VBAT_ADC4 ( LL_ADC_CHANNEL_14 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32U5, ADC channel available only on ADC instance: ADC4.

LL_ADC_CHANNEL_DAC1CH1_ADC4 ( LL_ADC_CHANNEL_21 | LL_ADC_CHANNEL_ID_INTERNAL_CH )

ADC internal channel connected to DAC1 channel 1, channel specific to ADC4

LL_ADC_CHANNEL_DAC1CH2_ADC4 ( LL_ADC_CHANNEL_DAC1CH1_ADC4

\

|

LL_ADC_CHANNEL_DIFF_VREFINT_VDDCORE )

ADC internal channel connected to DAC1 channel 2, channel specific to ADC4

LL_ADC_CHANNEL_NONE ( LL_ADC_CHANNEL_NONE_NB | LL_ADC_CHANNEL_NONE_SMP

\

|

LL_ADC_CHANNEL_NONE_BITFIELD )

ADC no channel selected

LL_ADC_CHANNEL_ALL ( LL_ADC_CHANNEL_ALL_NB | LL_ADC_CHANNEL_ALL_SMP

\

|

LL_ADC_CHANNEL_ALL_BITFIELD )

ADC all channels selected

ADC group regular - Trigger source

group ADC_LL_EC_REG_TRIGGER_SOURCE

Note

Triggers from timers capture compare are input capture or output capture.

Defines

LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)

ADC group regular conversion trigger internal: SW start.

LL_ADC_REG_TRIG_EXT_TIM1_CH1 ( LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM1 channel 1 event (capture compare)

LL_ADC_REG_TRIG_EXT_TIM1_CH2

(ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM1 channel 2 event (capture compare)

LL_ADC_REG_TRIG_EXT_TIM1_CH3

(ADC_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM1 channel 3 event (capture compare)

LL_ADC_REG_TRIG_EXT_TIM2_CH2

(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM2 channel 2 event (capture compare)

LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM3 TRGO event

LL_ADC_REG_TRIG_EXT_TIM4_CH4

(ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion triggerfrom periph: TIM4 channel 4 event (capture compare)

LL_ADC_REG_TRIG_EXT_EXTI_LINE11

(ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion triggerfrom periph: external interrupt line 11 event

LL_ADC_REG_TRIG_EXT_TIM8_TRGO

(ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \

| ADC_CFGR1_EXTSEL_0 |

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM8 TRGO event

LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_3 | LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM8 TRGO2 event

LL_ADC_REG_TRIG_EXT_TIM1_TRGO

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversio triggerfrom periph: TIM1 TRGO event

LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion triggerfrom periph: TIM1 TRGO2 event

LL_ADC_REG_TRIG_EXT_TIM2_TRGO

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \

| ADC_CFGR1_EXTSEL_0|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM2 TRGO event

LL_ADC_REG_TRIG_EXT_TIM4_TRGO

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM4 TRGO event

LL_ADC_REG_TRIG_EXT_TIM6_TRGO

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM6 TRGO event

LL_ADC_REG_TRIG_EXT_TIM15_TRGO

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM15 TRGO event

LL_ADC_REG_TRIG_EXT_TIM3_CH4

(ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \

| ADC_CFGR1_EXTSEL_0 |

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: TIM3 channel 4 event (capture compare)

LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: external interrupt line 15 event

LL_ADC_REG_TRIG_EXT_LPTIM1_CH1

(ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: LPTIM1 channel 1 event

LL_ADC_REG_TRIG_EXT_LPTIM2_CH1

(ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: LPTIM2 channel 1 event

LL_ADC_REG_TRIG_EXT_LPTIM3_CH1

(ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: LPTIM3 channel 1 event

LL_ADC_REG_TRIG_EXT_LPTIM4_OUT

(ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from periph: LPTIM4 OUT event

LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4 ( LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: TIM1 TRGO

LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4

(ADC4_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare)

LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4

(ADC4_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: TIM2 TRGO

LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4

(ADC4_CFGR1_EXTSEL_1 | ADC4_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: TIM15 TRGO

LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4

(ADC4_CFGR1_EXTSEL_2 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: TIM6 TRGO

LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4

(ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_0 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: LPTIM1 CH1

LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4

(ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \

|

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: LPTIM3 CH2

LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4

(ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \

| ADC4_CFGR1_EXTSEL_0 |

LL_ADC_REG_TRIG_EXT_EDGE_DEFAULT )

ADC group regular conversion trigger from external IP: external interrupt line 15

ADC group regular - Trigger edge

group ADC_LL_EC_REG_TRIGGER_EDGE

Defines

LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0)

ADC group regular conversion trigger polarity set to rising edge

LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1)

ADC group regular conversion trigger polarity set to falling edge

LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0)

ADC group regular conversion trigger polarity set to both rising and falling edges

ADC group regular - Continuous mode

group ADC_LL_EC_REG_CONTINUOUS_MODE

Defines

LL_ADC_REG_CONV_SINGLE (0x00000000UL)

ADC conversions are performed in single mode: one conversion per trigger

LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

ADC group regular - Data transfer mode of ADC conversion data

group ADC_LL_EC_REG_DATA_TRANSFER_MODE

Defines

LL_ADC_REG_DR_TRANSFER (0x00000000UL)

ADC conversions are transferred to DR register

LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)

ADC conversion data are not transferred by DMA but to DR register

LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMNGT_0)

ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 | ADC_CFGR1_DMNGT_0)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred(number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

LL_ADC_REG_MDF_TRANSFER (ADC_CFGR1_DMNGT_1)

ADC conversion data are transferred to DFSDM

ADC group regular - DMA transfer of ADC conversion data

group ADC_LL_EC_REG_DMA_TRANSFER

Defines

LL_ADC_REG_DMA_TRANSFER_NONE_ADC4 (0x00000000UL)

ADC conversions are not transferred by DMA

LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4 (ADC4_CFGR1_DMAEN)

ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4 (ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

ADC group regular - Overrun behavior on conversion data

group ADC_LL_EC_REG_OVR_DATA_BEHAVIOR

Note

Overrun occurs when conversion is completed while conversion data in data register (from previous conversion) has not ben fetched (by CPU or DMA).

Defines

LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)

ADC group regular behavior in case of overrun: data preserved. Note: an internal FIFO of 8 elements in enabled in this mode. Overrun occurs when the FIFO overflows. FIFO is emptied by successive reads of data register.

LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD)

ADC group regular behavior in case of overrun: data overwritten

ADC group regular - Sequencer configuration flexibility

group ADC_LL_EC_REG_SEQ_MODE

Defines

LL_ADC_REG_SEQ_FIXED (0x00000000UL)

Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function LL_ADC_REG_SetSequencerChannels() .

LL_ADC_REG_SEQ_CONFIGURABLE (ADC4_CFGR1_CHSELRMOD)

Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength() .

ADC group regular - Sequencer scan length

group ADC_LL_EC_REG_SEQ_SCAN_LENGTH

Defines

LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1)

ADC group regular sequencer enable with 3 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2)

ADC group regular sequencer enable with 5 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2| ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1)

ADC group regular sequencer enable with 7 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

(ADC_SQR1_L_2 | ADC_SQR1_L_1 \

| ADC_SQR1_L_0)


ADC group regular sequencer enable with 8 ranks in the sequence

LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3)

ADC group regular sequencer enable with 9 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3| ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3| ADC_SQR1_L_1)

ADC group regular sequencer enable with 11 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

(ADC_SQR1_L_3| ADC_SQR1_L_1 \

| ADC_SQR1_L_0)


ADC group regular sequencer enable with 12 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)

ADC group regular sequencer enable with 13 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

(ADC_SQR1_L_3 | ADC_SQR1_L_2 \

| ADC_SQR1_L_0)


ADC group regular sequencer enable with 14 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

(ADC_SQR1_L_3 | ADC_SQR1_L_2 \

| ADC_SQR1_L_1)


ADC group regular sequencer enable with 15 ranks in the sequence (not available on ADC4)

LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

(ADC_SQR1_L_3 | ADC_SQR1_L_2 \

| ADC_SQR1_L_1 | ADC_SQR1_L_0)


ADC group regular sequencer enable with 16 ranks in the sequence (not available on ADC4)

ADC group regular - Sequencer discontinuous mode

group ADC_LL_EC_REG_SEQ_DISCONT_MODE

Defines

LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group regular sequencer discontinuous mode disabled

LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every rank

LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 3 ranks

LL_ADC_REG_SEQ_DISCONT_4RANKS

(ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \

| ADC_CFGR1_DISCEN)


ADC group regular sequencer discontinuous mode enabled with sequence interruption every 4 ranks

LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 5 ranks

LL_ADC_REG_SEQ_DISCONT_6RANKS

(ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 \

| ADC_CFGR1_DISCEN)


ADC group regular sequencer discontinuous mode enabled with sequence interruption every 6 ranks

LL_ADC_REG_SEQ_DISCONT_7RANKS

(ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \

| ADC_CFGR1_DISCEN)


ADC group regular sequencer discontinuous mode enabled with sequence interruption every 7 ranks

LL_ADC_REG_SEQ_DISCONT_8RANKS

(ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \

| ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN)


ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

ADC group regular - Sequencer scan direction

group ADC_LL_EC_REG_SEQ_SCAN_DIRECTION

Defines

LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL)

On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function LL_ADC_REG_SetSequencerConfigurable() . ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 series, this setting is not available and the default scan direction is forward.

LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC4_CFGR1_SCANDIR)

On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function LL_ADC_REG_SetSequencerConfigurable() . ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer)

ADC group regular - Sequencer ranks

group ADC_LL_EC_REG_SEQ_RANKS

Defines

LL_ADC_REG_RANK_1 ( LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ1_Pos)

ADC group regular sequencer rank 1

LL_ADC_REG_RANK_2 ( LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ2_Pos)

ADC group regular sequencer rank 2

LL_ADC_REG_RANK_3 ( LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ3_Pos)

ADC group regular sequencer rank 3

LL_ADC_REG_RANK_4 ( LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ4_Pos)

ADC group regular sequencer rank 4

LL_ADC_REG_RANK_5 ( LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ5_Pos)

ADC group regular sequencer rank 5

LL_ADC_REG_RANK_6 ( LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ6_Pos)

ADC group regular sequencer rank 6

LL_ADC_REG_RANK_7 ( LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ7_Pos)

ADC group regular sequencer rank 7

LL_ADC_REG_RANK_8 ( LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ8_Pos)

ADC group regular sequencer rank 8

LL_ADC_REG_RANK_9 ( LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ9_Pos)

ADC group regular sequencer rank 9 (not available on ADC4)

LL_ADC_REG_RANK_10 ( LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ10_Pos)

ADC group regular sequencer rank 10 (not available on ADC4)

LL_ADC_REG_RANK_11 ( LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ11_Pos)

ADC group regular sequencer rank 11 (not available on ADC4)

LL_ADC_REG_RANK_12 ( LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ12_Pos)

ADC group regular sequencer rank 12 (not available on ADC4)

LL_ADC_REG_RANK_13 ( LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ13_Pos)

ADC group regular sequencer rank 13 (not available on ADC4)

LL_ADC_REG_RANK_14 ( LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ14_Pos)

ADC group regular sequencer rank 14 (not available on ADC4)

LL_ADC_REG_RANK_15 ( LL_ADC_SQR4_REGOFFSET | ADC_SQR4_SQ15_Pos)

ADC group regular sequencer rank 15 (not available on ADC4)

LL_ADC_REG_RANK_16 ( LL_ADC_SQR4_REGOFFSET | ADC_SQR4_SQ16_Pos)

ADC group regular sequencer rank 16 (not available on ADC4)

ADC group injected - Trigger source

group ADC_LL_EC_INJ_TRIGGER_SOURCE

Note

Triggers from timers capture compare are input capture or output capture.

Defines

LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)

ADC group injected conversion trigger internal: SW start.

LL_ADC_INJ_TRIG_EXT_TIM1_TRGO ( LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM1 TRGO event

LL_ADC_INJ_TRIG_EXT_TIM1_CH4

(ADC_JSQR_JEXTSEL_0 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM1 channel 4 event (capture compare)

LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

(ADC_JSQR_JEXTSEL_1 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM2 TRGO event

LL_ADC_INJ_TRIG_EXT_TIM2_CH1

(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM2 channel 1 event (capture compare)

LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM3 channel 4 event (capture compare)

LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM4 TRGO event

LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: external interrupt line 15

LL_ADC_INJ_TRIG_EXT_TIM8_CH4

(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \

| ADC_JSQR_JEXTSEL_0 |

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT

ADC group injected conversion trigger from periph: TIM8 channel 4 event (capture compare)

LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

(ADC_JSQR_JEXTSEL_3 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM1 TRGO2 event

LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM8 TRGO event

LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM8 TRGO2 event

LL_ADC_INJ_TRIG_EXT_TIM3_CH3

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \

| ADC_JSQR_JEXTSEL_0 |

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT

ADC group injected conversion trigger from periph: TIM3 channel 3 event (capture compare)

LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM3 TRGO event

LL_ADC_INJ_TRIG_EXT_TIM3_CH1

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \

| ADC_JSQR_JEXTSEL_0 |

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT

ADC group injected conversion trigger from periph: TIM3 channel 1 event (capture compare)

LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \

| ADC_JSQR_JEXTSEL_1 |

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT

ADC group injected conversion trigger from periph: TIM6 TRGO event

LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \

| ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: TIM15 TRGO event

LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2

(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: LPTIM1 OUT event

LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2

(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \

| ADC_JSQR_JEXTSEL_0 |

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT

ADC group injected conversion trigger from periph: LPTIM2 OUT event

LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1

(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \

|

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT )

ADC group injected conversion trigger from periph: LPTIM3 OUT event. 4 event (capture compare)

LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT

(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \

| ADC_JSQR_JEXTSEL_0 |

LL_ADC_INJ_TRIG_EXT_EDGE_DEFAULT

ADC group injected conversion trigger from periph: LPTIM3 OUT event. 4 event (capture compare)

ADC group injected - Trigger edge

group ADC_LL_EC_INJ_TRIGGER_EDGE

Defines

LL_ADC_INJ_TRIG_EXT_RISING (ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to rising edge

LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1)

ADC group injected conversion trigger polarity set to falling edge

LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to both rising and falling edges

ADC group injected - Automatic trigger mode

group ADC_LL_EC_INJ_TRIG_AUTO

Defines

LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

LL_ADC_INJ_TRIG_FROM_REGULAR (ADC_CFGR1_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

ADC group regular - Sampling mode

group ADC_LL_EC_REG_SAMPLING_MODE

Defines

LL_ADC_SAMPLING_MODE_NORMAL (0x00000000UL)

ADC conversions sampling phase duration is defined using Channel - Sampling time .

LL_ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB)

ADC conversions sampling phase starts immediately after end of conversion, stops upon trigger event. Note: first conversion is using minimal sampling time (see Channel - Sampling time ). Note: Usable only if conversions from ADC group regular (not ADC group injected) and not in continuous mode.

LL_ADC_SAMPLING_MODE_TRIGGER_CTRL (ADC_CFGR2_SMPTRIG)

ADC conversions sampling phase is controlled by trigger events: trigger rising edge starts sampling, trigger falling edge stops sampling and start conversion. Note: Usable only if conversions from ADC group regular (not ADC group injected) and not in continuous mode.

ADC group injected - Sequencer scan length

group ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

Defines

LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS (ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1)

ADC group injected sequencer enable with 3 ranks in the sequence

LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

ADC group injected - Sequencer discontinuous mode

group ADC_LL_EC_INJ_SEQ_DISCONT_MODE

Defines

LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group injected sequencer discontinuous mode disabled

LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN)

ADC group injected sequencer discontinuous mode enabled with sequence interruption every rank

ADC group injected - Sequencer ranks

group ADC_LL_EC_INJ_SEQ_RANKS

Defines

LL_ADC_INJ_RANK_1 ( LL_ADC_JDR1_REGOFFSET | ADC_JSQR_JSQ1_Pos)

ADC group injected sequencer rank 1

LL_ADC_INJ_RANK_2 ( LL_ADC_JDR2_REGOFFSET | ADC_JSQR_JSQ2_Pos)

ADC group injected sequencer rank 2

LL_ADC_INJ_RANK_3 ( LL_ADC_JDR3_REGOFFSET | ADC_JSQR_JSQ3_Pos)

ADC group injected sequencer rank 3

LL_ADC_INJ_RANK_4 ( LL_ADC_JDR4_REGOFFSET | ADC_JSQR_JSQ4_Pos)

ADC group injected sequencer rank 4

Channel - Sampling time

group ADC_LL_EC_CHANNEL_SAMPLINGTIME

Defines

LL_ADC_SAMPLINGTIME_5CYCLES (0x00000000UL)

Sampling time 5 ADC clock cycles

LL_ADC_SAMPLINGTIME_6CYCLES (ADC_SMPR2_SMP10_0)

Sampling time 6 ADC clock cycles

LL_ADC_SAMPLINGTIME_12CYCLES (ADC_SMPR2_SMP10_1)

Sampling time 12 ADC clock cycles

LL_ADC_SAMPLINGTIME_20CYCLES (ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 20 ADC clock cycles

LL_ADC_SAMPLINGTIME_36CYCLES (ADC_SMPR2_SMP10_2)

Sampling time 36 ADC clock cycles

LL_ADC_SAMPLINGTIME_68CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)

Sampling time 68 ADC clock cycles

LL_ADC_SAMPLINGTIME_391CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)

Sampling time 391 ADC clock cycles

LL_ADC_SAMPLINGTIME_814CYCLES

(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 \

| ADC_SMPR2_SMP10_0)


Sampling time 814 ADC clock cycles

LL_ADC4_SAMPLINGTIME_1CYCLE_5 (0x00000000UL)

Sampling time 1.5 ADC clock cycle

LL_ADC4_SAMPLINGTIME_3CYCLES_5 (ADC4_SMPR_SMP1_0)

Sampling time 3.5 ADC clock cycles

LL_ADC4_SAMPLINGTIME_7CYCLES_5 (ADC4_SMPR_SMP1_1)

Sampling time 7.5 ADC clock cycles

LL_ADC4_SAMPLINGTIME_12CYCLES_5 (ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0)

Sampling time 12.5 ADC clock cycles

LL_ADC4_SAMPLINGTIME_19CYCLES_5 (ADC4_SMPR_SMP1_2)

Sampling time 19.5 ADC clock cycles

LL_ADC4_SAMPLINGTIME_39CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_0)

Sampling time 39.5 ADC clock cycles

LL_ADC4_SAMPLINGTIME_79CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1)

Sampling time 79.5 ADC clock cycles

LL_ADC4_SAMPLINGTIME_814CYCLES_5

(ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 \

| ADC4_SMPR_SMP1_0)


Sampling time 814.5 ADC clock cycles

Channel - Input mode (single ended, differential)

group ADC_LL_EC_CHANNEL_IN_SINGLE_DIFF

Defines

LL_ADC_IN_SINGLE_ENDED (0x0000FFFFUL)

ADC channel input set to single ended (literal also used to set calibration mode)

LL_ADC_IN_DIFFERENTIAL (0xFFFF0000UL)

ADC channel input set to differential (literal also used to set calibration mode)

LL_ADC_IN_SINGLE_DIFF ( LL_ADC_IN_SINGLE_ENDED

\

|

LL_ADC_IN_DIFFERENTIAL )

ADC channel input set to both single ended and differential (literal used only to set calibration factors)

Channel - Input mode legacy definitions

group ADC_LL_EC_CHANNEL_IN_SINGLE_DIFF_LEGACY

Defines

LL_ADC_SINGLE_ENDED LL_ADC_IN_SINGLE_ENDED
LL_ADC_DIFFERENTIAL_ENDED LL_ADC_IN_DIFFERENTIAL
LL_ADC_BOTH_SINGLE_DIFF_ENDED LL_ADC_IN_SINGLE_DIFF

Analog watchdog - Analog watchdog number

group ADC_LL_EC_AWD_NB

Defines

LL_ADC_AWD_1 ( LL_ADC_AWD_CR1_CHANNEL_MASK | LL_ADC_AWD_CR1_REGOFFSET )

ADC analog watchdog instance 1

LL_ADC_AWD_2 ( LL_ADC_AWD_CR23_CHANNEL_MASK | LL_ADC_AWD_CR2_REGOFFSET )

ADC analog watchdog instance 2

LL_ADC_AWD_3 ( LL_ADC_AWD_CR23_CHANNEL_MASK | LL_ADC_AWD_CR3_REGOFFSET )

ADC analog watchdog instance 3

Analog watchdog - Thresholds

group ADC_LL_EC_AWD_THRESHOLDS

Defines

LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)

ADC analog watchdog threshold high

LL_ADC_AWD_THRESHOLD_LOW (0x0UL)

ADC analog watchdog threshold low

Analog watchdog - Filtering config

group ADC_LL_EC_AWD_FILTERING_CONFIG

Defines

LL_ADC_AWD_FILTERING_NONE (0x00000000UL)

ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_2SAMPLES (ADC_HTR_AWDFILT_0)

ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_3SAMPLES (ADC_HTR_AWDFILT_1)

ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_4SAMPLES (ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)

ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2)

ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)

ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)

ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt

LL_ADC_AWD_FILTERING_8SAMPLES

(ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 \

| ADC_HTR_AWDFILT_0)


ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt

Oversampling - Oversampling instance

group ADC_LL_EC_OVS_INSTANCE

Defines

LL_ADC_OVS_1 (0U)

ADC oversampling instance for standard oversampling: a single oversampling accumulator is common to regular and injected conversions. Therefore, settings ratio and shift are common and process is sequential. For constraints of oversampling on groups regular and injected, refer to parameters of ADC_LL_EC_OVS_SCOPE.

Oversampling - Oversampling scope

group ADC_LL_EC_OVS_SCOPE

Defines

LL_ADC_OVS_DISABLE (0x00000000UL)

ADC oversampling disabled.

LL_ADC_OVS_REG_CONTINUED (ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If ADC group injected conversion insertion within regular sequence: oversampling on group regular is temporary stopped and, after injected conversion, continued (oversampling accumulator maintained).

LL_ADC_OVS_REG_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If ADC group injected conversion insertion within regular sequence: after injected conversion, oversampling on group regular is resumed from start (oversampler accumulator reset).

LL_ADC_OVS_INJ (ADC_CFGR2_JOVSE)

ADC oversampling on conversions of ADC group injected, in sequential mode: oversampling conversions sequence sequential, switching data registers after each oversampling process (all ratio occurrences, shift). Note: A single oversampling accumulator is common to regular and injected conversions. Therefore, settings ratio and shift are common and process is sequential.

LL_ADC_OVS_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC groups regular and injected. Combination of LL_ADC_OVS_REG_RESUMED and LL_ADC_OVS_INJ: refer to description of these parameters. Note: Can be used only with function LL_ADC_SetOverSamplingScope() . For configuration with accumulator explicit selection, refer to LL_ADC_SetOverSamplingInstScope() , used with combination of regular and injected related parameters.

Oversampling - Discontinuous mode (triggered mode)

group ADC_LL_EC_OVS_DISCONT_MODE

Defines

LL_ADC_OVS_CONT (0x00000000UL)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio start from 1 trigger)

LL_ADC_OVS_DISCONT (ADC_CFGR2_TROVS)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) On this STM32 series, discontinuous mode is supported on oversampling on group regular and injected.

Oversampling - Oversampling legacy definitions

group ADC_LL_EC_OVS_SCOPE_LEGACY

Defines

LL_ADC_OVS_GRP_REGULAR_CONTINUED LL_ADC_OVS_REG_CONTINUED
LL_ADC_OVS_GRP_REGULAR_RESUMED LL_ADC_OVS_REG_RESUMED
LL_ADC_OVS_GRP_INJECTED LL_ADC_OVS_INJ
LL_ADC_OVS_GRP_INJ_REG_RESUMED LL_ADC_OVS_INJ_REG_RESUMED
LL_ADC_OVS_REG_CONT LL_ADC_OVS_CONT
LL_ADC_OVS_REG_DISCONT LL_ADC_OVS_DISCONT

Oversampling - Ratio

group ADC_LL_EC_OVS_RATIO

Defines

LL_ADC_OVS_RATIO_2 ( LL_ADC_ADC4_OVS_RATIO_PARAM | 0x00000000UL)

ADC oversampling ratio of 2: sum of 2 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_4 ( LL_ADC_ADC4_OVS_RATIO_PARAM | ADC4_CFGR2_OVSR_0)

ADC oversampling ratio of 4: sum of 4 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_8 ( LL_ADC_ADC4_OVS_RATIO_PARAM | ADC4_CFGR2_OVSR_1)

ADC oversampling ratio of 8: sum of 8 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_16 ( LL_ADC_ADC4_OVS_RATIO_PARAM

| ADC4_CFGR2_OVSR_1 \

| ADC4_CFGR2_OVSR_0)


ADC oversampling ratio of 16: sum of 16 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_32 ( LL_ADC_ADC4_OVS_RATIO_PARAM | ADC4_CFGR2_OVSR_2)

ADC oversampling ratio of 32: sum of 32 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_64 ( LL_ADC_ADC4_OVS_RATIO_PARAM

| ADC4_CFGR2_OVSR_2 \

| ADC4_CFGR2_OVSR_0)


ADC oversampling ratio of 64: sum of 64 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_128 ( LL_ADC_ADC4_OVS_RATIO_PARAM

| ADC4_CFGR2_OVSR_2 \

| ADC4_CFGR2_OVSR_1)


ADC oversampling ratio of 128: sum of 128 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

LL_ADC_OVS_RATIO_256 ( LL_ADC_ADC4_OVS_RATIO_PARAM

| ADC4_CFGR2_OVSR_2 \

| ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0)


ADC oversampling ratio of 256: sum of 256 conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Oversampling - Data shift

group ADC_LL_EC_OVS_SHIFT

Defines

LL_ADC_OVS_SHIFT_NONE (0x00000000UL)

ADC oversampling no shift (no division)

LL_ADC_OVS_SHIFT_RIGHT_1

((ADC_CFGR2_OVSS_0)\

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 1 (division by 2)

LL_ADC_OVS_SHIFT_RIGHT_2

((ADC_CFGR2_OVSS_1)\

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 2 (division by 4)

LL_ADC_OVS_SHIFT_RIGHT_3

((ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 3 (division by 8)

LL_ADC_OVS_SHIFT_RIGHT_4

((ADC_CFGR2_OVSS_2)\

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 4 (division by 16)

LL_ADC_OVS_SHIFT_RIGHT_5

((ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 5 (division by 32)

LL_ADC_OVS_SHIFT_RIGHT_6

((ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 6 (division by 64)

LL_ADC_OVS_SHIFT_RIGHT_7

((ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 7 (division by 128)

LL_ADC_OVS_SHIFT_RIGHT_8

((ADC_CFGR2_OVSS_3)\

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 8 (division by 256)

LL_ADC_OVS_SHIFT_RIGHT_9

((ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 9 (division by 512). Specific to ADC instance: ADC1, ADC2.

LL_ADC_OVS_SHIFT_RIGHT_10

((ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 10 (division by 1024). Specific to ADC instance: ADC1, ADC2.

LL_ADC_OVS_SHIFT_RIGHT_11

((ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) \

>> ADC_CFGR2_OVSS_Pos)


ADC oversampling shift of 11 (division by 2048). Specific to ADC instance: ADC1, ADC2.

Multimode - Mode

group ADC_LL_EC_MULTI_MODE

Defines

LL_ADC_MULTI_INDEPENDENT (0x00000000UL)

ADC dual mode disabled (ADC independent mode)

LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)

ADC dual mode enabled: group regular simultaneous

LL_ADC_MULTI_DUAL_REG_INTERL

(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \

| ADC_CCR_DUAL_0)


ADC dual mode enabled: Combined group regular interleaved

LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected simultaneous

LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not SW start)

LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1)

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous

Multimode - Data format

group ADC_LL_EC_MULTI_DMA_TRANSFER

Defines

LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)

ADC multimode group regular data format: full range, no data packing. Intended for cases:

  • multimode without DMA transfer

  • multimode with DMA transfer in two different buffers.

  • high data width (can exceed ADC resolution in case of oversampling or post-processing) over data packing constraints. For no data transfer:

  • to retrieve conversion data, use LL_ADC_REG_ReadConversionData32() with each ADC instance. For data transfer by DMA:

  • configure DMA to get data from register DR of ADC instance with LL_ADC_DMA_GetRegAddr() . Each ADC uses its own DMA channel, with its individual DMA transfer settings. Therefore, two destination buffers.

LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1)

ADC multimode group regular data format: full range and 2 data packing on 32 bits. Intended for cases:

  • multimode with DMA transfer in a single buffer.

  • high data width (can exceed ADC resolution in case of oversampling or post-processing) over data packing constraints. For no data transfer:

  • to retrieve conversion data, use LL_ADC_REG_ReadMultiConversionData32() or LL_ADC_REG_ReadConversionData32() with each ADC instance. For data transfer by DMA:

  • configure DMA to get data from register CDR or CDR2 with LL_ADC_DMA_GetRegAddr() . Note: conversion data in two ADC common instance data registers (CDR, CDR2) with packing option on 32 bits.

    • Register CDR: data packing on 32 bits: ADC master and slave data are concatenated (data master in [15; 0], data slave in [31; 16]), therefore data width must be lower than 16 bits (can exceed ADC resolution with post-processing: oversampling, offset, …).

    • Register CDR2: data of master and slave are alternatively set in full register width 32 bits, therefore no constraint on data width. In case of usage with DMA, CDR generates one transfer request and CDR2 two transfer requests per conversion.

LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0)

ADC multimode group regular data format: full range and 2 data packing on 16 bits. Intended for cases:

  • multimode with DMA transfer in a single buffer with elements 16 bits. For no data transfer:

  • to retrieve conversion data, use LL_ADC_REG_ReadConversionData32() with each ADC instance. For data transfer by DMA:

  • configure DMA to get data from register CDR or CDR2 with LL_ADC_DMA_GetRegAddr() . Note: conversion data in two ADC common instance data registers (CDR, CDR2) with packing option on 16 bits.

    • Register CDR: data packing on 16 bits: ADC master and slave data are concatenated (data master in [7; 0], data slave in [15; 8]), therefore data width must be lower than 8 bits (can exceed ADC resolution with post-processing: oversampling, offset, …).

    • Register CDR2: data of master and slave are alternatively set in full register width 32 bits, therefore no constraint on data width. In case of usage with DMA, CDR generates one transfer request and CDR2 two transfer requests per conversion.

Multimode - Delay between two sampling phases (for mode interleaved)

group ADC_LL_EC_MULTI_TWOSMP_DELAY

Defines

LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL)

ADC multimode delay between two sampling phases: 1 ADC clock cycle for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 2 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1)

ADC multimode delay between two sampling phases: 3 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 4 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2)

ADC multimode delay between two sampling phases: 5 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 6 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)

ADC multimode delay between two sampling phases: 7 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES

(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \

| ADC_CCR_DELAY_0)


ADC multimode delay between two sampling phases: 8 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3)

ADC multimode delay between two sampling phases: 9 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 10 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)

ADC multimode delay between two sampling phases: 11 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES

(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \

| ADC_CCR_DELAY_0)


ADC multimode delay between two sampling phases: 12 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)

ADC multimode delay between two sampling phases: 13 ADC clock cycles for all resolutions

LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES

(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 \

| ADC_CCR_DELAY_0)


ADC multimode delay between two sampling phases: 14 ADC clock cycles for resolutions 14, 12, 10 bit

LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES

(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 \

| ADC_CCR_DELAY_1)


ADC multimode delay between two sampling phases: 15 ADC clock cycles for resolutions 14, 12, 10 bit

LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES

(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \

| ADC_CCR_DELAY_0)


ADC multimode delay between two sampling phases: 16 ADC clock cycles for resolutions 14, 12 bit

LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS

(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \

| ADC_CCR_DELAY_0)


ADC multimode delay between two sampling phases: 13 ADC clock cycles for resolution 8 bit

LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS

(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \

| ADC_CCR_DELAY_0)


ADC multimode delay between two sampling phases: 15 ADC clock cycles for resolution 10 bit

Multimode - ADC master or slave

group ADC_LL_EC_MULTI_MASTER_SLAVE

Defines

LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: ADC master

LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV)

In multimode, selection among several ADC instances: ADC slave

LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: both ADC master and ADC slave

  • Legacy definitions

group ADC_LL_EC_LEGACY

Defines

LL_ADC_AWD1 LL_ADC_AWD_1
LL_ADC_AWD2 LL_ADC_AWD_2
LL_ADC_AWD3 LL_ADC_AWD_3
LL_ADC_INJ_TRIG_FROM_GRP_REGULAR LL_ADC_INJ_TRIG_FROM_REGULAR

Definitions of ADC hardware constraints delays

group ADC_LL_EC_HW_DELAYS

Note

Only ADC peripheral HW delays are defined in ADC LL driver driver, not timeout values.

Note

Timeout values for ADC operations are dependent to device clock configuration (system clock versus ADC clock), and therefore must be defined in user application. Indications for estimation of ADC timeout delays, for this STM32 series:

  • ADC calibration time: maximum delay is 16384/fADC (refer to device datasheet, parameter “tCAL”)

  • ADC enable time: maximum delay is 1 conversion cycle (refer to device datasheet, parameter “tSTAB”)

  • ADC disable time: maximum delay is few ADC clock cycles

  • ADC stop conversion time: maximum delay is few ADC clock cycles

  • ADC conversion time: duration depending on ADC clock and ADC configuration (refer to device reference manual, section “Timing”)

Defines

LL_ADC_DELAY_INTERNAL_REGUL_STAB_US (25UL)

Delay for ADC stabilization time (ADC voltage regulator start-up time), highest value corresponding to ADC4. Delay set to maximum value (refer to device datasheet, parameter “tADCVREG_STUP”). Unit: us

LL_ADC_DELAY_VREFINT_STAB_US (6UL)

Delay for internal voltage reference stabilization time. Delay set to maximum value (refer to device datasheet, parameter “tstart_vrefint”). Unit: us

LL_ADC_DELAY_TEMPSENSOR_STAB_US (10UL)

Delay for temperature sensor stabilization time. Literal set to maximum value (refer to device datasheet, parameter “tSTART”). Unit: us

LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (4UL)

Delay required between ADC end of calibration and ADC enable. Note: On this STM32 series, a minimum number of ADC clock cycles are required between ADC end of calibration and ADC enable. Wait time can be computed in user application by waiting for the equivalent number of CPU cycles, by taking into account ratio of CPU clock versus ADC clock prescalers. Unit: ADC clock cycles.