DBGMCU Exported Constants

DBGMCU Device ID definition

group DBGMCU_DEV_ID

Defines

LL_DBGMCU_DEV_ID_U5F5_U5G5 0x0476U

STM32U5 series device STM32U5Fx/5Gx

LL_DBGMCU_DEV_ID_U595_U5A5 0x0481U

STM32U5 series device STM32U59x/5Ax

LL_DBGMCU_DEV_ID_U575_U585 0x0482U

STM32U5 series device STM32U575/585

LL_DBGMCU_DEV_ID_U535_U545 0x0455U

STM32U5 series device STM32U535/545

DBGMCU Device revision ID definition

group DBGMCU_REV_ID

Defines

LL_DBGMCU_REV_ID_A 0x1000U

STM32U5 device revision A

LL_DBGMCU_REV_ID_B 0x2000U

STM32U5 device revision B

LL_DBGMCU_REV_ID_C 0x3000U

STM32U5 device revision C

LL_DBGMCU_REV_ID_X 0x2001U

STM32U5 device revision X (for devices: STM32U575/585)

LL_DBGMCU_REV_ID_Y 0x1003U

STM32U5 device revision Y (for devices: STM32U575/585)

LL_DBGMCU_REV_ID_Z 0x1001U

STM32U5 device revision Z (for devices: STM32U575/585)

DBGMCU Debug low power mode

group DBGMCU_DEBUG_LOW_POWER_MODE

Defines

LL_DBGMCU_STOP_MODE_DEBUG DBGMCU_CR_DBG_STOP

Debug during Stop0/1/2 mode

LL_DBGMCU_STANDBY_MODE_DEBUG DBGMCU_CR_DBG_STANDBY

Debug during Standby mode

LL_DBGMCU_LP_MODE_DEBUG_ALL (DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY)

Debug during Low power mode (Stop0/1/2 and Standby modes)

DBGMCU APB1 GRP1 STOP IP

group SYSTEM_LL_EC_APB1_GRP1_STOP_IP

Defines

LL_DBGMCU_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP

The counter clock of TIM2 is stopped when the core is halted

LL_DBGMCU_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP

The counter clock of TIM3 is stopped when the core is halted

LL_DBGMCU_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP

The counter clock of TIM4 is stopped when the core is halted

LL_DBGMCU_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP

The counter clock of TIM5 is stopped when the core is halted

LL_DBGMCU_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP

The counter clock of TIM6 is stopped when the core is halted

LL_DBGMCU_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP

The counter clock of TIM7 is stopped when the core is halted

LL_DBGMCU_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP

The window watchdog counter clock is stopped when the core is halted

LL_DBGMCU_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP

The independent watchdog counter clock is stopped when the core is halted

LL_DBGMCU_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP

The I2C1 SMBus timeout is frozen

LL_DBGMCU_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP

The I2C2 SMBus timeout is frozen

DBGMCU APB1 GRP2 STOP IP

group SYSTEM_LL_EC_APB1_GRP2_STOP_IP

Defines

LL_DBGMCU_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP

The I2C4 SMBus timeout is frozen

LL_DBGMCU_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP

The counter clock of LPTIM2 is stopped when the core is halted

LL_DBGMCU_I2C5_STOP DBGMCU_APB1FZR2_DBG_I2C5_STOP

The I2C5 SMBus timeout is frozen

LL_DBGMCU_I2C6_STOP DBGMCU_APB1FZR2_DBG_I2C6_STOP

The I2C6 SMBus timeout is frozen

DBGMCU APB2 GRP1 STOP IP

group SYSTEM_LL_EC_APB2_GRP1_STOP_IP

Defines

LL_DBGMCU_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP

The counter clock of TIM1 is stopped when the core is halted

LL_DBGMCU_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP

The counter clock of TIM8 is stopped when the core is halted

LL_DBGMCU_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP

The counter clock of TIM15 is stopped when the core is halted

LL_DBGMCU_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP

The counter clock of TIM16 is stopped when the core is halted

LL_DBGMCU_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP

The counter clock of TIM17 is stopped when the core is halted

DBGMCU APB3 GRP1 STOP IP

group SYSTEM_LL_EC_APB3_GRP1_STOP_IP

Defines

LL_DBGMCU_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP

The counter clock of I2C3 is stopped when the core is halted

LL_DBGMCU_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP

The counter clock of LPTIM1 is stopped when the core is halted

LL_DBGMCU_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP

The counter clock of LPTIM3 is stopped when the core is halted

LL_DBGMCU_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP

The counter clock of LPTIM4 is stopped when the core is halted

LL_DBGMCU_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP

The counter clock of RTC is stopped when the core is halted

DBGMCU AHB1 GRP1 STOP IP

group SYSTEM_LL_EC_AHB1_GRP1_STOP_IP

Defines

LL_DBGMCU_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP

The counter clock of GPDMA1 channel 0 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP

The counter clock of GPDMA1 channel 1 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP

The counter clock of GPDMA1 channel 2 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP

The counter clock of GPDMA1 channel 3 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP

The counter clock of GPDMA1 channel 4 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP

The counter clock of GPDMA1 channel 5 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP

The counter clock of GPDMA1 channel 6 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP

The counter clock of GPDMA1 channel 7 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP

The counter clock of GPDMA1 channel 8 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP

The counter clock of GPDMA1 channel 9 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP

The counter clock of GPDMA1 channel 10 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP

The counter clock of GPDMA1 channel 11 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP

The counter clock of GPDMA1 channel 12 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP

The counter clock of GPDMA1 channel 13 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP

The counter clock of GPDMA1 channel 14 is stopped when the core is halted

LL_DBGMCU_GPDMA1_CH15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP

The counter clock of GPDMA1 channel 15 is stopped when the core is halted

DBGMCU AHB3 GRP1 STOP IP

group SYSTEM_LL_EC_AHB3_GRP1_STOP_IP

Defines

LL_DBGMCU_LPDMA1_CH0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP

The counter clock of LPDMA1 channel 0 is stopped when the core is halted

LL_DBGMCU_LPDMA1_CH1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP

The counter clock of LPDMA1 channel 1 is stopped when the core is halted

LL_DBGMCU_LPDMA1_CH2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP

The counter clock of LPDMA1 channel 2 is stopped when the core is halted

LL_DBGMCU_LPDMA1_CH3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP

The counter clock of LPDMA1 channel 3 is stopped when the core is halted