Reference Manual to LL API cross reference

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for FLASH registers

Register

Bit

Function

ACR

LATENCY

ACR

LPM

ACR

PRFTEN

ACR

SLEEP_PD

ECCR

ADDR_ECC

ECCR

BK_ECC

ECCR

ECCC

ECCR

ECCD

ECCR

ECCIE

ECCR

SYSF_ECC

NSBOOTADD0R

NSBOOTADD0

NSBOOTADD1R

NSBOOTADD1

NSCR

BWR

NSCR

EOPIE

NSCR

ERRIE

NSCR

LOCK

NSCR

OBL_LAUNCH

NSCR

OPTLOCK

NSCR

OPTSTRT

NSCR

PER

NSCR

PG

NSCR

STRT

NSKEYR

NSKEY

NSSR

BSY

NSSR

EOP

NSSR

OEM1LOCK

NSSR

OEM2LOCK

NSSR

OPERR

NSSR

OPTWERR

NSSR

PD

NSSR

PD1

NSSR

PD2

NSSR

PGAERR

NSSR

PGSERR

NSSR

PROGERR

NSSR

SIZERR

NSSR

WDW

NSSR

WRPERR

OEM1KEYR1

OEM1KEY

OEM1KEYR2

OEM1KEY

OEM2KEYR1

OEM2KEY

OEM2KEYR2

OEM2KEY

OPSR

ADDR_OP

OPSR

BK_OP

OPSR

CODE_OP

OPSR

SYSF_OP

OPTKEYR

OPTKEY

OPTR

BKPRAM_ECC

OPTR

BOOT0

OPTR

BOR_LEV

OPTR

DUALBANK

OPTR

IO_VDDIO2_HSLV

OPTR

IO_VDD_HSLV

OPTR

IWDG_STDBY

OPTR

IWDG_STOP

OPTR

IWDG_SW

OPTR

NBOOT0

OPTR

NRST_SHDW

OPTR

NRST_STDBY

LL_FLASH_OB_DisableNRSTStopMode()

OPTR

NRST_STOP

LL_FLASH_OB_DisableNRSTStopMode()

OPTR

PA15_PUPEN

OPTR

RDP

OPTR

SRAM2_ECC

OPTR

SRAM2_RST

OPTR

SRAM3_ECC

OPTR

SRAM_RST

OPTR

SWAP_BANK

OPTR

TZEN

OPTR

WWDG_SW

OPTR

nSWBOOT0

PRIVCFGR

NSPRIV

PRIVCFGR

SPRIV

SECBOOTADD0R

BOOT_LOCK

SECBOOTADD0R

SECBOOTADD0

SECCR

INV

WRP1AR

WRP1A_PEND

WRP1AR

WRP1A_PSTRT

WRP1AR

WRP1A_PSTRT/WRP1A_PEND

WRP1BR

WRP1B_PEND

WRP1BR

WRP1B_PSTRT

WRP1BR

WRP1B_PSTRT/WRP1B_PEND

WRP2AR

WRP2A_PEND

WRP2AR

WRP2A_PSTRT

WRP2AR

WRP2A_PSTRT/WRP2A_PEND

WRP2BR

WRP2B_PEND

WRP2BR

WRP2B_PSTRT

WRP2BR

WRP2B_PSTRT/WRP2B_PEND