LL LPUART Constants

Clear Flags Defines

group LPUART_LL_EC_CLEAR_FLAG

Flags defines which can be used with LL_LPUART_WRITE_REG function.

Defines

LL_LPUART_ICR_PECF USART_ICR_PECF

Parity error clear flag

LL_LPUART_ICR_FECF USART_ICR_FECF

Framing error clear flag

LL_LPUART_ICR_NCF USART_ICR_NECF

Noise error detected clear flag

LL_LPUART_ICR_ORECF USART_ICR_ORECF

Overrun error clear flag

LL_LPUART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected clear flag

LL_LPUART_ICR_TCCF USART_ICR_TCCF

Transmission complete clear flag

LL_LPUART_ICR_CTSCF USART_ICR_CTSCF

CTS clear flag

LL_LPUART_ICR_CMCF USART_ICR_CMCF

Character match clear flag

LL_LPUART_ICR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Get Flags Defines

group LPUART_LL_EC_GET_FLAG

Flags defines which can be used with LL_LPUART_READ_REG function.

Defines

LL_LPUART_ISR_PE USART_ISR_PE

Parity error flag

LL_LPUART_ISR_FE USART_ISR_FE

Framing error flag

LL_LPUART_ISR_NE USART_ISR_NE

Noise detected flag

LL_LPUART_ISR_ORE USART_ISR_ORE

Overrun error flag

LL_LPUART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

LL_LPUART_ISR_TC USART_ISR_TC

Transmission complete flag

LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO not full flag

LL_LPUART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

LL_LPUART_ISR_CTS USART_ISR_CTS

CTS flag

LL_LPUART_ISR_BUSY USART_ISR_BUSY

Busy flag

LL_LPUART_ISR_CMF USART_ISR_CMF

Character match flag

LL_LPUART_ISR_SBKF USART_ISR_SBKF

Send break flag

LL_LPUART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

LL_LPUART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

LL_LPUART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

LL_LPUART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

LL_LPUART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

LL_LPUART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

LL_LPUART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

IT Defines

group LPUART_LL_EC_IT

IT defines which can be used with LL_LPUART_READ_REG and LL_LPUART_WRITE_REG functions.

Defines

LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

LL_LPUART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

LL_LPUART_CR1_PEIE USART_CR1_PEIE

Parity error

LL_LPUART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

LL_LPUART_CR3_EIE USART_CR3_EIE

Error interrupt enable

LL_LPUART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

FIFO Threshold

group LPUART_LL_EC_FIFOTHRESHOLD

Defines

LL_LPUART_FIFO_THRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

LL_LPUART_FIFO_THRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

LL_LPUART_FIFO_THRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

LL_LPUART_FIFO_THRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

LL_LPUART_FIFO_THRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

LL_LPUART_FIFO_THRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Direction

group LPUART_LL_EC_DIRECTION

Defines

LL_LPUART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

LL_LPUART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

LL_LPUART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Parity Control

group LPUART_LL_EC_PARITY

Defines

LL_LPUART_PARITY_NONE 0x00000000U

Parity control disabled

LL_LPUART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Wakeup

group LPUART_LL_EC_WAKEUP

Defines

LL_LPUART_WAKEUP_IDLELINE 0x00000000U

LPUART wake up from Mute mode on Idle Line

LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

LPUART wake up from Mute mode on Address Mark

Datawidth

group LPUART_LL_EC_DATAWIDTH

Defines

LL_LPUART_DATAWIDTH_7_BIT USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

LL_LPUART_DATAWIDTH_8_BIT 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

LL_LPUART_DATAWIDTH_9_BIT USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Clock Source Prescaler

group LPUART_LL_EC_PRESCALER

Defines

LL_LPUART_PRESCALER_DIV1 0x00000000U

Input clock not divided

LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock divided by 2

LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock divided by 4

LL_LPUART_PRESCALER_DIV6

(USART_PRESC_PRESCALER_1 |\

USART_PRESC_PRESCALER_0)


Input clock divided by 6

LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock divided by 8

LL_LPUART_PRESCALER_DIV10

(USART_PRESC_PRESCALER_2 |\

USART_PRESC_PRESCALER_0)


Input clock divided by 10

LL_LPUART_PRESCALER_DIV12

(USART_PRESC_PRESCALER_2 |\

USART_PRESC_PRESCALER_1)


Input clock divided by 12

LL_LPUART_PRESCALER_DIV16

(USART_PRESC_PRESCALER_2 |\

USART_PRESC_PRESCALER_1 |\

USART_PRESC_PRESCALER_0)


Input clock divided by 16

LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock divided by 32

LL_LPUART_PRESCALER_DIV64

(USART_PRESC_PRESCALER_3 |\

USART_PRESC_PRESCALER_0)


Input clock divided by 64

LL_LPUART_PRESCALER_DIV128

(USART_PRESC_PRESCALER_3 |\

USART_PRESC_PRESCALER_1)


Input clock divided by 128

LL_LPUART_PRESCALER_DIV256

(USART_PRESC_PRESCALER_3 |\

USART_PRESC_PRESCALER_1 |\

USART_PRESC_PRESCALER_0)


Input clock divided by 256

Stop Bits

group LPUART_LL_EC_STOPBITS

Defines

LL_LPUART_STOP_BIT_1 0x00000000U

1 stop bit

LL_LPUART_STOP_BIT_2 USART_CR2_STOP_1

2 stop bits

TX RX Pins Swap

group LPUART_LL_EC_TXRX

Defines

LL_LPUART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

RX Pin Active Level Inversion

group LPUART_LL_EC_RXPIN_LEVEL

Defines

LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

TX Pin Active Level Inversion

group LPUART_LL_EC_TXPIN_LEVEL

Defines

LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Binary Data Inversion

group LPUART_LL_EC_BINARY_LOGIC

Defines

LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Bit Order

group LPUART_LL_EC_BITORDER

Defines

LL_LPUART_BITORDER_LSBFIRST 0x00000000U

Data is transmitted/received with data bit 0 first, following the start bit

LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Data is transmitted/received with the MSB first, following the start bit

Address Length Detection

group LPUART_LL_EC_ADDRESS_DETECT

Defines

LL_LPUART_ADDRESS_DETECT_4_BIT 0x00000000U

4-bit address detection method selected

LL_LPUART_ADDRESS_DETECT_7_BIT USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Hardware Control

group LPUART_LL_EC_HWCONTROL

Defines

LL_LPUART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Driver Enable Polarity

group LPUART_LL_EC_DE_POLARITY

Defines

LL_LPUART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

DMA Register Data

group LPUART_LL_EC_DMA_REG_DATA

Defines

LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Request

group LPUART_LL_EC_REQUEST

Defines

LL_LPUART_REQUEST_SEND_BREAK USART_RQR_SBKRQ

Send Break Request

LL_LPUART_REQUEST_MUTE_MODE USART_RQR_MMRQ

mute mode Request

LL_LPUART_REQUEST_RXDATA_FLUSH USART_RQR_RXFRQ

receive data flush Request

LL_LPUART_REQUEST_TXDATA_FLUSH USART_RQR_TXFRQ

transmit data flush Request

Autonomous Trigger selection

group LPUART_LL_EC_AUTOCR_TRIGSEL

LPUART Autonomous Trigger selection.

Defines

LL_LPUART_TRIG_LPDMA1_CH0_TC (uint32_t)(0U << USART_AUTOCR_TRIGSEL_Pos)

LPUART LPDMA1 channel0 Internal Trigger

LL_LPUART_TRIG_LPDMA1_CH1_TC (uint32_t)(1U << USART_AUTOCR_TRIGSEL_Pos)

LPUART LPDMA1 channel1 Internal Trigger

LL_LPUART_TRIG_LPDMA1_CH2_TC (uint32_t)(2U << USART_AUTOCR_TRIGSEL_Pos)

LPUART LPDMA1 channel2 Internal Trigger

LL_LPUART_TRIG_LPDMA1_CH3_TC (uint32_t)(3U << USART_AUTOCR_TRIGSEL_Pos)

LPUART LPDMA1 channel3 Internal Trigger

LL_LPUART_TRIG_EXTI6 (uint32_t)(4U << USART_AUTOCR_TRIGSEL_Pos)

LPUART EXTI line 6 Internal Trigger

LL_LPUART_TRIG_EXTI8 (uint32_t)(5U << USART_AUTOCR_TRIGSEL_Pos)

LPUART EXTI line 8 Internal Trigger

LL_LPUART_TRIG_LPTIM1_CH1 (uint32_t)(6U << USART_AUTOCR_TRIGSEL_Pos)

LPUART LPTIM1 channel1 Internal Trigger

LL_LPUART_TRIG_LPTIM3_CH1 (uint32_t)(7U << USART_AUTOCR_TRIGSEL_Pos)

LPUART LPTIM3 channel1 Internal Trigger

LL_LPUART_TRIG_COMP1_OUT (uint32_t)(8U << USART_AUTOCR_TRIGSEL_Pos)

LPUART COMP1 out Internal Trigger

LL_LPUART_TRIG_COMP2_OUT (uint32_t)(9U << USART_AUTOCR_TRIGSEL_Pos)

LPUART COMP2 out Internal Trigger

LL_LPUART_TRIG_RTC_ALRA_TRG (uint32_t)(10U << USART_AUTOCR_TRIGSEL_Pos)

LPUART RTC alarm Internal Trigger

LL_LPUART_TRIG_RTC_WUT_TRG (uint32_t)(11U << USART_AUTOCR_TRIGSEL_Pos)

LPUART RTC wakeup Internal Trigger

Autonomous trigger polarity

group LPUART_LL_EC_AUTOCR_TRIGPOL

LPUART autonomous trigger polarity.

Defines

LL_LPUART_TRIG_POLARITY_RISING 0x00000000U

LPUART triggered on rising edge

LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL

LPUART triggered on falling edge