Reference Manual to LL API cross reference ¶

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for RCC registers

Register	Bit	Function
AHB1ENR	BKPSRAMEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CORDICEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CRCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DCACHE1EN	`LL_AHB1_GRP1_EnableClock()`
AHB1ENR	DCACHE2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DCACHEEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DMA2DEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FLASHEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FMACEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GFXMMUEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPU2DEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GTZC1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	JPEGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	MDF1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	RAMCFGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	TSCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1RSTR	CORDICRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	CRCRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	DCACHE2RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	DMA2DRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	FMACRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GFXMMURSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPDMA1RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPU2DRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	JPEGRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	MDF1RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	RAMCFGRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	TSCRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1SMENR	BKPSRAMSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	CORDICSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	CRCSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DCACHE2SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DCACHESMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DMA2DSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	FLASHSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	FMACSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GFXMMUSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GPDMA1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GPU2DSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GTZC1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	ICACHESMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	JPEGSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	MDF1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	RAMCFGSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	SRAM1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	TSCSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB2ENR1	ADC12EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	AESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	DCMI_PSSIEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOCEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIODEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOEEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOFEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOIEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOJEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	HASHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OCTOSPIMEN	`LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OSPIMEN	`LL_AHB2_GRP1_DisableClock()`
AHB2ENR1	OTFDEC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTFDEC2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGHSPHYEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGHSPHYSMEN	`LL_AHB2_GRP1_EnableClockStopSleep()`
AHB2ENR1	PKAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	RNGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SAESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SDMMC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SDMMC2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SRAM2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SRAM3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR2	FSMCEN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	HSPI1EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	OCTOSPI1EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	OCTOSPI2EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	SRAM5EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	SRAM6EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()`
AHB2RSTR1	ADC12RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	AESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	DCMI_PSSIRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOCRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIODRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOERST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOFRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOIRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOJRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	HASHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OCTOSPIMRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTFDEC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTFDEC2RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	PKARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	RNGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SAESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SDMMC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SDMMC2RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR2	FSMCRST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	HSPI1RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	OCTOSPI1RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	OCTOSPI2RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2SMENR1	ADC12SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	AESSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	DCMI_PSSISMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOASMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOBSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOCSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIODSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOESMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOFSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOHSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOISMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOJSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	HASHSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OSPIMSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTFDEC1SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTFDEC2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTGHSPHYSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	PKASMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	RNGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SAESSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SDMMC1SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SDMMC2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SRAM2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SRAM3SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR2	FSMCSMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	HSPI1SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	OCTOSPI1SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	OCTOSPI2SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	SRAM5SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	SRAM6SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB3ENR	ADC4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	ADF1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	GTZC2EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	LPDMA1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	LPGPIO1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	PWREN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	SRAM4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3RSTR	ADC4RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	ADF1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	GTZC2RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	LPDMA1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	LPGPIO1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	PWRRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3SMENR	ADC4SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	ADF1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	DAC1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	GTZC2SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	LPDMA1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	LPGPIO1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	PWRSMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	SRAM4SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
APB1ENR1	CRSEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART6N	`LL_APB1_GRP1_EnableClock()`
APB1ENR1	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR2	FDCAN1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C4EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C5EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C6EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	LPTIM2EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	UCPD1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1RSTR1	CRSRST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR2	FDCAN1RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C4RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C5RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C6RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	LPTIM2RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPD1RST	`LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPDRST	`LL_APB1_GRP2_DisableClock()`
APB1SMENR1	CRSSMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	I2C1SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	I2C2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	SPI2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM3SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM4SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM5SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM6SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM7SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	UART4SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	UART5SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART3SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART6SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR2	FDCAN1SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C4SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C5SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C6SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	LPTIM2SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	UCPD1SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB2ENR	DSIHOSTEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	GFXTIMEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	LTDCEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SAI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SAI2EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USBEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2RSTR	DSIHOSTRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	GFXTIMRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	LTDCRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SAI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SAI2RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USBRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2SMENR	DSIHOSTSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	GFXTIMSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	LTDCSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SAI1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SAI2SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SPI1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM15SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM16SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM17SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM8SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	USART1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	USBSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB3ENR	COMPEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	I2C3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM4EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPUART1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	OPAMPEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	RTCAPBEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SPI3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SYSCFGEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	VREFEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3RSTR	COMPRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	I2C3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM4RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPUART1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	OPAMPRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	RTCAPBRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SPI3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SYSCFGRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	VREFRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3SMENR	COMPSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	I2C3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM1SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM4SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPUART1SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	OPAMPSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	RTCAPBSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	SPI3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	SYSCFGSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	VREFSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
BDCR	BDRST	`LL_RCC_ForceBackupDomainReset()` `LL_RCC_ReleaseBackupDomainReset()`
BDCR	LSCOEN	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_Disable()` `LL_RCC_LSCO_Enable()`
BDCR	LSCOSEL	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_GetSource()` `LL_RCC_LSCO_SetSource()`
BDCR	LSEBYP	`LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()`
BDCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
BDCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
BDCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
BDCR	LSEGFON	`LL_RCC_LSE_DisableGlitchFilter()` `LL_RCC_LSE_EnableGlitchFilter()` `LL_RCC_LSE_IsGlitchFilterEnabled()`
BDCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
BDCR	LSERDY	`LL_RCC_LSE_IsReady()`
BDCR	LSESYSEN	`LL_RCC_LSE_DisablePropagation()` `LL_RCC_LSE_EnablePropagation()`
BDCR	LSESYSRDY	`LL_RCC_LSE_IsPropagationReady()`
BDCR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
BDCR	LSIPREDIV	`LL_RCC_LSI_GetPrescaler()` `LL_RCC_LSI_SetPrescaler()`
BDCR	LSIRDY	`LL_RCC_LSI_IsReady()`
BDCR	RCC_BDCR_LSEBYP	`LL_RCC_LSE_IsBypassed()`
BDCR	RCC_BDCR_LSESYSEN	`LL_RCC_LSE_IsPropagationEnabled()`
BDCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
BDCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`
CCIPR1	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR1	I2C1SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	I2C2SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	I2C4SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	ICLKSEL	`LL_RCC_GetSDMMCClockSource()` `LL_RCC_GetUSBClockSource()` `LL_RCC_SetSDMMCClockSource()` `LL_RCC_SetUSBClockSource()`
CCIPR1	LPTIM2SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR1	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()`
CCIPR1	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI2SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SYSTICKSEL	`LL_RCC_GetSystickClockSource()` `LL_RCC_SetSystickClockSource()`
CCIPR1	TIMICSEL	`LL_RCC_GetTIMICClockSource()` `LL_RCC_SetTIMICClockSource()`
CCIPR1	UART4SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART5SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	USART1SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART2SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART3SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR2	DSISEL	`LL_RCC_GetDSIClockSource()` `LL_RCC_SetDSIClockSource()`
CCIPR2	HSPISEL	`LL_RCC_GetHSPIClockSource()` `LL_RCC_SetHSPIClockSource()`
CCIPR2	LTDCSEL	`LL_RCC_GetLTDCClockSource()` `LL_RCC_SetLTDCClockSource()`
CCIPR2	MDF1SEL	`LL_RCC_GetMDF1ClockSource()`
CCIPR2	OSPISEL	`LL_RCC_GetOCTOSPIClockSource()` `LL_RCC_SetOCTOSPIClockSource()`
CCIPR2	OTGHSSEL	`LL_RCC_GetUSBHSPHYClockSource()` `LL_RCC_SetUSBHSPHYClockSource()`
CCIPR2	RNGSEL	`LL_RCC_GetRNGClockSource()` `LL_RCC_SetRNGClockSource()`
CCIPR2	SAESSEL	`LL_RCC_GetSAESClockSource()` `LL_RCC_SetSAESClockSource()`
CCIPR2	SAI1SEL	`LL_RCC_GetSAIClockSource()` `LL_RCC_SetSAIClockSource()`
CCIPR2	SAI2SEL	`LL_RCC_GetSAIClockSource()` `LL_RCC_SetSAIClockSource()`
CCIPR2	SDMMCSEL	`LL_RCC_GetSDMMCKernelClockSource()` `LL_RCC_SetSDMMCKernelClockSource()`
CCIPR2	USART6SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR3	ADCDACSEL	`LL_RCC_SetADCDACClockSource()`
CCIPR3	ADF1SEL	`LL_RCC_GetADF1ClockSource()` `LL_RCC_SetADF1ClockSource()`
CCIPR3	DAC1SEL	`LL_RCC_GetDAC1ClockSource()` `LL_RCC_SetDAC1ClockSource()`
CCIPR3	I2C3SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR3	LPTIM2SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR3	LPTIM34SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR3	LPUART1SEL	`LL_RCC_SetLPUARTClockSource()`
CCIPR3	MDF1SEL	`LL_RCC_SetMDF1ClockSource()`
CCIPR3	SPI3SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CFGR1	MCOPRE	`LL_RCC_ConfigMCO()`
CFGR1	MCOSEL	`LL_RCC_ConfigMCO()`
CFGR1	STOPKERWUCK	`LL_RCC_GetKerClkAfterWakeFromStop()` `LL_RCC_SetKerClkAfterWakeFromStop()`
CFGR1	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR1	SW	`LL_RCC_SetSysClkSource()`
CFGR1	SWS	`LL_RCC_GetSysClkSource()`
CFGR2	AHB1DIS	`LL_AHB1_GRP1_DisableBusClock()` `LL_AHB1_GRP1_EnableBusClock()` `LL_AHB1_GRP1_IsEnabledBusClock()`
CFGR2	AHB2DIS1	`LL_AHB2_GRP1_DisableBusClock()` `LL_AHB2_GRP1_EnableBusClock()` `LL_AHB2_GRP1_IsEnabledBusClock()`
CFGR2	AHB2DIS2	`LL_AHB2_GRP2_DisableBusClock()` `LL_AHB2_GRP2_EnableBusClock()` `LL_AHB2_GRP2_IsEnabledBusClock()`
CFGR2	AHB3DIS	`LL_AHB3_GRP1_DisableBusClock()`
CFGR2	APB1DIS	`LL_APB1_GRP1_DisableBusClock()` `LL_APB1_GRP1_EnableBusClock()` `LL_APB1_GRP1_IsEnabledBusClock()`
CFGR2	APB2DIS	`LL_APB2_GRP1_DisableBusClock()` `LL_APB2_GRP1_EnableBusClock()` `LL_APB2_GRP1_IsEnabledBusClock()`
CFGR2	APB3DIS	`LL_APB3_GRP1_DisableBusClock()`
CFGR2	HPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAHBPrescaler()` `LL_RCC_SetAHBPrescaler()`
CFGR2	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
CFGR2	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
CFGR2	PPRE_DPHY	`LL_RCC_GetDPHYPrescaler()` `LL_RCC_SetDPHYPrescaler()`
CFGR3	AHB3DIS	`LL_AHB3_GRP1_EnableBusClock()` `LL_AHB3_GRP1_IsEnabledBusClock()`
CFGR3	APB3DIS	`LL_APB3_GRP1_EnableBusClock()` `LL_APB3_GRP1_IsEnabledBusClock()`
CFGR3	PPRE3	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB3Prescaler()`
CICR	CSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	CSSF	`LL_RCC_IsActiveFlag()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSERDYF	`LL_RCC_IsActiveFlag()`
CICR	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	HSI48RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSI48RDY()`
CICR	HSI48RDYF	`LL_RCC_IsActiveFlag()`
CICR	HSI48RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	HSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSERDYF	`LL_RCC_IsActiveFlag()`
CICR	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	LSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	MSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_MSIKRDY()`
CICR	MSIKRDYF	`LL_RCC_IsActiveFlag()`
CICR	MSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	MSISRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_MSIRDY()`
CICR	MSISRDYF	`LL_RCC_IsActiveFlag()`
CICR	MSISRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL1RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL1RDY()`
CICR	PLL1RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL1RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL2RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL2RDY()`
CICR	PLL2RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL2RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL3RDY()`
CICR	PLL3RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	SHSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_SHSIRDY()`
CICR	SHSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	SHSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CIER	HSERDYIE	`LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSI48RDYIE	`LL_RCC_DisableIT_HSI48RDY()` `LL_RCC_EnableIT_HSI48RDY()` `LL_RCC_IsEnabledIT_HSI48RDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSERDYIE	`LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	MSIKRDYIE	`LL_RCC_DisableIT_MSIKRDY()` `LL_RCC_EnableIT_MSIKRDY()` `LL_RCC_IsEnabledIT_MSIKRDY()`
CIER	MSIRDYIE	`LL_RCC_EnableIT_MSIRDY()` `LL_RCC_IsEnabledIT_MSIRDY()`
CIER	MSISRDYIE	`LL_RCC_DisableIT_MSIRDY()`
CIER	PLL1RDYIE	`LL_RCC_DisableIT_PLL1RDY()` `LL_RCC_EnableIT_PLL1RDY()` `LL_RCC_IsEnabledIT_PLL1RDY()`
CIER	PLL2RDYIE	`LL_RCC_DisableIT_PLL2RDY()` `LL_RCC_EnableIT_PLL2RDY()` `LL_RCC_IsEnabledIT_PLL2RDY()`
CIER	PLL3RDYIE	`LL_RCC_DisableIT_PLL3RDY()` `LL_RCC_EnableIT_PLL3RDY()` `LL_RCC_IsEnabledIT_PLL3RDY()`
CIER	SHSIRDYIE	`LL_RCC_DisableIT_SHSIRDY()` `LL_RCC_EnableIT_SHSIRDY()` `LL_RCC_IsEnabledIT_SHSIRDY()`
CIFR	CSSF	`LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSI48RDYF	`LL_RCC_IsActiveFlag_HSI48RDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	MSIKRDYF	`LL_RCC_IsActiveFlag_MSIKRDY()`
CIFR	MSISRDYF	`LL_RCC_IsActiveFlag_MSIRDY()`
CIFR	PLL1RDYF	`LL_RCC_IsActiveFlag_PLL1RDY()`
CIFR	PLL2RDYF	`LL_RCC_IsActiveFlag_PLL2RDY()`
CIFR	PLL3RDYF	`LL_RCC_IsActiveFlag_PLL3RDY()`
CIFR	SHSIRDYF	`LL_RCC_IsActiveFlag_SHSIRDY()`
CR	CSSON	`LL_RCC_HSE_EnableCSS()`
CR	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetClockMode()` `LL_RCC_HSE_SetClockMode()`
CR	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR	HSERDY	`LL_RCC_HSE_IsReady()`
CR	HSI48ON	`LL_RCC_HSI48_Disable()` `LL_RCC_HSI48_Enable()` `LL_RCC_HSI48_IsEnabled()`
CR	HSI48RDY	`LL_RCC_HSI48_IsReady()`
CR	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR	HSION	`LL_RCC_HSI_Disable()` `LL_RCC_HSI_Enable()` `LL_RCC_HSI_IsEnabled()`
CR	HSIRDY	`LL_RCC_HSI_IsReady()`
CR	MSIKERON	`LL_RCC_MSIK_DisableInStopMode()` `LL_RCC_MSIK_EnableInStopMode()` `LL_RCC_MSIK_IsEnabledInStopMode()`
CR	MSIKON	`LL_RCC_MSIK_Disable()` `LL_RCC_MSIK_Enable()` `LL_RCC_MSIK_IsEnabled()`
CR	MSIKRDY	`LL_RCC_MSIK_IsReady()`
CR	MSIPLLEN	`LL_RCC_IsEnabledPLLMode()` `LL_RCC_MSI_DisablePLLMode()` `LL_RCC_MSI_EnablePLLMode()`
CR	MSIPLLFAST	`LL_RCC_Disable_MSIPLLFAST()` `LL_RCC_Enable_MSIPLLFAST()` `LL_RCC_MSI_ConfigHWAutoCalib()` `LL_RCC_MSI_IsEnabledMSIPLLFAST()`
CR	MSIPLLSEL	`LL_RCC_GetMSIPLLMode()` `LL_RCC_MSI_ConfigHWAutoCalib()` `LL_RCC_SetMSIPLLMode()`
CR	MSISON	`LL_RCC_MSIS_Disable()` `LL_RCC_MSIS_Enable()` `LL_RCC_MSIS_IsEnabled()`
CR	MSISRDY	`LL_RCC_MSIS_IsReady()`
CR	PLL1ON	`LL_RCC_PLL1_Enable()`
CR	PLL1RDY	`LL_RCC_PLL1_IsReady()`
CR	PLL2ON	`LL_RCC_PLL2_Disable()` `LL_RCC_PLL2_Enable()`
CR	PLL2RDY	`LL_RCC_PLL2_IsReady()`
CR	PLL3ON	`LL_RCC_PLL3_Disable()` `LL_RCC_PLL3_Enable()`
CR	PLL3RDY	`LL_RCC_PLL3_IsReady()`
CR	PLLON	`LL_RCC_PLL1_Disable()`
CR	PRIV	`LL_RCC_DisablePrivilegedMode()` `LL_RCC_IsEnabledPrivilegedMode()`
CR	SHSION	`LL_RCC_SHSI_Disable()` `LL_RCC_SHSI_Enable()` `LL_RCC_SHSI_IsEnabled()`
CR	SHSIRDY	`LL_RCC_SHSI_IsReady()`
CRRCR	HSI48CAL	`LL_RCC_HSI48_GetCalibration()`
CSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
CSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
CSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
CSR	MSIKSRANGE	`LL_RCC_MSIK_GetRangeAfterStandby()` `LL_RCC_MSIK_SetRangeAfterStandby()`
CSR	MSISSRANGE	`LL_RCC_MSIS_GetRangeAfterStandby()` `LL_RCC_MSIS_SetRangeAfterStandby()`
CSR	OBLRSTF	`LL_RCC_IsActiveFlag_OBLRST()`
CSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
CSR	RMVF	`LL_RCC_ClearResetFlags()`
CSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
CSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`
ICSC3R	HSITRIM	`LL_RCC_HSI_GetCalibTrimming()`
ICSCR1	MSIBIAS	`LL_RCC_MSI_GetMSIBiasMode()` `LL_RCC_MSI_SetMSIBiasMode()`
ICSCR1	MSICALx	`LL_RCC_MSI_GetCalibration()`
ICSCR1	MSIKRANGE	`LL_RCC_MSIK_GetRange()` `LL_RCC_MSIK_SetRange()` `LL_RCC_MSIK_SwitchRange()`
ICSCR1	MSIRGSEL	`LL_RCC_MSIK_SwitchRange()` `LL_RCC_MSIS_SwitchRange()` `LL_RCC_MSI_EnableRangeSelection()` `LL_RCC_MSI_IsEnabledRangeSelect()`
ICSCR1	MSISRANGE	`LL_RCC_MSIS_GetRange()` `LL_RCC_MSIS_SetRange()` `LL_RCC_MSIS_SwitchRange()`
ICSCR2	MSITRIMx	`LL_RCC_MSI_GetCalibTrimming()` `LL_RCC_MSI_SetCalibTrimming()`
ICSCR3	HSICAL	`LL_RCC_HSI_GetCalibration()`
ICSCR3	HSITRIM	`LL_RCC_HSI_SetCalibTrimming()`
PLL1CFGR	PLL1FRACEN	`LL_RCC_PLL1FRACN_Disable()` `LL_RCC_PLL1FRACN_Enable()` `LL_RCC_PLL1FRACN_IsEnabled()`
PLL1CFGR	PLL1M	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetDivider()` `LL_RCC_PLL1_SetDivider()`
PLL1CFGR	PLL1MBOOST	`LL_RCC_GetPll1EPodPrescaler()` `LL_RCC_PLL1_Config()` `LL_RCC_SetPll1EPodPrescaler()`
PLL1CFGR	PLL1N	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetN()` `LL_RCC_PLL1_SetN()`
PLL1CFGR	PLL1P	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_GetP()` `LL_RCC_PLL1_SetP()`
PLL1CFGR	PLL1PEN	`LL_RCC_PLL1_DisableDomain_SAI()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_SAI()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_SAI()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1Q	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_GetQ()`
PLL1CFGR	PLL1QEN	`LL_RCC_PLL1_DisableDomain_48M()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_48M()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_48M()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1R	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_SYS()`
PLL1CFGR	PLL1REN	`LL_RCC_PLL1_DisableDomain_SYS()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_SYS()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_SYS()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1RGE	`LL_RCC_PLL1_SetVCOInputRange()`
PLL1CFGR	PLL1SRC	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetMainSource()` `LL_RCC_PLL1_SetMainSource()`
PLL1DIVR	PLL1Q	`LL_RCC_PLL1_SetQ()`
PLL1DIVR	PLL1R	`LL_RCC_PLL1_GetR()` `LL_RCC_PLL1_SetR()`
PLL1FRACR	PLL1FRACN	`LL_RCC_PLL1_GetFRACN()` `LL_RCC_PLL1_SetFRACN()`
PLL2CFGR	PLL2FRACEN	`LL_RCC_PLL2FRACN_Disable()` `LL_RCC_PLL2FRACN_Enable()` `LL_RCC_PLL2FRACN_IsEnabled()`
PLL2CFGR	PLL2M	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetDivider()` `LL_RCC_PLL2_SetDivider()`
PLL2CFGR	PLL2N	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetN()` `LL_RCC_PLL2_SetN()`
PLL2CFGR	PLL2P	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_GetP()` `LL_RCC_PLL2_SetP()`
PLL2CFGR	PLL2PEN	`LL_RCC_PLL2_DisableDomain_SAI()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_SAI()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_SAI()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2Q	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_GetQ()`
PLL2CFGR	PLL2QEN	`LL_RCC_PLL2_DisableDomain_48M()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_48M()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_48M()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2R	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_SetR()`
PLL2CFGR	PLL2REN	`LL_RCC_PLL2_DisableDomain_ADC()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_ADC()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_ADC()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2RGE	`LL_RCC_PLL2_SetVCOInputRange()`
PLL2CFGR	PLL2SRC	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetSource()` `LL_RCC_PLL2_SetSource()`
PLL2DIVR	PLL2Q	`LL_RCC_PLL2_SetQ()`
PLL2DIVR	PLL2R	`LL_RCC_PLL2_GetR()`
PLL2FRACR	PLL2FRACN	`LL_RCC_PLL2_GetFRACN()` `LL_RCC_PLL2_SetFRACN()`
PLL3CFGR	PLL3FRACEN	`LL_RCC_PLL3FRACN_Disable()` `LL_RCC_PLL3FRACN_Enable()` `LL_RCC_PLL3FRACN_IsEnabled()`
PLL3CFGR	PLL3M	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetDivider()` `LL_RCC_PLL3_SetDivider()`
PLL3CFGR	PLL3N	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetN()` `LL_RCC_PLL3_SetN()`
PLL3CFGR	PLL3P	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_GetP()` `LL_RCC_PLL3_SetP()`
PLL3CFGR	PLL3PEN	`LL_RCC_PLL3_DisableDomain_SAI()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_SAI()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_SAI()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3Q	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_GetQ()`
PLL3CFGR	PLL3QEN	`LL_RCC_PLL3_DisableDomain_48M()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_48M()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_48M()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3R	`LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_SetR()`
PLL3CFGR	PLL3REN	`LL_RCC_PLL3_DisableDomain_HSPI_LTDC()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_HSPI_LTDC()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3RGE	`LL_RCC_PLL3_SetVCOInputRange()`
PLL3CFGR	PLL3SRC	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetSource()` `LL_RCC_PLL3_SetSource()`
PLL3DIVR	PLL3P	`LL_RCC_PLL3_ConfigDomain_SAI()`
PLL3DIVR	PLL3Q	`LL_RCC_PLL3_SetQ()`
PLL3DIVR	PLL3R	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_GetR()`
PLL3FRACR	PLL3FRACN	`LL_RCC_PLL3_GetFRACN()` `LL_RCC_PLL3_SetFRACN()`
PLLC1FGR	PLL1M	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1N	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1P	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1SRC	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC2FGR	PLL2M	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2N	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2P	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2SRC	`LL_RCC_PLL2_ConfigDomain_SAI()`
PRIVCFGR	NSPRIV	`LL_RCC_DisableNSecPrivilegedMode()` `LL_RCC_EnableNSecPrivilegedMode()` `LL_RCC_EnablePrivilegedMode()` `LL_RCC_IsEnabledNSecPrivilegedMode()`
PRIVCFGR	SPRIV	`LL_RCC_DisableSecPrivilegedMode()` `LL_RCC_EnablePrivilegedMode()` `LL_RCC_EnableSecPrivilegedMode()` `LL_RCC_IsEnabledSecPrivilegedMode()`
SECCFGR	CLK48MSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSESEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSI48SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	LSESEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	LSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	MSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL1SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL2SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL3SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PRESCSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	RMVFSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	SYSCLKSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SRDAMR	ADC4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	ADF1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	COMPAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	DAC1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	I2C3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPDMA1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPGPIO1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPUART1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	OPAMPAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	RTCAPBAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	SPI3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	SRAM4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	VREFAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	VREFRST	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`

Register	Bit	Function
AHB1ENR	BKPSRAMEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CORDICEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CRCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DCACHE1EN	`LL_AHB1_GRP1_EnableClock()`
AHB1ENR	DCACHE2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DCACHEEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DMA2DEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FLASHEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FMACEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GFXMMUEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPU2DEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GTZC1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	JPEGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	MDF1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	RAMCFGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	TSCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1RSTR	CORDICRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	CRCRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	DCACHE2RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	DMA2DRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	FMACRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GFXMMURSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPDMA1RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPU2DRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	JPEGRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	MDF1RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	RAMCFGRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	TSCRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1SMENR	BKPSRAMSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	CORDICSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	CRCSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DCACHE2SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DCACHESMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DMA2DSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	FLASHSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	FMACSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GFXMMUSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GPDMA1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GPU2DSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GTZC1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	ICACHESMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	JPEGSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	MDF1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	RAMCFGSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	SRAM1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	TSCSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB2ENR1	ADC12EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	AESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	DCMI_PSSIEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOCEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIODEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOEEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOFEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOIEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOJEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	HASHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OCTOSPIMEN	`LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OSPIMEN	`LL_AHB2_GRP1_DisableClock()`
AHB2ENR1	OTFDEC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTFDEC2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGHSPHYEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGHSPHYSMEN	`LL_AHB2_GRP1_EnableClockStopSleep()`
AHB2ENR1	PKAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	RNGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SAESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SDMMC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SDMMC2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SRAM2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SRAM3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR2	FSMCEN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	HSPI1EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	OCTOSPI1EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	OCTOSPI2EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	SRAM5EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	SRAM6EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()`
AHB2RSTR1	ADC12RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	AESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	DCMI_PSSIRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOCRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIODRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOERST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOFRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOIRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOJRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	HASHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OCTOSPIMRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTFDEC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTFDEC2RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	PKARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	RNGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SAESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SDMMC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SDMMC2RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR2	FSMCRST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	HSPI1RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	OCTOSPI1RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	OCTOSPI2RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2SMENR1	ADC12SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	AESSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	DCMI_PSSISMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOASMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOBSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOCSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIODSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOESMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOFSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOHSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOISMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOJSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	HASHSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OSPIMSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTFDEC1SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTFDEC2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTGHSPHYSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	PKASMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	RNGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SAESSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SDMMC1SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SDMMC2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SRAM2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SRAM3SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR2	FSMCSMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	HSPI1SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	OCTOSPI1SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	OCTOSPI2SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	SRAM5SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	SRAM6SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB3ENR	ADC4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	ADF1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	GTZC2EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	LPDMA1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	LPGPIO1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	PWREN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	SRAM4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3RSTR	ADC4RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	ADF1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	GTZC2RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	LPDMA1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	LPGPIO1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	PWRRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3SMENR	ADC4SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	ADF1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	DAC1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	GTZC2SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	LPDMA1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	LPGPIO1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	PWRSMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	SRAM4SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
APB1ENR1	CRSEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART6N	`LL_APB1_GRP1_EnableClock()`
APB1ENR1	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR2	FDCAN1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C4EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C5EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C6EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	LPTIM2EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	UCPD1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1RSTR1	CRSRST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR2	FDCAN1RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C4RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C5RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C6RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	LPTIM2RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPD1RST	`LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPDRST	`LL_APB1_GRP2_DisableClock()`
APB1SMENR1	CRSSMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	I2C1SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	I2C2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	SPI2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM3SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM4SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM5SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM6SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM7SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	UART4SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	UART5SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART3SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART6SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR2	FDCAN1SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C4SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C5SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C6SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	LPTIM2SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	UCPD1SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB2ENR	DSIHOSTEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	GFXTIMEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	LTDCEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SAI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SAI2EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USBEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2RSTR	DSIHOSTRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	GFXTIMRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	LTDCRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SAI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SAI2RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USBRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2SMENR	DSIHOSTSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	GFXTIMSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	LTDCSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SAI1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SAI2SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SPI1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM15SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM16SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM17SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM8SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	USART1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	USBSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB3ENR	COMPEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	I2C3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM4EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPUART1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	OPAMPEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	RTCAPBEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SPI3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SYSCFGEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	VREFEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3RSTR	COMPRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	I2C3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM4RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPUART1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	OPAMPRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	RTCAPBRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SPI3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SYSCFGRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	VREFRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3SMENR	COMPSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	I2C3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM1SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM4SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPUART1SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	OPAMPSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	RTCAPBSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	SPI3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	SYSCFGSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	VREFSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
BDCR	BDRST	`LL_RCC_ForceBackupDomainReset()` `LL_RCC_ReleaseBackupDomainReset()`
BDCR	LSCOEN	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_Disable()` `LL_RCC_LSCO_Enable()`
BDCR	LSCOSEL	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_GetSource()` `LL_RCC_LSCO_SetSource()`
BDCR	LSEBYP	`LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()`
BDCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
BDCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
BDCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
BDCR	LSEGFON	`LL_RCC_LSE_DisableGlitchFilter()` `LL_RCC_LSE_EnableGlitchFilter()` `LL_RCC_LSE_IsGlitchFilterEnabled()`
BDCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
BDCR	LSERDY	`LL_RCC_LSE_IsReady()`
BDCR	LSESYSEN	`LL_RCC_LSE_DisablePropagation()` `LL_RCC_LSE_EnablePropagation()`
BDCR	LSESYSRDY	`LL_RCC_LSE_IsPropagationReady()`
BDCR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
BDCR	LSIPREDIV	`LL_RCC_LSI_GetPrescaler()` `LL_RCC_LSI_SetPrescaler()`
BDCR	LSIRDY	`LL_RCC_LSI_IsReady()`
BDCR	RCC_BDCR_LSEBYP	`LL_RCC_LSE_IsBypassed()`
BDCR	RCC_BDCR_LSESYSEN	`LL_RCC_LSE_IsPropagationEnabled()`
BDCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
BDCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`
CCIPR1	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR1	I2C1SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	I2C2SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	I2C4SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	ICLKSEL	`LL_RCC_GetSDMMCClockSource()` `LL_RCC_GetUSBClockSource()` `LL_RCC_SetSDMMCClockSource()` `LL_RCC_SetUSBClockSource()`
CCIPR1	LPTIM2SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR1	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()`
CCIPR1	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI2SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SYSTICKSEL	`LL_RCC_GetSystickClockSource()` `LL_RCC_SetSystickClockSource()`
CCIPR1	TIMICSEL	`LL_RCC_GetTIMICClockSource()` `LL_RCC_SetTIMICClockSource()`
CCIPR1	UART4SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART5SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	USART1SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART2SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART3SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR2	DSISEL	`LL_RCC_GetDSIClockSource()` `LL_RCC_SetDSIClockSource()`
CCIPR2	HSPISEL	`LL_RCC_GetHSPIClockSource()` `LL_RCC_SetHSPIClockSource()`
CCIPR2	LTDCSEL	`LL_RCC_GetLTDCClockSource()` `LL_RCC_SetLTDCClockSource()`
CCIPR2	MDF1SEL	`LL_RCC_GetMDF1ClockSource()`
CCIPR2	OSPISEL	`LL_RCC_GetOCTOSPIClockSource()` `LL_RCC_SetOCTOSPIClockSource()`
CCIPR2	OTGHSSEL	`LL_RCC_GetUSBHSPHYClockSource()` `LL_RCC_SetUSBHSPHYClockSource()`
CCIPR2	RNGSEL	`LL_RCC_GetRNGClockSource()` `LL_RCC_SetRNGClockSource()`
CCIPR2	SAESSEL	`LL_RCC_GetSAESClockSource()` `LL_RCC_SetSAESClockSource()`
CCIPR2	SAI1SEL	`LL_RCC_GetSAIClockSource()` `LL_RCC_SetSAIClockSource()`
CCIPR2	SAI2SEL	`LL_RCC_GetSAIClockSource()` `LL_RCC_SetSAIClockSource()`
CCIPR2	SDMMCSEL	`LL_RCC_GetSDMMCKernelClockSource()` `LL_RCC_SetSDMMCKernelClockSource()`
CCIPR2	USART6SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR3	ADCDACSEL	`LL_RCC_SetADCDACClockSource()`
CCIPR3	ADF1SEL	`LL_RCC_GetADF1ClockSource()` `LL_RCC_SetADF1ClockSource()`
CCIPR3	DAC1SEL	`LL_RCC_GetDAC1ClockSource()` `LL_RCC_SetDAC1ClockSource()`
CCIPR3	I2C3SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR3	LPTIM2SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR3	LPTIM34SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR3	LPUART1SEL	`LL_RCC_SetLPUARTClockSource()`
CCIPR3	MDF1SEL	`LL_RCC_SetMDF1ClockSource()`
CCIPR3	SPI3SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CFGR1	MCOPRE	`LL_RCC_ConfigMCO()`
CFGR1	MCOSEL	`LL_RCC_ConfigMCO()`
CFGR1	STOPKERWUCK	`LL_RCC_GetKerClkAfterWakeFromStop()` `LL_RCC_SetKerClkAfterWakeFromStop()`
CFGR1	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR1	SW	`LL_RCC_SetSysClkSource()`
CFGR1	SWS	`LL_RCC_GetSysClkSource()`
CFGR2	AHB1DIS	`LL_AHB1_GRP1_DisableBusClock()` `LL_AHB1_GRP1_EnableBusClock()` `LL_AHB1_GRP1_IsEnabledBusClock()`
CFGR2	AHB2DIS1	`LL_AHB2_GRP1_DisableBusClock()` `LL_AHB2_GRP1_EnableBusClock()` `LL_AHB2_GRP1_IsEnabledBusClock()`
CFGR2	AHB2DIS2	`LL_AHB2_GRP2_DisableBusClock()` `LL_AHB2_GRP2_EnableBusClock()` `LL_AHB2_GRP2_IsEnabledBusClock()`
CFGR2	AHB3DIS	`LL_AHB3_GRP1_DisableBusClock()`
CFGR2	APB1DIS	`LL_APB1_GRP1_DisableBusClock()` `LL_APB1_GRP1_EnableBusClock()` `LL_APB1_GRP1_IsEnabledBusClock()`
CFGR2	APB2DIS	`LL_APB2_GRP1_DisableBusClock()` `LL_APB2_GRP1_EnableBusClock()` `LL_APB2_GRP1_IsEnabledBusClock()`
CFGR2	APB3DIS	`LL_APB3_GRP1_DisableBusClock()`
CFGR2	HPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAHBPrescaler()` `LL_RCC_SetAHBPrescaler()`
CFGR2	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
CFGR2	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
CFGR2	PPRE_DPHY	`LL_RCC_GetDPHYPrescaler()` `LL_RCC_SetDPHYPrescaler()`
CFGR3	AHB3DIS	`LL_AHB3_GRP1_EnableBusClock()` `LL_AHB3_GRP1_IsEnabledBusClock()`
CFGR3	APB3DIS	`LL_APB3_GRP1_EnableBusClock()` `LL_APB3_GRP1_IsEnabledBusClock()`
CFGR3	PPRE3	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB3Prescaler()`
CICR	CSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	CSSF	`LL_RCC_IsActiveFlag()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSERDYF	`LL_RCC_IsActiveFlag()`
CICR	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	HSI48RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSI48RDY()`
CICR	HSI48RDYF	`LL_RCC_IsActiveFlag()`
CICR	HSI48RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	HSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSERDYF	`LL_RCC_IsActiveFlag()`
CICR	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	LSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	MSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_MSIKRDY()`
CICR	MSIKRDYF	`LL_RCC_IsActiveFlag()`
CICR	MSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	MSISRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_MSIRDY()`
CICR	MSISRDYF	`LL_RCC_IsActiveFlag()`
CICR	MSISRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL1RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL1RDY()`
CICR	PLL1RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL1RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL2RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL2RDY()`
CICR	PLL2RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL2RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL3RDY()`
CICR	PLL3RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	SHSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_SHSIRDY()`
CICR	SHSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	SHSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CIER	HSERDYIE	`LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSI48RDYIE	`LL_RCC_DisableIT_HSI48RDY()` `LL_RCC_EnableIT_HSI48RDY()` `LL_RCC_IsEnabledIT_HSI48RDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSERDYIE	`LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	MSIKRDYIE	`LL_RCC_DisableIT_MSIKRDY()` `LL_RCC_EnableIT_MSIKRDY()` `LL_RCC_IsEnabledIT_MSIKRDY()`
CIER	MSIRDYIE	`LL_RCC_EnableIT_MSIRDY()` `LL_RCC_IsEnabledIT_MSIRDY()`
CIER	MSISRDYIE	`LL_RCC_DisableIT_MSIRDY()`
CIER	PLL1RDYIE	`LL_RCC_DisableIT_PLL1RDY()` `LL_RCC_EnableIT_PLL1RDY()` `LL_RCC_IsEnabledIT_PLL1RDY()`
CIER	PLL2RDYIE	`LL_RCC_DisableIT_PLL2RDY()` `LL_RCC_EnableIT_PLL2RDY()` `LL_RCC_IsEnabledIT_PLL2RDY()`
CIER	PLL3RDYIE	`LL_RCC_DisableIT_PLL3RDY()` `LL_RCC_EnableIT_PLL3RDY()` `LL_RCC_IsEnabledIT_PLL3RDY()`
CIER	SHSIRDYIE	`LL_RCC_DisableIT_SHSIRDY()` `LL_RCC_EnableIT_SHSIRDY()` `LL_RCC_IsEnabledIT_SHSIRDY()`
CIFR	CSSF	`LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSI48RDYF	`LL_RCC_IsActiveFlag_HSI48RDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	MSIKRDYF	`LL_RCC_IsActiveFlag_MSIKRDY()`
CIFR	MSISRDYF	`LL_RCC_IsActiveFlag_MSIRDY()`
CIFR	PLL1RDYF	`LL_RCC_IsActiveFlag_PLL1RDY()`
CIFR	PLL2RDYF	`LL_RCC_IsActiveFlag_PLL2RDY()`
CIFR	PLL3RDYF	`LL_RCC_IsActiveFlag_PLL3RDY()`
CIFR	SHSIRDYF	`LL_RCC_IsActiveFlag_SHSIRDY()`
CR	CSSON	`LL_RCC_HSE_EnableCSS()`
CR	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetClockMode()` `LL_RCC_HSE_SetClockMode()`
CR	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR	HSERDY	`LL_RCC_HSE_IsReady()`
CR	HSI48ON	`LL_RCC_HSI48_Disable()` `LL_RCC_HSI48_Enable()` `LL_RCC_HSI48_IsEnabled()`
CR	HSI48RDY	`LL_RCC_HSI48_IsReady()`
CR	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR	HSION	`LL_RCC_HSI_Disable()` `LL_RCC_HSI_Enable()` `LL_RCC_HSI_IsEnabled()`
CR	HSIRDY	`LL_RCC_HSI_IsReady()`
CR	MSIKERON	`LL_RCC_MSIK_DisableInStopMode()` `LL_RCC_MSIK_EnableInStopMode()` `LL_RCC_MSIK_IsEnabledInStopMode()`
CR	MSIKON	`LL_RCC_MSIK_Disable()` `LL_RCC_MSIK_Enable()` `LL_RCC_MSIK_IsEnabled()`
CR	MSIKRDY	`LL_RCC_MSIK_IsReady()`
CR	MSIPLLEN	`LL_RCC_IsEnabledPLLMode()` `LL_RCC_MSI_DisablePLLMode()` `LL_RCC_MSI_EnablePLLMode()`
CR	MSIPLLFAST	`LL_RCC_Disable_MSIPLLFAST()` `LL_RCC_Enable_MSIPLLFAST()` `LL_RCC_MSI_ConfigHWAutoCalib()` `LL_RCC_MSI_IsEnabledMSIPLLFAST()`
CR	MSIPLLSEL	`LL_RCC_GetMSIPLLMode()` `LL_RCC_MSI_ConfigHWAutoCalib()` `LL_RCC_SetMSIPLLMode()`
CR	MSISON	`LL_RCC_MSIS_Disable()` `LL_RCC_MSIS_Enable()` `LL_RCC_MSIS_IsEnabled()`
CR	MSISRDY	`LL_RCC_MSIS_IsReady()`
CR	PLL1ON	`LL_RCC_PLL1_Enable()`
CR	PLL1RDY	`LL_RCC_PLL1_IsReady()`
CR	PLL2ON	`LL_RCC_PLL2_Disable()` `LL_RCC_PLL2_Enable()`
CR	PLL2RDY	`LL_RCC_PLL2_IsReady()`
CR	PLL3ON	`LL_RCC_PLL3_Disable()` `LL_RCC_PLL3_Enable()`
CR	PLL3RDY	`LL_RCC_PLL3_IsReady()`
CR	PLLON	`LL_RCC_PLL1_Disable()`
CR	PRIV	`LL_RCC_DisablePrivilegedMode()` `LL_RCC_IsEnabledPrivilegedMode()`
CR	SHSION	`LL_RCC_SHSI_Disable()` `LL_RCC_SHSI_Enable()` `LL_RCC_SHSI_IsEnabled()`
CR	SHSIRDY	`LL_RCC_SHSI_IsReady()`
CRRCR	HSI48CAL	`LL_RCC_HSI48_GetCalibration()`
CSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
CSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
CSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
CSR	MSIKSRANGE	`LL_RCC_MSIK_GetRangeAfterStandby()` `LL_RCC_MSIK_SetRangeAfterStandby()`
CSR	MSISSRANGE	`LL_RCC_MSIS_GetRangeAfterStandby()` `LL_RCC_MSIS_SetRangeAfterStandby()`
CSR	OBLRSTF	`LL_RCC_IsActiveFlag_OBLRST()`
CSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
CSR	RMVF	`LL_RCC_ClearResetFlags()`
CSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
CSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`
ICSC3R	HSITRIM	`LL_RCC_HSI_GetCalibTrimming()`
ICSCR1	MSIBIAS	`LL_RCC_MSI_GetMSIBiasMode()` `LL_RCC_MSI_SetMSIBiasMode()`
ICSCR1	MSICALx	`LL_RCC_MSI_GetCalibration()`
ICSCR1	MSIKRANGE	`LL_RCC_MSIK_GetRange()` `LL_RCC_MSIK_SetRange()` `LL_RCC_MSIK_SwitchRange()`
ICSCR1	MSIRGSEL	`LL_RCC_MSIK_SwitchRange()` `LL_RCC_MSIS_SwitchRange()` `LL_RCC_MSI_EnableRangeSelection()` `LL_RCC_MSI_IsEnabledRangeSelect()`
ICSCR1	MSISRANGE	`LL_RCC_MSIS_GetRange()` `LL_RCC_MSIS_SetRange()` `LL_RCC_MSIS_SwitchRange()`
ICSCR2	MSITRIMx	`LL_RCC_MSI_GetCalibTrimming()` `LL_RCC_MSI_SetCalibTrimming()`
ICSCR3	HSICAL	`LL_RCC_HSI_GetCalibration()`
ICSCR3	HSITRIM	`LL_RCC_HSI_SetCalibTrimming()`
PLL1CFGR	PLL1FRACEN	`LL_RCC_PLL1FRACN_Disable()` `LL_RCC_PLL1FRACN_Enable()` `LL_RCC_PLL1FRACN_IsEnabled()`
PLL1CFGR	PLL1M	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetDivider()` `LL_RCC_PLL1_SetDivider()`
PLL1CFGR	PLL1MBOOST	`LL_RCC_GetPll1EPodPrescaler()` `LL_RCC_PLL1_Config()` `LL_RCC_SetPll1EPodPrescaler()`
PLL1CFGR	PLL1N	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetN()` `LL_RCC_PLL1_SetN()`
PLL1CFGR	PLL1P	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_GetP()` `LL_RCC_PLL1_SetP()`
PLL1CFGR	PLL1PEN	`LL_RCC_PLL1_DisableDomain_SAI()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_SAI()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_SAI()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1Q	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_GetQ()`
PLL1CFGR	PLL1QEN	`LL_RCC_PLL1_DisableDomain_48M()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_48M()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_48M()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1R	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_SYS()`
PLL1CFGR	PLL1REN	`LL_RCC_PLL1_DisableDomain_SYS()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_SYS()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_SYS()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1RGE	`LL_RCC_PLL1_SetVCOInputRange()`
PLL1CFGR	PLL1SRC	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetMainSource()` `LL_RCC_PLL1_SetMainSource()`
PLL1DIVR	PLL1Q	`LL_RCC_PLL1_SetQ()`
PLL1DIVR	PLL1R	`LL_RCC_PLL1_GetR()` `LL_RCC_PLL1_SetR()`
PLL1FRACR	PLL1FRACN	`LL_RCC_PLL1_GetFRACN()` `LL_RCC_PLL1_SetFRACN()`
PLL2CFGR	PLL2FRACEN	`LL_RCC_PLL2FRACN_Disable()` `LL_RCC_PLL2FRACN_Enable()` `LL_RCC_PLL2FRACN_IsEnabled()`
PLL2CFGR	PLL2M	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetDivider()` `LL_RCC_PLL2_SetDivider()`
PLL2CFGR	PLL2N	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetN()` `LL_RCC_PLL2_SetN()`
PLL2CFGR	PLL2P	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_GetP()` `LL_RCC_PLL2_SetP()`
PLL2CFGR	PLL2PEN	`LL_RCC_PLL2_DisableDomain_SAI()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_SAI()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_SAI()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2Q	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_GetQ()`
PLL2CFGR	PLL2QEN	`LL_RCC_PLL2_DisableDomain_48M()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_48M()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_48M()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2R	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_SetR()`
PLL2CFGR	PLL2REN	`LL_RCC_PLL2_DisableDomain_ADC()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_ADC()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_ADC()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2RGE	`LL_RCC_PLL2_SetVCOInputRange()`
PLL2CFGR	PLL2SRC	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetSource()` `LL_RCC_PLL2_SetSource()`
PLL2DIVR	PLL2Q	`LL_RCC_PLL2_SetQ()`
PLL2DIVR	PLL2R	`LL_RCC_PLL2_GetR()`
PLL2FRACR	PLL2FRACN	`LL_RCC_PLL2_GetFRACN()` `LL_RCC_PLL2_SetFRACN()`
PLL3CFGR	PLL3FRACEN	`LL_RCC_PLL3FRACN_Disable()` `LL_RCC_PLL3FRACN_Enable()` `LL_RCC_PLL3FRACN_IsEnabled()`
PLL3CFGR	PLL3M	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetDivider()` `LL_RCC_PLL3_SetDivider()`
PLL3CFGR	PLL3N	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetN()` `LL_RCC_PLL3_SetN()`
PLL3CFGR	PLL3P	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_GetP()` `LL_RCC_PLL3_SetP()`
PLL3CFGR	PLL3PEN	`LL_RCC_PLL3_DisableDomain_SAI()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_SAI()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_SAI()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3Q	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_GetQ()`
PLL3CFGR	PLL3QEN	`LL_RCC_PLL3_DisableDomain_48M()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_48M()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_48M()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3R	`LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_SetR()`
PLL3CFGR	PLL3REN	`LL_RCC_PLL3_DisableDomain_HSPI_LTDC()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_HSPI_LTDC()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3RGE	`LL_RCC_PLL3_SetVCOInputRange()`
PLL3CFGR	PLL3SRC	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetSource()` `LL_RCC_PLL3_SetSource()`
PLL3DIVR	PLL3P	`LL_RCC_PLL3_ConfigDomain_SAI()`
PLL3DIVR	PLL3Q	`LL_RCC_PLL3_SetQ()`
PLL3DIVR	PLL3R	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_GetR()`
PLL3FRACR	PLL3FRACN	`LL_RCC_PLL3_GetFRACN()` `LL_RCC_PLL3_SetFRACN()`
PLLC1FGR	PLL1M	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1N	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1P	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1SRC	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC2FGR	PLL2M	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2N	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2P	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2SRC	`LL_RCC_PLL2_ConfigDomain_SAI()`
PRIVCFGR	NSPRIV	`LL_RCC_DisableNSecPrivilegedMode()` `LL_RCC_EnableNSecPrivilegedMode()` `LL_RCC_EnablePrivilegedMode()` `LL_RCC_IsEnabledNSecPrivilegedMode()`
PRIVCFGR	SPRIV	`LL_RCC_DisableSecPrivilegedMode()` `LL_RCC_EnablePrivilegedMode()` `LL_RCC_EnableSecPrivilegedMode()` `LL_RCC_IsEnabledSecPrivilegedMode()`
SECCFGR	CLK48MSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSESEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSI48SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	LSESEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	LSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	MSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL1SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL2SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL3SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PRESCSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	RMVFSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	SYSCLKSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SRDAMR	ADC4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	ADF1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	COMPAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	DAC1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	I2C3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPDMA1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPGPIO1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPUART1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	OPAMPAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	RTCAPBAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	SPI3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	SRAM4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	VREFAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	VREFRST	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`

Register	Bit	Function
AHB1ENR	BKPSRAMEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CORDICEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CRCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DCACHE1EN	`LL_AHB1_GRP1_EnableClock()`
AHB1ENR	DCACHE2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DCACHEEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	DMA2DEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FLASHEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FMACEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GFXMMUEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPU2DEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GTZC1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	JPEGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	MDF1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	RAMCFGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	TSCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1RSTR	CORDICRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	CRCRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	DCACHE2RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	DMA2DRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	FMACRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GFXMMURSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPDMA1RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPU2DRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	JPEGRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	MDF1RSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	RAMCFGRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	TSCRSTR	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1SMENR	BKPSRAMSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	CORDICSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	CRCSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DCACHE2SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DCACHESMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	DMA2DSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	FLASHSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	FMACSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GFXMMUSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GPDMA1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GPU2DSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	GTZC1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	ICACHESMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	JPEGSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	MDF1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	RAMCFGSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	SRAM1SMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB1SMENR	TSCSMEN	`LL_AHB1_GRP1_DisableClockStopSleep()` `LL_AHB1_GRP1_EnableClockStopSleep()` `LL_AHB1_GRP1_IsEnabledClockStopSleep()`
AHB2ENR1	ADC12EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	AESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	DCMI_PSSIEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOCEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIODEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOEEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOFEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOIEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	GPIOJEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	HASHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OCTOSPIMEN	`LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OSPIMEN	`LL_AHB2_GRP1_DisableClock()`
AHB2ENR1	OTFDEC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTFDEC2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGHSPHYEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	OTGHSPHYSMEN	`LL_AHB2_GRP1_EnableClockStopSleep()`
AHB2ENR1	PKAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	RNGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SAESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SDMMC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SDMMC2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SRAM2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR1	SRAM3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR2	FSMCEN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	HSPI1EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	OCTOSPI1EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	OCTOSPI2EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	SRAM5EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()` `LL_AHB2_GRP2_IsEnabledClock()`
AHB2ENR2	SRAM6EN	`LL_AHB2_GRP2_DisableClock()` `LL_AHB2_GRP2_EnableClock()`
AHB2RSTR1	ADC12RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	AESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	DCMI_PSSIRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOCRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIODRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOERST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOFRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOIRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	GPIOJRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	HASHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OCTOSPIMRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTFDEC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTFDEC2RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	OTGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	PKARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	RNGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SAESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SDMMC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR1	SDMMC2RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR2	FSMCRST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	HSPI1RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	OCTOSPI1RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2RSTR2	OCTOSPI2RST	`LL_AHB2_GRP2_ForceReset()` `LL_AHB2_GRP2_ReleaseReset()`
AHB2SMENR1	ADC12SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	AESSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	DCMI_PSSISMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOASMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOBSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOCSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIODSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOESMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOFSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOHSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOISMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	GPIOJSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	HASHSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OSPIMSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTFDEC1SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTFDEC2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTGHSPHYSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	OTGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	PKASMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	RNGSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SAESSMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SDMMC1SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SDMMC2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SRAM2SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR1	SRAM3SMEN	`LL_AHB2_GRP1_DisableClockStopSleep()` `LL_AHB2_GRP1_EnableClockStopSleep()` `LL_AHB2_GRP1_IsEnabledClockStopSleep()`
AHB2SMENR2	FSMCSMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	HSPI1SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	OCTOSPI1SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	OCTOSPI2SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	SRAM5SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB2SMENR2	SRAM6SMEN	`LL_AHB2_GRP2_DisableClockStopSleep()` `LL_AHB2_GRP2_EnableClockStopSleep()` `LL_AHB2_GRP2_IsEnabledClockStopSleep()`
AHB3ENR	ADC4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	ADF1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	GTZC2EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	LPDMA1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	LPGPIO1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	PWREN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	SRAM4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3RSTR	ADC4RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	ADF1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	GTZC2RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	LPDMA1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	LPGPIO1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	PWRRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3SMENR	ADC4SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	ADF1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	DAC1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	GTZC2SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	LPDMA1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	LPGPIO1SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	PWRSMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
AHB3SMENR	SRAM4SMEN	`LL_AHB3_GRP1_DisableClockStopSleep()` `LL_AHB3_GRP1_EnableClockStopSleep()` `LL_AHB3_GRP1_IsEnabledClockStopSleep()`
APB1ENR1	CRSEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART6N	`LL_APB1_GRP1_EnableClock()`
APB1ENR1	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR2	FDCAN1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C4EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C5EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	I2C6EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	LPTIM2EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	UCPD1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1RSTR1	CRSRST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR2	FDCAN1RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C4RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C5RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	I2C6RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	LPTIM2RST	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPD1RST	`LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPDRST	`LL_APB1_GRP2_DisableClock()`
APB1SMENR1	CRSSMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	I2C1SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	I2C2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	SPI2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM3SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM4SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM5SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM6SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	TIM7SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	UART4SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	UART5SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART2SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART3SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR1	USART6SMEN	`LL_APB1_GRP1_DisableClockStopSleep()` `LL_APB1_GRP1_EnableClockStopSleep()` `LL_APB1_GRP1_IsEnabledClockStopSleep()`
APB1SMENR2	FDCAN1SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C4SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C5SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	I2C6SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	LPTIM2SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB1SMENR2	UCPD1SMEN	`LL_APB1_GRP2_DisableClockStopSleep()` `LL_APB1_GRP2_EnableClockStopSleep()` `LL_APB1_GRP2_IsEnabledClockStopSleep()`
APB2ENR	DSIHOSTEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	GFXTIMEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	LTDCEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SAI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SAI2EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USBEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2RSTR	DSIHOSTRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	GFXTIMRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	LTDCRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SAI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SAI2RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USBRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2SMENR	DSIHOSTSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	GFXTIMSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	LTDCSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SAI1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SAI2SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	SPI1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM15SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM16SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM17SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	TIM8SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	USART1SMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB2SMENR	USBSMEN	`LL_APB2_GRP1_DisableClockStopSleep()` `LL_APB2_GRP1_EnableClockStopSleep()` `LL_APB2_GRP1_IsEnabledClockStopSleep()`
APB3ENR	COMPEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	I2C3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPTIM4EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPUART1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	OPAMPEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	RTCAPBEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SPI3EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SYSCFGEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	VREFEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3RSTR	COMPRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	I2C3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPTIM4RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPUART1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	OPAMPRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	RTCAPBRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SPI3RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SYSCFGRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	VREFRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3SMENR	COMPSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	I2C3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM1SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPTIM4SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	LPUART1SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	OPAMPSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	RTCAPBSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	SPI3SMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	SYSCFGSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
APB3SMENR	VREFSMEN	`LL_APB3_GRP1_DisableClockStopSleep()` `LL_APB3_GRP1_EnableClockStopSleep()` `LL_APB3_GRP1_IsEnabledClockStopSleep()`
BDCR	BDRST	`LL_RCC_ForceBackupDomainReset()` `LL_RCC_ReleaseBackupDomainReset()`
BDCR	LSCOEN	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_Disable()` `LL_RCC_LSCO_Enable()`
BDCR	LSCOSEL	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_GetSource()` `LL_RCC_LSCO_SetSource()`
BDCR	LSEBYP	`LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()`
BDCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
BDCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
BDCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
BDCR	LSEGFON	`LL_RCC_LSE_DisableGlitchFilter()` `LL_RCC_LSE_EnableGlitchFilter()` `LL_RCC_LSE_IsGlitchFilterEnabled()`
BDCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
BDCR	LSERDY	`LL_RCC_LSE_IsReady()`
BDCR	LSESYSEN	`LL_RCC_LSE_DisablePropagation()` `LL_RCC_LSE_EnablePropagation()`
BDCR	LSESYSRDY	`LL_RCC_LSE_IsPropagationReady()`
BDCR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
BDCR	LSIPREDIV	`LL_RCC_LSI_GetPrescaler()` `LL_RCC_LSI_SetPrescaler()`
BDCR	LSIRDY	`LL_RCC_LSI_IsReady()`
BDCR	RCC_BDCR_LSEBYP	`LL_RCC_LSE_IsBypassed()`
BDCR	RCC_BDCR_LSESYSEN	`LL_RCC_LSE_IsPropagationEnabled()`
BDCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
BDCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`
CCIPR1	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR1	I2C1SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	I2C2SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	I2C4SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR1	ICLKSEL	`LL_RCC_GetSDMMCClockSource()` `LL_RCC_GetUSBClockSource()` `LL_RCC_SetSDMMCClockSource()` `LL_RCC_SetUSBClockSource()`
CCIPR1	LPTIM2SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR1	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()`
CCIPR1	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI2SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SYSTICKSEL	`LL_RCC_GetSystickClockSource()` `LL_RCC_SetSystickClockSource()`
CCIPR1	TIMICSEL	`LL_RCC_GetTIMICClockSource()` `LL_RCC_SetTIMICClockSource()`
CCIPR1	UART4SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART5SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	USART1SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART2SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART3SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR2	MDF1SEL	`LL_RCC_GetMDF1ClockSource()`
CCIPR2	OSPISEL	`LL_RCC_GetOCTOSPIClockSource()` `LL_RCC_SetOCTOSPIClockSource()`
CCIPR2	RNGSEL	`LL_RCC_GetRNGClockSource()` `LL_RCC_SetRNGClockSource()`
CCIPR2	SAESSEL	`LL_RCC_GetSAESClockSource()` `LL_RCC_SetSAESClockSource()`
CCIPR2	SAI1SEL	`LL_RCC_GetSAIClockSource()` `LL_RCC_SetSAIClockSource()`
CCIPR2	SAI2SEL	`LL_RCC_GetSAIClockSource()` `LL_RCC_SetSAIClockSource()`
CCIPR2	SDMMCSEL	`LL_RCC_GetSDMMCKernelClockSource()` `LL_RCC_SetSDMMCKernelClockSource()`
CCIPR2	USART6SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR3	ADCDACSEL	`LL_RCC_SetADCDACClockSource()`
CCIPR3	ADF1SEL	`LL_RCC_GetADF1ClockSource()` `LL_RCC_SetADF1ClockSource()`
CCIPR3	DAC1SEL	`LL_RCC_GetDAC1ClockSource()` `LL_RCC_SetDAC1ClockSource()`
CCIPR3	I2C3SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR3	LPTIM2SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR3	LPTIM34SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR3	LPUART1SEL	`LL_RCC_SetLPUARTClockSource()`
CCIPR3	MDF1SEL	`LL_RCC_SetMDF1ClockSource()`
CCIPR3	SPI3SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CFGR1	MCOPRE	`LL_RCC_ConfigMCO()`
CFGR1	MCOSEL	`LL_RCC_ConfigMCO()`
CFGR1	STOPKERWUCK	`LL_RCC_GetKerClkAfterWakeFromStop()` `LL_RCC_SetKerClkAfterWakeFromStop()`
CFGR1	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR1	SW	`LL_RCC_SetSysClkSource()`
CFGR1	SWS	`LL_RCC_GetSysClkSource()`
CFGR2	AHB1DIS	`LL_AHB1_GRP1_DisableBusClock()` `LL_AHB1_GRP1_EnableBusClock()` `LL_AHB1_GRP1_IsEnabledBusClock()`
CFGR2	AHB2DIS1	`LL_AHB2_GRP1_DisableBusClock()` `LL_AHB2_GRP1_EnableBusClock()` `LL_AHB2_GRP1_IsEnabledBusClock()`
CFGR2	AHB2DIS2	`LL_AHB2_GRP2_DisableBusClock()` `LL_AHB2_GRP2_EnableBusClock()` `LL_AHB2_GRP2_IsEnabledBusClock()`
CFGR2	AHB3DIS	`LL_AHB3_GRP1_DisableBusClock()`
CFGR2	APB1DIS	`LL_APB1_GRP1_DisableBusClock()` `LL_APB1_GRP1_EnableBusClock()` `LL_APB1_GRP1_IsEnabledBusClock()`
CFGR2	APB2DIS	`LL_APB2_GRP1_DisableBusClock()` `LL_APB2_GRP1_EnableBusClock()` `LL_APB2_GRP1_IsEnabledBusClock()`
CFGR2	APB3DIS	`LL_APB3_GRP1_DisableBusClock()`
CFGR2	HPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAHBPrescaler()` `LL_RCC_SetAHBPrescaler()`
CFGR2	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
CFGR2	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
CFGR3	AHB3DIS	`LL_AHB3_GRP1_EnableBusClock()` `LL_AHB3_GRP1_IsEnabledBusClock()`
CFGR3	APB3DIS	`LL_APB3_GRP1_EnableBusClock()` `LL_APB3_GRP1_IsEnabledBusClock()`
CFGR3	PPRE3	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB3Prescaler()`
CICR	CSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	CSSF	`LL_RCC_IsActiveFlag()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSERDYF	`LL_RCC_IsActiveFlag()`
CICR	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	HSI48RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSI48RDY()`
CICR	HSI48RDYF	`LL_RCC_IsActiveFlag()`
CICR	HSI48RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	HSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSERDYF	`LL_RCC_IsActiveFlag()`
CICR	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	LSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	MSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_MSIKRDY()`
CICR	MSIKRDYF	`LL_RCC_IsActiveFlag()`
CICR	MSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	MSISRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_MSIRDY()`
CICR	MSISRDYF	`LL_RCC_IsActiveFlag()`
CICR	MSISRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL1RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL1RDY()`
CICR	PLL1RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL1RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL2RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL2RDY()`
CICR	PLL2RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL2RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	PLL3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL3RDY()`
CICR	PLL3RDYF	`LL_RCC_IsActiveFlag()`
CICR	PLL3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CICR	SHSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_SHSIRDY()`
CICR	SHSIRDYF	`LL_RCC_IsActiveFlag()`
CICR	SHSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_EnableIT()`
CIER	HSERDYIE	`LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSI48RDYIE	`LL_RCC_DisableIT_HSI48RDY()` `LL_RCC_EnableIT_HSI48RDY()` `LL_RCC_IsEnabledIT_HSI48RDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSERDYIE	`LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	MSIKRDYIE	`LL_RCC_DisableIT_MSIKRDY()` `LL_RCC_EnableIT_MSIKRDY()` `LL_RCC_IsEnabledIT_MSIKRDY()`
CIER	MSIRDYIE	`LL_RCC_EnableIT_MSIRDY()` `LL_RCC_IsEnabledIT_MSIRDY()`
CIER	MSISRDYIE	`LL_RCC_DisableIT_MSIRDY()`
CIER	PLL1RDYIE	`LL_RCC_DisableIT_PLL1RDY()` `LL_RCC_EnableIT_PLL1RDY()` `LL_RCC_IsEnabledIT_PLL1RDY()`
CIER	PLL2RDYIE	`LL_RCC_DisableIT_PLL2RDY()` `LL_RCC_EnableIT_PLL2RDY()` `LL_RCC_IsEnabledIT_PLL2RDY()`
CIER	PLL3RDYIE	`LL_RCC_DisableIT_PLL3RDY()` `LL_RCC_EnableIT_PLL3RDY()` `LL_RCC_IsEnabledIT_PLL3RDY()`
CIER	SHSIRDYIE	`LL_RCC_DisableIT_SHSIRDY()` `LL_RCC_EnableIT_SHSIRDY()` `LL_RCC_IsEnabledIT_SHSIRDY()`
CIFR	CSSF	`LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSI48RDYF	`LL_RCC_IsActiveFlag_HSI48RDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	MSIKRDYF	`LL_RCC_IsActiveFlag_MSIKRDY()`
CIFR	MSISRDYF	`LL_RCC_IsActiveFlag_MSIRDY()`
CIFR	PLL1RDYF	`LL_RCC_IsActiveFlag_PLL1RDY()`
CIFR	PLL2RDYF	`LL_RCC_IsActiveFlag_PLL2RDY()`
CIFR	PLL3RDYF	`LL_RCC_IsActiveFlag_PLL3RDY()`
CIFR	SHSIRDYF	`LL_RCC_IsActiveFlag_SHSIRDY()`
CR	CSSON	`LL_RCC_HSE_EnableCSS()`
CR	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetClockMode()` `LL_RCC_HSE_SetClockMode()`
CR	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR	HSERDY	`LL_RCC_HSE_IsReady()`
CR	HSI48ON	`LL_RCC_HSI48_Disable()` `LL_RCC_HSI48_Enable()` `LL_RCC_HSI48_IsEnabled()`
CR	HSI48RDY	`LL_RCC_HSI48_IsReady()`
CR	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR	HSION	`LL_RCC_HSI_Disable()` `LL_RCC_HSI_Enable()` `LL_RCC_HSI_IsEnabled()`
CR	HSIRDY	`LL_RCC_HSI_IsReady()`
CR	MSIKERON	`LL_RCC_MSIK_DisableInStopMode()` `LL_RCC_MSIK_EnableInStopMode()` `LL_RCC_MSIK_IsEnabledInStopMode()`
CR	MSIKON	`LL_RCC_MSIK_Disable()` `LL_RCC_MSIK_Enable()` `LL_RCC_MSIK_IsEnabled()`
CR	MSIKRDY	`LL_RCC_MSIK_IsReady()`
CR	MSIPLLEN	`LL_RCC_IsEnabledPLLMode()` `LL_RCC_MSI_DisablePLLMode()` `LL_RCC_MSI_EnablePLLMode()`
CR	MSIPLLFAST	`LL_RCC_Disable_MSIPLLFAST()` `LL_RCC_Enable_MSIPLLFAST()` `LL_RCC_MSI_ConfigHWAutoCalib()` `LL_RCC_MSI_IsEnabledMSIPLLFAST()`
CR	MSIPLLSEL	`LL_RCC_GetMSIPLLMode()` `LL_RCC_MSI_ConfigHWAutoCalib()` `LL_RCC_SetMSIPLLMode()`
CR	MSISON	`LL_RCC_MSIS_Disable()` `LL_RCC_MSIS_Enable()` `LL_RCC_MSIS_IsEnabled()`
CR	MSISRDY	`LL_RCC_MSIS_IsReady()`
CR	PLL1ON	`LL_RCC_PLL1_Enable()`
CR	PLL1RDY	`LL_RCC_PLL1_IsReady()`
CR	PLL2ON	`LL_RCC_PLL2_Disable()` `LL_RCC_PLL2_Enable()`
CR	PLL2RDY	`LL_RCC_PLL2_IsReady()`
CR	PLL3ON	`LL_RCC_PLL3_Disable()` `LL_RCC_PLL3_Enable()`
CR	PLL3RDY	`LL_RCC_PLL3_IsReady()`
CR	PLLON	`LL_RCC_PLL1_Disable()`
CR	PRIV	`LL_RCC_DisablePrivilegedMode()` `LL_RCC_IsEnabledPrivilegedMode()`
CR	SHSION	`LL_RCC_SHSI_Disable()` `LL_RCC_SHSI_Enable()` `LL_RCC_SHSI_IsEnabled()`
CR	SHSIRDY	`LL_RCC_SHSI_IsReady()`
CRRCR	HSI48CAL	`LL_RCC_HSI48_GetCalibration()`
CSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
CSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
CSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
CSR	MSIKSRANGE	`LL_RCC_MSIK_GetRangeAfterStandby()` `LL_RCC_MSIK_SetRangeAfterStandby()`
CSR	MSISSRANGE	`LL_RCC_MSIS_GetRangeAfterStandby()` `LL_RCC_MSIS_SetRangeAfterStandby()`
CSR	OBLRSTF	`LL_RCC_IsActiveFlag_OBLRST()`
CSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
CSR	RMVF	`LL_RCC_ClearResetFlags()`
CSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
CSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`
ICSC3R	HSITRIM	`LL_RCC_HSI_GetCalibTrimming()`
ICSCR1	MSIBIAS	`LL_RCC_MSI_GetMSIBiasMode()` `LL_RCC_MSI_SetMSIBiasMode()`
ICSCR1	MSICALx	`LL_RCC_MSI_GetCalibration()`
ICSCR1	MSIKRANGE	`LL_RCC_MSIK_GetRange()` `LL_RCC_MSIK_SetRange()` `LL_RCC_MSIK_SwitchRange()`
ICSCR1	MSIRGSEL	`LL_RCC_MSIK_SwitchRange()` `LL_RCC_MSIS_SwitchRange()` `LL_RCC_MSI_EnableRangeSelection()` `LL_RCC_MSI_IsEnabledRangeSelect()`
ICSCR1	MSISRANGE	`LL_RCC_MSIS_GetRange()` `LL_RCC_MSIS_SetRange()` `LL_RCC_MSIS_SwitchRange()`
ICSCR2	MSITRIMx	`LL_RCC_MSI_GetCalibTrimming()` `LL_RCC_MSI_SetCalibTrimming()`
ICSCR3	HSICAL	`LL_RCC_HSI_GetCalibration()`
ICSCR3	HSITRIM	`LL_RCC_HSI_SetCalibTrimming()`
PLL1CFGR	PLL1FRACEN	`LL_RCC_PLL1FRACN_Disable()` `LL_RCC_PLL1FRACN_Enable()` `LL_RCC_PLL1FRACN_IsEnabled()`
PLL1CFGR	PLL1M	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetDivider()` `LL_RCC_PLL1_SetDivider()`
PLL1CFGR	PLL1MBOOST	`LL_RCC_GetPll1EPodPrescaler()` `LL_RCC_PLL1_Config()` `LL_RCC_SetPll1EPodPrescaler()`
PLL1CFGR	PLL1N	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetN()` `LL_RCC_PLL1_SetN()`
PLL1CFGR	PLL1P	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_GetP()` `LL_RCC_PLL1_SetP()`
PLL1CFGR	PLL1PEN	`LL_RCC_PLL1_DisableDomain_SAI()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_SAI()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_SAI()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1Q	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_GetQ()`
PLL1CFGR	PLL1QEN	`LL_RCC_PLL1_DisableDomain_48M()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_48M()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_48M()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1R	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_SYS()`
PLL1CFGR	PLL1REN	`LL_RCC_PLL1_DisableDomain_SYS()` `LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_EnableDomain_SYS()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_IsEnabledDomain_SYS()` `LL_RCC_PLL1_IsOutputEnabled()`
PLL1CFGR	PLL1RGE	`LL_RCC_PLL1_SetVCOInputRange()`
PLL1CFGR	PLL1SRC	`LL_RCC_PLL1_Config()` `LL_RCC_PLL1_ConfigDomain_48M()` `LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetMainSource()` `LL_RCC_PLL1_SetMainSource()`
PLL1DIVR	PLL1Q	`LL_RCC_PLL1_SetQ()`
PLL1DIVR	PLL1R	`LL_RCC_PLL1_GetR()` `LL_RCC_PLL1_SetR()`
PLL1FRACR	PLL1FRACN	`LL_RCC_PLL1_GetFRACN()` `LL_RCC_PLL1_SetFRACN()`
PLL2CFGR	PLL2FRACEN	`LL_RCC_PLL2FRACN_Disable()` `LL_RCC_PLL2FRACN_Enable()` `LL_RCC_PLL2FRACN_IsEnabled()`
PLL2CFGR	PLL2M	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetDivider()` `LL_RCC_PLL2_SetDivider()`
PLL2CFGR	PLL2N	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetN()` `LL_RCC_PLL2_SetN()`
PLL2CFGR	PLL2P	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_GetP()` `LL_RCC_PLL2_SetP()`
PLL2CFGR	PLL2PEN	`LL_RCC_PLL2_DisableDomain_SAI()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_SAI()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_SAI()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2Q	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_GetQ()`
PLL2CFGR	PLL2QEN	`LL_RCC_PLL2_DisableDomain_48M()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_48M()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_48M()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2R	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_SetR()`
PLL2CFGR	PLL2REN	`LL_RCC_PLL2_DisableDomain_ADC()` `LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_EnableDomain_ADC()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_IsEnabledDomain_ADC()` `LL_RCC_PLL2_IsOutputEnabled()`
PLL2CFGR	PLL2RGE	`LL_RCC_PLL2_SetVCOInputRange()`
PLL2CFGR	PLL2SRC	`LL_RCC_PLL2_Config()` `LL_RCC_PLL2_ConfigDomain_48M()` `LL_RCC_PLL2_ConfigDomain_ADC()` `LL_RCC_PLL2_GetSource()` `LL_RCC_PLL2_SetSource()`
PLL2DIVR	PLL2Q	`LL_RCC_PLL2_SetQ()`
PLL2DIVR	PLL2R	`LL_RCC_PLL2_GetR()`
PLL2FRACR	PLL2FRACN	`LL_RCC_PLL2_GetFRACN()` `LL_RCC_PLL2_SetFRACN()`
PLL3CFGR	PLL3FRACEN	`LL_RCC_PLL3FRACN_Disable()` `LL_RCC_PLL3FRACN_Enable()` `LL_RCC_PLL3FRACN_IsEnabled()`
PLL3CFGR	PLL3M	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetDivider()` `LL_RCC_PLL3_SetDivider()`
PLL3CFGR	PLL3N	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetN()` `LL_RCC_PLL3_SetN()`
PLL3CFGR	PLL3P	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_GetP()` `LL_RCC_PLL3_SetP()`
PLL3CFGR	PLL3PEN	`LL_RCC_PLL3_DisableDomain_SAI()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_SAI()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_SAI()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3Q	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_GetQ()`
PLL3CFGR	PLL3QEN	`LL_RCC_PLL3_DisableDomain_48M()` `LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableDomain_48M()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsEnabledDomain_48M()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3R	`LL_RCC_PLL3_SetR()`
PLL3CFGR	PLL3REN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_IsOutputEnabled()`
PLL3CFGR	PLL3RGE	`LL_RCC_PLL3_SetVCOInputRange()`
PLL3CFGR	PLL3SRC	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_ConfigDomain_48M()` `LL_RCC_PLL3_ConfigDomain_SAI()` `LL_RCC_PLL3_GetSource()` `LL_RCC_PLL3_SetSource()`
PLL3DIVR	PLL3P	`LL_RCC_PLL3_ConfigDomain_SAI()`
PLL3DIVR	PLL3Q	`LL_RCC_PLL3_SetQ()`
PLL3DIVR	PLL3R	`LL_RCC_PLL3_Config()` `LL_RCC_PLL3_GetR()`
PLL3FRACR	PLL3FRACN	`LL_RCC_PLL3_GetFRACN()` `LL_RCC_PLL3_SetFRACN()`
PLLC1FGR	PLL1M	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1N	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1P	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC1FGR	PLL1SRC	`LL_RCC_PLL1_ConfigDomain_SAI()`
PLLC2FGR	PLL2M	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2N	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2P	`LL_RCC_PLL2_ConfigDomain_SAI()`
PLLC2FGR	PLL2SRC	`LL_RCC_PLL2_ConfigDomain_SAI()`
PRIVCFGR	NSPRIV	`LL_RCC_DisableNSecPrivilegedMode()` `LL_RCC_EnableNSecPrivilegedMode()` `LL_RCC_EnablePrivilegedMode()` `LL_RCC_IsEnabledNSecPrivilegedMode()`
PRIVCFGR	SPRIV	`LL_RCC_DisableSecPrivilegedMode()` `LL_RCC_EnablePrivilegedMode()` `LL_RCC_EnableSecPrivilegedMode()` `LL_RCC_IsEnabledSecPrivilegedMode()`
SECCFGR	CLK48MSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSESEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSI48SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	HSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	LSESEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	LSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	MSISEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL1SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL2SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PLL3SEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	PRESCSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	RMVFSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SECCFGR	SYSCLKSEC	`LL_RCC_ConfigSecure()` `LL_RCC_GetConfigSecure()`
SRDAMR	ADC4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	ADF1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	COMPAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	DAC1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	I2C3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPDMA1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPGPIO1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPTIM4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	LPUART1AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	OPAMPAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	RTCAPBAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	SPI3AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	SRAM4AMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	VREFAMEN	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`
SRDAMR	VREFRST	`LL_SRDAMR_GRP1_DisableAutonomousClock()` `LL_SRDAMR_GRP1_EnableAutonomousClock()` `LL_SRDAMR_GRP1_IsEnabledAutonomousClock()`