LL RNG Constants

Clock Error Detection

group RNG_LL_CED

Defines

LL_RNG_CED_ENABLE 0x00000000U

Clock error detection enabled

LL_RNG_CED_DISABLE RNG_CR_CED

Clock error detection disabled

Auto reset disable

group RNG_LL_ARDIS

Defines

LL_RNG_ARDIS_ENABLE 0x00000000U

ARDIS enabled automatic reset to clear SECS bit

LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS

ARDIS disabled no automatic reset to clear SECS bit

Value used to configure an internal

group RNG_LL_Clock_Divider_Factor

programmable divider acting on the incoming RNG clock

Defines

LL_RNG_CLKDIV_BY_1 (0x00000000UL)

No clock division

LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)

2 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)

4 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

8 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)

16 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

32 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

64 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

128 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)

256 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)

512 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)

1024 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

2048 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)

4096 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

8192 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

16384 RNG clock cycles per internal RNG clock

LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

32768 RNG clock cycles per internal RNG clock

NIST Compliance configuration

group RNG_LL_NIST_Compliance

Defines

LL_RNG_NIST_COMPLIANT (0x00000000UL)

Default NIST compliant configuration

LL_RNG_CUSTOM_NIST (RNG_CR_NISTC)

Custom NIST configuration

Get Flags Defines

group RNG_LL_EC_GET_FLAG

Flags defines which can be used with LL_RNG_ReadReg function.

Defines

LL_RNG_SR_DRDY RNG_SR_DRDY

Register contains valid random data

LL_RNG_SR_CECS RNG_SR_CECS

Clock error current status

LL_RNG_SR_SECS RNG_SR_SECS

Seed error current status

LL_RNG_SR_CEIS RNG_SR_CEIS

Clock error interrupt status

LL_RNG_SR_SEIS RNG_SR_SEIS

Seed error interrupt status

Oscillator Sources Defines

group RNG_LL_NSCR_Oscillator_Sources

Defines

LL_RNG_OSC_1 RNG_NSCR_EN_OSC1
LL_RNG_OSC_2 RNG_NSCR_EN_OSC2
LL_RNG_OSC_3 RNG_NSCR_EN_OSC3
LL_RNG_OSC_4 RNG_NSCR_EN_OSC4
LL_RNG_OSC_5 RNG_NSCR_EN_OSC5
LL_RNG_OSC_6 RNG_NSCR_EN_OSC6

Noise Sources Ports Defines

group RNG_LL_NSCR_Noise_Sources_Ports

Defines

LL_RNG_NOISE_SRC_1 (0x01UL)
LL_RNG_NOISE_SRC_2 (0x02UL)
LL_RNG_NOISE_SRC_3 (0x04UL)

IT Defines

group RNG_LL_EC_IT

Defines

LL_RNG_CR_IE RNG_CR_IE

RNG Interrupt enable