Reference Manual to LL API cross reference ¶

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for SPI registers

Register	Bit	Function
AUTOCR	TRIGEN	`LL_SPI_Disable_SelectedTrigger()` `LL_SPI_Enable_SelectedTrigger()` `LL_SPI_IsEnabled_SelectedTrigger()`
AUTOCR	TRIGPOL	`LL_SPI_GetTriggerPolarity()` `LL_SPI_SetAutonomousConfig()` `LL_SPI_SetTriggerPolarity()`
AUTOCR	TRIGSEL	`LL_SPI_GetSelectedTrigger()` `LL_SPI_SetAutonomousConfig()` `LL_SPI_SetSelectedTrigger()`
CFG1	BPASS	`LL_SPI_GetBaudRatePrescaler()` `LL_SPI_SetBaudRatePrescaler()` `LL_SPI_SetConfig()`
CFG1	CRCEN	`LL_SPI_DisableCRC()` `LL_SPI_EnableCRC()` `LL_SPI_IsEnabledCRC()`
CFG1	CRCSIZE	`LL_SPI_GetCRCWidth()` `LL_SPI_SetCRCWidth()`
CFG1	DSIZE	`LL_SPI_GetDataWidth()` `LL_SPI_SetConfig()` `LL_SPI_SetDataWidth()`
CFG1	FTHLV	`LL_SPI_GetFIFOThreshold()` `LL_SPI_SetFIFOThreshold()`
CFG1	MBR	`LL_SPI_GetBaudRatePrescaler()` `LL_SPI_SetBaudRatePrescaler()` `LL_SPI_SetConfig()`
CFG1	RXDMAEN	`LL_SPI_DisableDMAReq_RX()` `LL_SPI_EnableDMAReq_RX()` `LL_SPI_IsEnabledDMAReq_RX()`
CFG1	TXDMAEN	`LL_SPI_DisableDMAReq_TX()` `LL_SPI_EnableDMAReq_TX()` `LL_SPI_IsEnabledDMAReq_TX()`
CFG1	UDRCFG	`LL_SPI_GetUDRConfiguration()` `LL_SPI_SetUDRConfiguration()`
CFG2	AFCNTR	`LL_SPI_DisableGPIOControl()` `LL_SPI_EnableGPIOControl()` `LL_SPI_IsEnabledGPIOControl()`
CFG2	COMM	`LL_SPI_GetTransferDirection()` `LL_SPI_IsHalfDuplexDirection()` `LL_SPI_SetConfig()` `LL_SPI_SetTransferDirection()`
CFG2	CPHA	`LL_SPI_GetClockPhase()` `LL_SPI_SetClockPhase()` `LL_SPI_SetConfig()`
CFG2	CPOL	`LL_SPI_GetClockPolarity()` `LL_SPI_SetClockPolarity()` `LL_SPI_SetConfig()`
CFG2	IOSWP	`LL_SPI_DisableMosiMisoSwap()` `LL_SPI_EnableMosiMisoSwap()` `LL_SPI_IsEnabledMosiMisoSwap()`
CFG2	LSBFRST	`LL_SPI_GetTransferBitOrder()` `LL_SPI_SetConfig()` `LL_SPI_SetTransferBitOrder()`
CFG2	MASTER	`LL_SPI_GetMode()` `LL_SPI_SetConfig()` `LL_SPI_SetMode()`
CFG2	MIDI	`LL_SPI_SetInterDataIdleness()`
CFG2	MSSI	`LL_SPI_GetMasterSSIdleness()` `LL_SPI_GetNSSConfig()` `LL_SPI_SetMasterSSIdleness()` `LL_SPI_SetNSSConfig()`
CFG2	RDIOM	`LL_SPI_DisableReadyPin()` `LL_SPI_EnableReadyPin()` `LL_SPI_IsEnabledReadyPin()`
CFG2	RDIOP	`LL_SPI_GetReadyPinPolarity()` `LL_SPI_SetReadyPinPolarity()`
CFG2	SP	`LL_SPI_GetStandard()` `LL_SPI_SetStandard()`
CFG2	SSIOP	`LL_SPI_GetNSSConfig()` `LL_SPI_GetNSSPolarity()` `LL_SPI_SetNSSConfig()` `LL_SPI_SetNSSPolarity()`
CFG2	SSM	`LL_SPI_GetNSSMode()` `LL_SPI_SetNSSMode()`
CFG2	SSOE	`LL_SPI_GetNSSMode()` `LL_SPI_SetNSSMode()`
CFG2	SSOM	`LL_SPI_DisableNSSPulseMgt()` `LL_SPI_EnableNSSPulseMgt()` `LL_SPI_GetNSSConfig()` `LL_SPI_IsEnabledNSSPulse()` `LL_SPI_SetNSSConfig()`
CR1	CRC33_17	`LL_SPI_DisableFullSizeCRC()` `LL_SPI_EnableFullSizeCRC()` `LL_SPI_IsEnabledFullSizeCRC()`
CR1	CSTART	`LL_SPI_IsActiveMasterTransfer()` `LL_SPI_StartMasterTransfer()`
CR1	CSUSP	`LL_SPI_SuspendMasterTransfer()`
CR1	HDDIR	`LL_SPI_GetHalfDuplexDirection()` `LL_SPI_SetHalfDuplexDirection()`
CR1	IOLOCK	`LL_SPI_EnableIOLock()` `LL_SPI_IsEnabledIOLock()`
CR1	MASRX	`LL_SPI_DisableMasterRxAutoSuspend()` `LL_SPI_EnableMasterRxAutoSuspend()` `LL_SPI_IsEnabledMasterRxAutoSuspend()`
CR1	RCRCINI	`LL_SPI_GetRxCRCInitPattern()` `LL_SPI_SetCRCInitPattern()` `LL_SPI_SetRxCRCInitPattern()`
CR1	SPE	`LL_SPI_Disable()` `LL_SPI_Enable()` `LL_SPI_IsEnabled()`
CR1	SSI	`LL_SPI_GetInternalSSLevel()` `LL_SPI_SetConfig()` `LL_SPI_SetInternalSSLevel()`
CR1	TCRCINI	`LL_SPI_GetTxCRCInitPattern()` `LL_SPI_SetCRCInitPattern()` `LL_SPI_SetTxCRCInitPattern()`
CR2	TSIZE	`LL_SPI_GetTransferSize()` `LL_SPI_SetTransferSize()`
CRCPOLY	CRCPOLY	`LL_SPI_GetCRCPolynomial()` `LL_SPI_SetCRCPolynomial()`
IER	CRCEIE	`LL_SPI_DisableIT_CRCERR()` `LL_SPI_EnableIT_CRCERR()` `LL_SPI_IsEnabledIT_CRCERR()`
IER	DXPIE	`LL_SPI_DisableIT_DXP()` `LL_SPI_EnableIT_DXP()` `LL_SPI_IsEnabledIT_DXP()`
IER	EOTIE	`LL_SPI_DisableIT_EOT()` `LL_SPI_EnableIT_EOT()` `LL_SPI_IsEnabledIT_EOT()`
IER	MODFIE	`LL_SPI_DisableIT_MODF()` `LL_SPI_EnableIT_MODF()` `LL_SPI_IsEnabledIT_MODF()`
IER	OVRIE	`LL_SPI_DisableIT_OVR()` `LL_SPI_EnableIT_OVR()` `LL_SPI_IsEnabledIT_OVR()`
IER	RXPIE	`LL_SPI_DisableIT_RXP()` `LL_SPI_EnableIT_RXP()` `LL_SPI_IsEnabledIT_RXP()`
IER	SPI_IER_CRCEIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_DXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_EOTIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_MODFIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_OVRIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_RXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TIFREIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TXTFIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_UDRIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	TIFREIE	`LL_SPI_DisableIT_FRE()` `LL_SPI_EnableIT_FRE()` `LL_SPI_IsEnabledIT_FRE()`
IER	TXPIE	`LL_SPI_DisableIT_TXP()` `LL_SPI_EnableIT_TXP()` `LL_SPI_IsEnabledIT_TXP()`
IER	TXTFIE	`LL_SPI_DisableIT_TXTF()` `LL_SPI_EnableIT_TXTF()` `LL_SPI_IsEnabledIT_TXTF()`
IER	UDRIE	`LL_SPI_DisableIT_UDR()` `LL_SPI_EnableIT_UDR()` `LL_SPI_IsEnabledIT_UDR()`
IFCR	CRCEC	`LL_SPI_ClearFlag_CRCERR()`
IFCR	EOTC	`LL_SPI_ClearFlag_EOT()`
IFCR	MODFC	`LL_SPI_ClearFlag_MODF()`
IFCR	OVRC	`LL_SPI_ClearFlag_OVR()`
IFCR	SPI_IFCR_CRCE	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_EOT	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_MODF	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_OVR	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_SUSP	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_TIFRE	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_TXTF	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_UDR	`LL_SPI_ClearFlag()`
IFCR	SUSPC	`LL_SPI_ClearFlag_SUSP()`
IFCR	TIFREC	`LL_SPI_ClearFlag_FRE()`
IFCR	TXTFC	`LL_SPI_ClearFlag_TXTF()`
IFCR	UDRC	`LL_SPI_ClearFlag_UDR()`
RXCRC	RXCRC	`LL_SPI_GetRxCRC()`
RXDR	.	`LL_SPI_ReceiveData16()` `LL_SPI_ReceiveData32()` `LL_SPI_ReceiveData8()`
RXDR	RXDR	`LL_SPI_DMA_GetRxRegAddr()`
SR	CRCE	`LL_SPI_IsActiveFlag_CRCERR()`
SR	CTSIZE	`LL_SPI_GetRemainingDataFrames()`
SR	DXP	`LL_SPI_IsActiveFlag_DXP()`
SR	EOT	`LL_SPI_IsActiveFlag_EOT()`
SR	MODF	`LL_SPI_IsActiveFlag_MODF()`
SR	OVR	`LL_SPI_IsActiveFlag_OVR()`
SR	RXP	`LL_SPI_IsActiveFlag_RXP()`
SR	RXPLVL	`LL_SPI_GetRxFIFOPackingLevel()`
SR	RXWNE	`LL_SPI_IsActiveFlag_RXWNE()`
SR	SPI_SR_CRCE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_DXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_EOT	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_MODF	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_OVR	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_RXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_RXWNE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_SUSP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TIFRE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXC	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXTF	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_UDR	`LL_SPI_IsActiveFlag()`
SR	SUSP	`LL_SPI_IsActiveFlag_SUSP()`
SR	TIFRE	`LL_SPI_IsActiveFlag_FRE()`
SR	TXC	`LL_SPI_IsActiveFlag_TXC()`
SR	TXP	`LL_SPI_IsActiveFlag_TXP()`
SR	TXTF	`LL_SPI_IsActiveFlag_TXTF()`
SR	UDR	`LL_SPI_IsActiveFlag_UDR()`
TXCRC	TXCRC	`LL_SPI_GetTxCRC()`
TXDR	.	`LL_SPI_TransmitData16()` `LL_SPI_TransmitData32()` `LL_SPI_TransmitData8()`
TXDR	TXDR	`LL_SPI_DMA_GetTxRegAddr()`
UDRDR	UDRDR	`LL_SPI_GetUDRPattern()` `LL_SPI_SetUDRPattern()`

Register	Bit	Function
AUTOCR	TRIGEN	`LL_SPI_Disable_SelectedTrigger()` `LL_SPI_Enable_SelectedTrigger()` `LL_SPI_IsEnabled_SelectedTrigger()`
AUTOCR	TRIGPOL	`LL_SPI_GetTriggerPolarity()` `LL_SPI_SetAutonomousConfig()` `LL_SPI_SetTriggerPolarity()`
AUTOCR	TRIGSEL	`LL_SPI_GetSelectedTrigger()` `LL_SPI_SetAutonomousConfig()` `LL_SPI_SetSelectedTrigger()`
CFG1	BPASS	`LL_SPI_GetBaudRatePrescaler()` `LL_SPI_SetBaudRatePrescaler()` `LL_SPI_SetConfig()`
CFG1	CRCEN	`LL_SPI_DisableCRC()` `LL_SPI_EnableCRC()` `LL_SPI_IsEnabledCRC()`
CFG1	CRCSIZE	`LL_SPI_GetCRCWidth()` `LL_SPI_SetCRCWidth()`
CFG1	DSIZE	`LL_SPI_GetDataWidth()` `LL_SPI_SetConfig()` `LL_SPI_SetDataWidth()`
CFG1	FTHLV	`LL_SPI_GetFIFOThreshold()` `LL_SPI_SetFIFOThreshold()`
CFG1	MBR	`LL_SPI_GetBaudRatePrescaler()` `LL_SPI_SetBaudRatePrescaler()` `LL_SPI_SetConfig()`
CFG1	RXDMAEN	`LL_SPI_DisableDMAReq_RX()` `LL_SPI_EnableDMAReq_RX()` `LL_SPI_IsEnabledDMAReq_RX()`
CFG1	TXDMAEN	`LL_SPI_DisableDMAReq_TX()` `LL_SPI_EnableDMAReq_TX()` `LL_SPI_IsEnabledDMAReq_TX()`
CFG1	UDRCFG	`LL_SPI_GetUDRConfiguration()` `LL_SPI_SetUDRConfiguration()`
CFG2	AFCNTR	`LL_SPI_DisableGPIOControl()` `LL_SPI_EnableGPIOControl()` `LL_SPI_IsEnabledGPIOControl()`
CFG2	COMM	`LL_SPI_GetTransferDirection()` `LL_SPI_IsHalfDuplexDirection()` `LL_SPI_SetConfig()` `LL_SPI_SetTransferDirection()`
CFG2	CPHA	`LL_SPI_GetClockPhase()` `LL_SPI_SetClockPhase()` `LL_SPI_SetConfig()`
CFG2	CPOL	`LL_SPI_GetClockPolarity()` `LL_SPI_SetClockPolarity()` `LL_SPI_SetConfig()`
CFG2	IOSWP	`LL_SPI_DisableMosiMisoSwap()` `LL_SPI_EnableMosiMisoSwap()` `LL_SPI_IsEnabledMosiMisoSwap()`
CFG2	LSBFRST	`LL_SPI_GetTransferBitOrder()` `LL_SPI_SetConfig()` `LL_SPI_SetTransferBitOrder()`
CFG2	MASTER	`LL_SPI_GetMode()` `LL_SPI_SetConfig()` `LL_SPI_SetMode()`
CFG2	MIDI	`LL_SPI_SetInterDataIdleness()`
CFG2	MSSI	`LL_SPI_GetMasterSSIdleness()` `LL_SPI_GetNSSConfig()` `LL_SPI_SetMasterSSIdleness()` `LL_SPI_SetNSSConfig()`
CFG2	RDIOM	`LL_SPI_DisableReadyPin()` `LL_SPI_EnableReadyPin()` `LL_SPI_IsEnabledReadyPin()`
CFG2	RDIOP	`LL_SPI_GetReadyPinPolarity()` `LL_SPI_SetReadyPinPolarity()`
CFG2	SP	`LL_SPI_GetStandard()` `LL_SPI_SetStandard()`
CFG2	SSIOP	`LL_SPI_GetNSSConfig()` `LL_SPI_GetNSSPolarity()` `LL_SPI_SetNSSConfig()` `LL_SPI_SetNSSPolarity()`
CFG2	SSM	`LL_SPI_GetNSSMode()` `LL_SPI_SetNSSMode()`
CFG2	SSOE	`LL_SPI_GetNSSMode()` `LL_SPI_SetNSSMode()`
CFG2	SSOM	`LL_SPI_DisableNSSPulseMgt()` `LL_SPI_EnableNSSPulseMgt()` `LL_SPI_GetNSSConfig()` `LL_SPI_IsEnabledNSSPulse()` `LL_SPI_SetNSSConfig()`
CR1	CRC33_17	`LL_SPI_DisableFullSizeCRC()` `LL_SPI_EnableFullSizeCRC()` `LL_SPI_IsEnabledFullSizeCRC()`
CR1	CSTART	`LL_SPI_IsActiveMasterTransfer()` `LL_SPI_StartMasterTransfer()`
CR1	CSUSP	`LL_SPI_SuspendMasterTransfer()`
CR1	HDDIR	`LL_SPI_GetHalfDuplexDirection()` `LL_SPI_SetHalfDuplexDirection()`
CR1	IOLOCK	`LL_SPI_EnableIOLock()` `LL_SPI_IsEnabledIOLock()`
CR1	MASRX	`LL_SPI_DisableMasterRxAutoSuspend()` `LL_SPI_EnableMasterRxAutoSuspend()` `LL_SPI_IsEnabledMasterRxAutoSuspend()`
CR1	RCRCINI	`LL_SPI_GetRxCRCInitPattern()` `LL_SPI_SetCRCInitPattern()` `LL_SPI_SetRxCRCInitPattern()`
CR1	SPE	`LL_SPI_Disable()` `LL_SPI_Enable()` `LL_SPI_IsEnabled()`
CR1	SSI	`LL_SPI_GetInternalSSLevel()` `LL_SPI_SetConfig()` `LL_SPI_SetInternalSSLevel()`
CR1	TCRCINI	`LL_SPI_GetTxCRCInitPattern()` `LL_SPI_SetCRCInitPattern()` `LL_SPI_SetTxCRCInitPattern()`
CR2	TSIZE	`LL_SPI_GetTransferSize()` `LL_SPI_SetTransferSize()`
CRCPOLY	CRCPOLY	`LL_SPI_GetCRCPolynomial()` `LL_SPI_SetCRCPolynomial()`
IER	CRCEIE	`LL_SPI_DisableIT_CRCERR()` `LL_SPI_EnableIT_CRCERR()` `LL_SPI_IsEnabledIT_CRCERR()`
IER	DXPIE	`LL_SPI_DisableIT_DXP()` `LL_SPI_EnableIT_DXP()` `LL_SPI_IsEnabledIT_DXP()`
IER	EOTIE	`LL_SPI_DisableIT_EOT()` `LL_SPI_EnableIT_EOT()` `LL_SPI_IsEnabledIT_EOT()`
IER	MODFIE	`LL_SPI_DisableIT_MODF()` `LL_SPI_EnableIT_MODF()` `LL_SPI_IsEnabledIT_MODF()`
IER	OVRIE	`LL_SPI_DisableIT_OVR()` `LL_SPI_EnableIT_OVR()` `LL_SPI_IsEnabledIT_OVR()`
IER	RXPIE	`LL_SPI_DisableIT_RXP()` `LL_SPI_EnableIT_RXP()` `LL_SPI_IsEnabledIT_RXP()`
IER	SPI_IER_CRCEIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_DXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_EOTIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_MODFIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_OVRIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_RXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TIFREIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TXTFIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_UDRIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	TIFREIE	`LL_SPI_DisableIT_FRE()` `LL_SPI_EnableIT_FRE()` `LL_SPI_IsEnabledIT_FRE()`
IER	TXPIE	`LL_SPI_DisableIT_TXP()` `LL_SPI_EnableIT_TXP()` `LL_SPI_IsEnabledIT_TXP()`
IER	TXTFIE	`LL_SPI_DisableIT_TXTF()` `LL_SPI_EnableIT_TXTF()` `LL_SPI_IsEnabledIT_TXTF()`
IER	UDRIE	`LL_SPI_DisableIT_UDR()` `LL_SPI_EnableIT_UDR()` `LL_SPI_IsEnabledIT_UDR()`
IFCR	CRCEC	`LL_SPI_ClearFlag_CRCERR()`
IFCR	EOTC	`LL_SPI_ClearFlag_EOT()`
IFCR	MODFC	`LL_SPI_ClearFlag_MODF()`
IFCR	OVRC	`LL_SPI_ClearFlag_OVR()`
IFCR	SPI_IFCR_CRCE	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_EOT	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_MODF	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_OVR	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_SUSP	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_TIFRE	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_TXTF	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_UDR	`LL_SPI_ClearFlag()`
IFCR	SUSPC	`LL_SPI_ClearFlag_SUSP()`
IFCR	TIFREC	`LL_SPI_ClearFlag_FRE()`
IFCR	TXTFC	`LL_SPI_ClearFlag_TXTF()`
IFCR	UDRC	`LL_SPI_ClearFlag_UDR()`
RXCRC	RXCRC	`LL_SPI_GetRxCRC()`
RXDR	.	`LL_SPI_ReceiveData16()` `LL_SPI_ReceiveData32()` `LL_SPI_ReceiveData8()`
RXDR	RXDR	`LL_SPI_DMA_GetRxRegAddr()`
SR	CRCE	`LL_SPI_IsActiveFlag_CRCERR()`
SR	CTSIZE	`LL_SPI_GetRemainingDataFrames()`
SR	DXP	`LL_SPI_IsActiveFlag_DXP()`
SR	EOT	`LL_SPI_IsActiveFlag_EOT()`
SR	MODF	`LL_SPI_IsActiveFlag_MODF()`
SR	OVR	`LL_SPI_IsActiveFlag_OVR()`
SR	RXP	`LL_SPI_IsActiveFlag_RXP()`
SR	RXPLVL	`LL_SPI_GetRxFIFOPackingLevel()`
SR	RXWNE	`LL_SPI_IsActiveFlag_RXWNE()`
SR	SPI_SR_CRCE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_DXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_EOT	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_MODF	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_OVR	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_RXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_RXWNE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_SUSP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TIFRE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXC	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXTF	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_UDR	`LL_SPI_IsActiveFlag()`
SR	SUSP	`LL_SPI_IsActiveFlag_SUSP()`
SR	TIFRE	`LL_SPI_IsActiveFlag_FRE()`
SR	TXC	`LL_SPI_IsActiveFlag_TXC()`
SR	TXP	`LL_SPI_IsActiveFlag_TXP()`
SR	TXTF	`LL_SPI_IsActiveFlag_TXTF()`
SR	UDR	`LL_SPI_IsActiveFlag_UDR()`
TXCRC	TXCRC	`LL_SPI_GetTxCRC()`
TXDR	.	`LL_SPI_TransmitData16()` `LL_SPI_TransmitData32()` `LL_SPI_TransmitData8()`
TXDR	TXDR	`LL_SPI_DMA_GetTxRegAddr()`
UDRDR	UDRDR	`LL_SPI_GetUDRPattern()` `LL_SPI_SetUDRPattern()`

Register	Bit	Function
AUTOCR	TRIGEN	`LL_SPI_Disable_SelectedTrigger()` `LL_SPI_Enable_SelectedTrigger()` `LL_SPI_IsEnabled_SelectedTrigger()`
AUTOCR	TRIGPOL	`LL_SPI_GetTriggerPolarity()` `LL_SPI_SetAutonomousConfig()` `LL_SPI_SetTriggerPolarity()`
AUTOCR	TRIGSEL	`LL_SPI_GetSelectedTrigger()` `LL_SPI_SetAutonomousConfig()` `LL_SPI_SetSelectedTrigger()`
CFG1	BPASS	`LL_SPI_GetBaudRatePrescaler()` `LL_SPI_SetBaudRatePrescaler()` `LL_SPI_SetConfig()`
CFG1	CRCEN	`LL_SPI_DisableCRC()` `LL_SPI_EnableCRC()` `LL_SPI_IsEnabledCRC()`
CFG1	CRCSIZE	`LL_SPI_GetCRCWidth()` `LL_SPI_SetCRCWidth()`
CFG1	DSIZE	`LL_SPI_GetDataWidth()` `LL_SPI_SetConfig()` `LL_SPI_SetDataWidth()`
CFG1	FTHLV	`LL_SPI_GetFIFOThreshold()` `LL_SPI_SetFIFOThreshold()`
CFG1	MBR	`LL_SPI_GetBaudRatePrescaler()` `LL_SPI_SetBaudRatePrescaler()` `LL_SPI_SetConfig()`
CFG1	RXDMAEN	`LL_SPI_DisableDMAReq_RX()` `LL_SPI_EnableDMAReq_RX()` `LL_SPI_IsEnabledDMAReq_RX()`
CFG1	TXDMAEN	`LL_SPI_DisableDMAReq_TX()` `LL_SPI_EnableDMAReq_TX()` `LL_SPI_IsEnabledDMAReq_TX()`
CFG1	UDRCFG	`LL_SPI_GetUDRConfiguration()` `LL_SPI_SetUDRConfiguration()`
CFG2	AFCNTR	`LL_SPI_DisableGPIOControl()` `LL_SPI_EnableGPIOControl()` `LL_SPI_IsEnabledGPIOControl()`
CFG2	COMM	`LL_SPI_GetTransferDirection()` `LL_SPI_IsHalfDuplexDirection()` `LL_SPI_SetConfig()` `LL_SPI_SetTransferDirection()`
CFG2	CPHA	`LL_SPI_GetClockPhase()` `LL_SPI_SetClockPhase()` `LL_SPI_SetConfig()`
CFG2	CPOL	`LL_SPI_GetClockPolarity()` `LL_SPI_SetClockPolarity()` `LL_SPI_SetConfig()`
CFG2	IOSWP	`LL_SPI_DisableMosiMisoSwap()` `LL_SPI_EnableMosiMisoSwap()` `LL_SPI_IsEnabledMosiMisoSwap()`
CFG2	LSBFRST	`LL_SPI_GetTransferBitOrder()` `LL_SPI_SetConfig()` `LL_SPI_SetTransferBitOrder()`
CFG2	MASTER	`LL_SPI_GetMode()` `LL_SPI_SetConfig()` `LL_SPI_SetMode()`
CFG2	MIDI	`LL_SPI_SetInterDataIdleness()`
CFG2	MSSI	`LL_SPI_GetMasterSSIdleness()` `LL_SPI_GetNSSConfig()` `LL_SPI_SetMasterSSIdleness()` `LL_SPI_SetNSSConfig()`
CFG2	RDIOM	`LL_SPI_DisableReadyPin()` `LL_SPI_EnableReadyPin()` `LL_SPI_IsEnabledReadyPin()`
CFG2	RDIOP	`LL_SPI_GetReadyPinPolarity()` `LL_SPI_SetReadyPinPolarity()`
CFG2	SP	`LL_SPI_GetStandard()` `LL_SPI_SetStandard()`
CFG2	SSIOP	`LL_SPI_GetNSSConfig()` `LL_SPI_GetNSSPolarity()` `LL_SPI_SetNSSConfig()` `LL_SPI_SetNSSPolarity()`
CFG2	SSM	`LL_SPI_GetNSSMode()` `LL_SPI_SetNSSMode()`
CFG2	SSOE	`LL_SPI_GetNSSMode()` `LL_SPI_SetNSSMode()`
CFG2	SSOM	`LL_SPI_DisableNSSPulseMgt()` `LL_SPI_EnableNSSPulseMgt()` `LL_SPI_GetNSSConfig()` `LL_SPI_IsEnabledNSSPulse()` `LL_SPI_SetNSSConfig()`
CR1	CRC33_17	`LL_SPI_DisableFullSizeCRC()` `LL_SPI_EnableFullSizeCRC()` `LL_SPI_IsEnabledFullSizeCRC()`
CR1	CSTART	`LL_SPI_IsActiveMasterTransfer()` `LL_SPI_StartMasterTransfer()`
CR1	CSUSP	`LL_SPI_SuspendMasterTransfer()`
CR1	HDDIR	`LL_SPI_GetHalfDuplexDirection()` `LL_SPI_SetHalfDuplexDirection()`
CR1	IOLOCK	`LL_SPI_EnableIOLock()` `LL_SPI_IsEnabledIOLock()`
CR1	MASRX	`LL_SPI_DisableMasterRxAutoSuspend()` `LL_SPI_EnableMasterRxAutoSuspend()` `LL_SPI_IsEnabledMasterRxAutoSuspend()`
CR1	RCRCINI	`LL_SPI_GetRxCRCInitPattern()` `LL_SPI_SetCRCInitPattern()` `LL_SPI_SetRxCRCInitPattern()`
CR1	SPE	`LL_SPI_Disable()` `LL_SPI_Enable()` `LL_SPI_IsEnabled()`
CR1	SSI	`LL_SPI_GetInternalSSLevel()` `LL_SPI_SetConfig()` `LL_SPI_SetInternalSSLevel()`
CR1	TCRCINI	`LL_SPI_GetTxCRCInitPattern()` `LL_SPI_SetCRCInitPattern()` `LL_SPI_SetTxCRCInitPattern()`
CR2	TSIZE	`LL_SPI_GetTransferSize()` `LL_SPI_SetTransferSize()`
CRCPOLY	CRCPOLY	`LL_SPI_GetCRCPolynomial()` `LL_SPI_SetCRCPolynomial()`
IER	CRCEIE	`LL_SPI_DisableIT_CRCERR()` `LL_SPI_EnableIT_CRCERR()` `LL_SPI_IsEnabledIT_CRCERR()`
IER	DXPIE	`LL_SPI_DisableIT_DXP()` `LL_SPI_EnableIT_DXP()` `LL_SPI_IsEnabledIT_DXP()`
IER	EOTIE	`LL_SPI_DisableIT_EOT()` `LL_SPI_EnableIT_EOT()` `LL_SPI_IsEnabledIT_EOT()`
IER	MODFIE	`LL_SPI_DisableIT_MODF()` `LL_SPI_EnableIT_MODF()` `LL_SPI_IsEnabledIT_MODF()`
IER	OVRIE	`LL_SPI_DisableIT_OVR()` `LL_SPI_EnableIT_OVR()` `LL_SPI_IsEnabledIT_OVR()`
IER	RXPIE	`LL_SPI_DisableIT_RXP()` `LL_SPI_EnableIT_RXP()` `LL_SPI_IsEnabledIT_RXP()`
IER	SPI_IER_CRCEIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_DXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_EOTIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_MODFIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_OVRIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_RXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TIFREIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TXPIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_TXTFIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	SPI_IER_UDRIE	`LL_SPI_DisableIT()` `LL_SPI_EnableIT()` `LL_SPI_IsEnabledIT()`
IER	TIFREIE	`LL_SPI_DisableIT_FRE()` `LL_SPI_EnableIT_FRE()` `LL_SPI_IsEnabledIT_FRE()`
IER	TXPIE	`LL_SPI_DisableIT_TXP()` `LL_SPI_EnableIT_TXP()` `LL_SPI_IsEnabledIT_TXP()`
IER	TXTFIE	`LL_SPI_DisableIT_TXTF()` `LL_SPI_EnableIT_TXTF()` `LL_SPI_IsEnabledIT_TXTF()`
IER	UDRIE	`LL_SPI_DisableIT_UDR()` `LL_SPI_EnableIT_UDR()` `LL_SPI_IsEnabledIT_UDR()`
IFCR	CRCEC	`LL_SPI_ClearFlag_CRCERR()`
IFCR	EOTC	`LL_SPI_ClearFlag_EOT()`
IFCR	MODFC	`LL_SPI_ClearFlag_MODF()`
IFCR	OVRC	`LL_SPI_ClearFlag_OVR()`
IFCR	SPI_IFCR_CRCE	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_EOT	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_MODF	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_OVR	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_SUSP	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_TIFRE	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_TXTF	`LL_SPI_ClearFlag()`
IFCR	SPI_IFCR_UDR	`LL_SPI_ClearFlag()`
IFCR	SUSPC	`LL_SPI_ClearFlag_SUSP()`
IFCR	TIFREC	`LL_SPI_ClearFlag_FRE()`
IFCR	TXTFC	`LL_SPI_ClearFlag_TXTF()`
IFCR	UDRC	`LL_SPI_ClearFlag_UDR()`
RXCRC	RXCRC	`LL_SPI_GetRxCRC()`
RXDR	.	`LL_SPI_ReceiveData16()` `LL_SPI_ReceiveData32()` `LL_SPI_ReceiveData8()`
RXDR	RXDR	`LL_SPI_DMA_GetRxRegAddr()`
SR	CRCE	`LL_SPI_IsActiveFlag_CRCERR()`
SR	CTSIZE	`LL_SPI_GetRemainingDataFrames()`
SR	DXP	`LL_SPI_IsActiveFlag_DXP()`
SR	EOT	`LL_SPI_IsActiveFlag_EOT()`
SR	MODF	`LL_SPI_IsActiveFlag_MODF()`
SR	OVR	`LL_SPI_IsActiveFlag_OVR()`
SR	RXP	`LL_SPI_IsActiveFlag_RXP()`
SR	RXPLVL	`LL_SPI_GetRxFIFOPackingLevel()`
SR	RXWNE	`LL_SPI_IsActiveFlag_RXWNE()`
SR	SPI_SR_CRCE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_DXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_EOT	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_MODF	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_OVR	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_RXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_RXWNE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_SUSP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TIFRE	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXC	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXP	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_TXTF	`LL_SPI_IsActiveFlag()`
SR	SPI_SR_UDR	`LL_SPI_IsActiveFlag()`
SR	SUSP	`LL_SPI_IsActiveFlag_SUSP()`
SR	TIFRE	`LL_SPI_IsActiveFlag_FRE()`
SR	TXC	`LL_SPI_IsActiveFlag_TXC()`
SR	TXP	`LL_SPI_IsActiveFlag_TXP()`
SR	TXTF	`LL_SPI_IsActiveFlag_TXTF()`
SR	UDR	`LL_SPI_IsActiveFlag_UDR()`
TXCRC	TXCRC	`LL_SPI_GetTxCRC()`
TXDR	.	`LL_SPI_TransmitData16()` `LL_SPI_TransmitData32()` `LL_SPI_TransmitData8()`
TXDR	TXDR	`LL_SPI_DMA_GetTxRegAddr()`
UDRDR	UDRDR	`LL_SPI_GetUDRPattern()` `LL_SPI_SetUDRPattern()`