LL UCPD Constants

Status flags definition

group UCPD_LL_EC_GET_FLAG

Flags defines which can be used with LL_UCPD_READ_REG function.

Defines

LL_UCPD_SR_TXIS UCPD_SR_TXIS

Transmit interrupt status

LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC

Transmit message discarded interrupt

LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT

Transmit message sent interrupt

LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT

Transmit message abort interrupt

LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC

HRST discarded interrupt

LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT

HRST sent interrupt

LL_UCPD_SR_TXUND UCPD_SR_TXUND

Tx data underrun condition interrupt

LL_UCPD_SR_RXNE UCPD_SR_RXNE

Receive data register not empty interrupt

LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET

Rx ordered set (4 K-codes) detected interrupt

LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET

Rx Hard Reset detect interrupt

LL_UCPD_SR_RXOVR UCPD_SR_RXOVR

Rx data overflow interrupt

LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND

Rx message received

LL_UCPD_SR_RXERR UCPD_SR_RXERR

Rx error

LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1

Type-C voltage level event on CC1

LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2

Type-C voltage level event on CC2

LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1

Status of DC level on CC1 pin

LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2

Status of DC level on CC2 pin

LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT

Fast Role Swap detection event

Interrupts definition

group UCPD_LL_EC_IT

IT defines which can be used with LL_UCPD_READ_REG and LL_UCPD_WRITE_REG functions.

Defines

LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE

Enable transmit interrupt status

LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE

Enable transmit message discarded interrupt

LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE

Enable transmit message sent interrupt

LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE

Enable transmit message abort interrupt

LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE

Enable HRST discarded interrupt

LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE

Enable HRST sent interrupt

LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE

Enable tx data underrun condition interrupt

LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE

Enable Receive data register not empty interrupt

LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE

Enable Rx ordered set (4 K-codes) detected interrupt

LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE

Enable Rx Hard Reset detect interrupt

LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE

Enable Rx data overflow interrupt

LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE

Enable Rx message received

LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE

Enable Type-C voltage level event on CC1

LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE

Enable Type-C voltage level event on CC2

LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE

Enable Fast Role Swap detection event

Tx ordered sets definition

group UCPD_LL_EC_ORDERSET

Definition of the usual Tx ordered sets.

Defines

LL_UCPD_SYNC1 (0x18U)

K-code for Startsynch #1

LL_UCPD_SYNC2 (0x11U)

K-code for Startsynch #2

LL_UCPD_SYNC3 (0x06U)

K-code for Startsynch #3

LL_UCPD_RST1 (0x07U)

K-code for Hard Reset #1

LL_UCPD_RST2 (0x19U)

K-code for Hard Reset #2

LL_UCPD_EOP (0x0DU)

K-code for EOP End of Packet

LL_UCPD_TX_ORDERED_SET_SOP ( LL_UCPD_SYNC1 | ( LL_UCPD_SYNC1 <<5U) | ( LL_UCPD_SYNC1 <<10U) | ( LL_UCPD_SYNC2 <<15U))

SOP Ordered set coding

LL_UCPD_TX_ORDERED_SET_SOP1 ( LL_UCPD_SYNC1 | ( LL_UCPD_SYNC1 <<5U) | ( LL_UCPD_SYNC3 <<10U) | ( LL_UCPD_SYNC3 <<15U))

SOP’ Ordered set coding

LL_UCPD_TX_ORDERED_SET_SOP2 ( LL_UCPD_SYNC1 | ( LL_UCPD_SYNC3 <<5U) | ( LL_UCPD_SYNC1 <<10U) | ( LL_UCPD_SYNC3 <<15U))

SOP’’ Ordered set coding

LL_UCPD_TX_ORDERED_SET_HARD_RESET ( LL_UCPD_RST1 | ( LL_UCPD_RST1 <<5U) | ( LL_UCPD_RST1 <<10U) | ( LL_UCPD_RST2 <<15U))

Hard Reset Ordered set coding

LL_UCPD_TX_ORDERED_SET_CABLE_RESET ( LL_UCPD_RST1 | ( LL_UCPD_SYNC1 <<5U) | ( LL_UCPD_RST1 <<10U) | ( LL_UCPD_SYNC3 <<15U))

Cable Reset Ordered set coding

LL_UCPD_TX_ORDERED_SET_SOP1_DEBUG ( LL_UCPD_SYNC1 | ( LL_UCPD_RST2 <<5U) | ( LL_UCPD_RST2 <<10U) | ( LL_UCPD_SYNC3 <<15U))

SOP’ Debug Ordered set coding

LL_UCPD_TX_ORDERED_SET_SOP2_DEBUG ( LL_UCPD_SYNC1 | ( LL_UCPD_RST2 <<5U) | ( LL_UCPD_SYNC3 <<10U) | ( LL_UCPD_SYNC2 <<15U))

SOP’’ Debug Ordered set coding

Role mode

group UCPD_LL_EC_MODE

Defines

LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE

Mode SNK Rd

LL_UCPD_ROLE_SRC (0x0U)

Mode SRC Rp

Resistor value

group UCPD_LL_EC_RESISTOR

Defines

LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0

Rp default

LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1

Rp 1.5 A

LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE

Rp 3.0 A

LL_UCPD_RESISTOR_NONE (0x0U)

No resistor

Rx ordered set configuration

group UCPD_LL_EC_CFGR1_ORDERSET

Defines

LL_UCPD_RX_ORDERED_SET_SOP UCPD_CFGR1_RXORDSETEN_0

SOP Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_SOP1 UCPD_CFGR1_RXORDSETEN_1

SOP’ Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_SOP2 UCPD_CFGR1_RXORDSETEN_2

SOP’’ Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_HARDRST UCPD_CFGR1_RXORDSETEN_3

Hard Reset Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_CABLERST UCPD_CFGR1_RXORDSETEN_4

Cable Reset Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_SOP1_DEBUG UCPD_CFGR1_RXORDSETEN_5

SOP’ Debug Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_SOP2_DEBUG UCPD_CFGR1_RXORDSETEN_6

SOP’’ Debug Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_SOP_EXT1 UCPD_CFGR1_RXORDSETEN_7

SOP extension#1 Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_SOP_EXT2 UCPD_CFGR1_RXORDSETEN_8

SOP extension#2 Ordered set detection enabled

LL_UCPD_RX_ORDERED_SET_NONE (0x0U)

Ordered set detection disabled

Voltage state on CCx line

group UCPD_LL_EC_Vstate

Defines

LL_UCPD_CC1_VSTATE_LOWEST (0x00U)

Voltage level on CC1 ligne is lowest

LL_UCPD_CC1_VSTATE_LOW UCPD_SR_TYPEC_VSTATE_CC1_0

Voltage level on CC1 ligne is low

LL_UCPD_CC1_VSTATE_HIGH UCPD_SR_TYPEC_VSTATE_CC1_1

Voltage level on CC1 ligne is high

LL_UCPD_CC1_VSTATE_HIGHEST

(UCPD_SR_TYPEC_VSTATE_CC1_0 | \

UCPD_SR_TYPEC_VSTATE_CC1_1)


Voltage level on CC1 ligne is highest

LL_UCPD_CC2_VSTATE_LOWEST (0x00U)

Voltage level on CC2 ligne is lowest

LL_UCPD_CC2_VSTATE_LOW UCPD_SR_TYPEC_VSTATE_CC2_0

Voltage level on CC2 ligne is low

LL_UCPD_CC2_VSTATE_HIGH UCPD_SR_TYPEC_VSTATE_CC2_1

Voltage level on CC2 ligne is high

LL_UCPD_CC2_VSTATE_HIGHEST

(UCPD_SR_TYPEC_VSTATE_CC2_0 | \

UCPD_SR_TYPEC_VSTATE_CC2_1)


Voltage level on CC2 ligne is highest

Prescaler for UCPDCLK

group UCPD_LL_EC_PSC

Defines

LL_UCPD_PSC_DIV1 (0x0U)

Bypass pre-scaling / divide by 1

LL_UCPD_PSC_DIV2 UCPD_CFGR1_PSC_UCPDCLK_0

Pre-scale clock by dividing by 2

LL_UCPD_PSC_DIV4 UCPD_CFGR1_PSC_UCPDCLK_1

Pre-scale clock by dividing by 4

LL_UCPD_PSC_DIV8

(UCPD_CFGR1_PSC_UCPDCLK_1 | \

UCPD_CFGR1_PSC_UCPDCLK_0)


Pre-scale clock by dividing by 8

LL_UCPD_PSC_DIV16 UCPD_CFGR1_PSC_UCPDCLK_2

Pre-scale clock by dividing by 16

Divider for producing half-bit clock hbit_clk from ucpd_clk

group UCPD_LL_EC_HBITCLKDIV

Defines

LL_UCPD_HBITCLK_DIV1 (0x00U)

Bypass divider

LL_UCPD_HBITCLK_DIV2 (0x01U)

Divide ucpd_clk by 2

LL_UCPD_HBITCLK_DIV3 (0x02U)

Divide ucpd_clk by 3

LL_UCPD_HBITCLK_DIV4 (0x03U)

Divide ucpd_clk by 4

LL_UCPD_HBITCLK_DIV5 (0x04U)

Divide ucpd_clk by 5

LL_UCPD_HBITCLK_DIV6 (0x05U)

Divide ucpd_clk by 6

LL_UCPD_HBITCLK_DIV7 (0x06U)

Divide ucpd_clk by 7

LL_UCPD_HBITCLK_DIV8 (0x07U)

Divide ucpd_clk by 8

LL_UCPD_HBITCLK_DIV9 (0x08U)

Divide ucpd_clk by 9

LL_UCPD_HBITCLK_DIV10 (0x09U)

Divide ucpd_clk by 10

LL_UCPD_HBITCLK_DIV11 (0x0AU)

Divide ucpd_clk by 11

LL_UCPD_HBITCLK_DIV12 (0x0BU)

Divide ucpd_clk by 12

LL_UCPD_HBITCLK_DIV13 (0x0CU)

Divide ucpd_clk by 13

LL_UCPD_HBITCLK_DIV14 (0x0DU)

Divide ucpd_clk by 14

LL_UCPD_HBITCLK_DIV15 (0x0EU)

Divide ucpd_clk by 15

LL_UCPD_HBITCLK_DIV16 (0x0FU)

Divide ucpd_clk by 16

LL_UCPD_HBITCLK_DIV17 (0x10U)

Divide ucpd_clk by 17

LL_UCPD_HBITCLK_DIV18 (0x11U)

Divide ucpd_clk by 28

LL_UCPD_HBITCLK_DIV19 (0x12U)

Divide ucpd_clk by 19

LL_UCPD_HBITCLK_DIV20 (0x13U)

Divide ucpd_clk by 20

LL_UCPD_HBITCLK_DIV21 (0x14U)

Divide ucpd_clk by 21

LL_UCPD_HBITCLK_DIV22 (0x15U)

Divide ucpd_clk by 22

LL_UCPD_HBITCLK_DIV23 (0x16U)

Divide ucpd_clk by 23

LL_UCPD_HBITCLK_DIV24 (0x17U)

Divide ucpd_clk by 24

LL_UCPD_HBITCLK_DIV25 (0x18U)

Divide ucpd_clk by 25

LL_UCPD_HBITCLK_DIV26 (0x19U)

Divide ucpd_clk by 26

LL_UCPD_HBITCLK_DIV27 (0x1AU)

Divide ucpd_clk by 27

LL_UCPD_HBITCLK_DIV28 (0x1BU)

Divide ucpd_clk by 28

LL_UCPD_HBITCLK_DIV29 (0x1CU)

Divide ucpd_clk by 29

LL_UCPD_HBITCLK_DIV30 (0x1DU)

Divide ucpd_clk by 30

LL_UCPD_HBITCLK_DIV31 (0x1EU)

Divide ucpd_clk by 31

LL_UCPD_HBITCLK_DIV32 (0x1FU)

Divide ucpd_clk by 32

LL_UCPD_HBITCLK_DIV33 (0x20U)

Divide ucpd_clk by 33

LL_UCPD_HBITCLK_DIV34 (0x21U)

Divide ucpd_clk by 34

LL_UCPD_HBITCLK_DIV35 (0x22U)

Divide ucpd_clk by 35

LL_UCPD_HBITCLK_DIV36 (0x23U)

Divide ucpd_clk by 36

LL_UCPD_HBITCLK_DIV37 (0x24U)

Divide ucpd_clk by 37

LL_UCPD_HBITCLK_DIV38 (0x25U)

Divide ucpd_clk by 38

LL_UCPD_HBITCLK_DIV39 (0x26U)

Divide ucpd_clk by 39

LL_UCPD_HBITCLK_DIV40 (0x27U)

Divide ucpd_clk by 40

LL_UCPD_HBITCLK_DIV41 (0x28U)

Divide ucpd_clk by 41

LL_UCPD_HBITCLK_DIV42 (0x29U)

Divide ucpd_clk by 42

LL_UCPD_HBITCLK_DIV43 (0x2AU)

Divide ucpd_clk by 43

LL_UCPD_HBITCLK_DIV44 (0x2BU)

Divide ucpd_clk by 44

LL_UCPD_HBITCLK_DIV45 (0x2CU)

Divide ucpd_clk by 45

LL_UCPD_HBITCLK_DIV46 (0x2DU)

Divide ucpd_clk by 46

LL_UCPD_HBITCLK_DIV47 (0x2EU)

Divide ucpd_clk by 47

LL_UCPD_HBITCLK_DIV48 (0x2FU)

Divide ucpd_clk by 48

LL_UCPD_HBITCLK_DIV49 (0x30U)

Divide ucpd_clk by 49

LL_UCPD_HBITCLK_DIV50 (0x31U)

Divide ucpd_clk by 50

LL_UCPD_HBITCLK_DIV51 (0x32U)

Divide ucpd_clk by 51

LL_UCPD_HBITCLK_DIV52 (0x33U)

Divide ucpd_clk by 52

LL_UCPD_HBITCLK_DIV53 (0x34U)

Divide ucpd_clk by 53

LL_UCPD_HBITCLK_DIV54 (0x35U)

Divide ucpd_clk by 54

LL_UCPD_HBITCLK_DIV55 (0x36U)

Divide ucpd_clk by 55

LL_UCPD_HBITCLK_DIV56 (0x37U)

Divide ucpd_clk by 56

LL_UCPD_HBITCLK_DIV57 (0x38U)

Divide ucpd_clk by 57

LL_UCPD_HBITCLK_DIV58 (0x39U)

Divide ucpd_clk by 58

LL_UCPD_HBITCLK_DIV59 (0x3AU)

Divide ucpd_clk by 59

LL_UCPD_HBITCLK_DIV60 (0x3BU)

Divide ucpd_clk by 60

LL_UCPD_HBITCLK_DIV61 (0x3CU)

Divide ucpd_clk by 61

LL_UCPD_HBITCLK_DIV62 (0x3DU)

Divide ucpd_clk by 62

LL_UCPD_HBITCLK_DIV63 (0x3EU)

Divide ucpd_clk by 63

LL_UCPD_HBITCLK_DIV64 (0x3FU)

Divide ucpd_clk by 64

Divider for producing transition window duration from hbit_clk

group UCPD_LL_EC_TRANSWINDIV

Defines

LL_UCPD_TRANSWIN_DIVINVALID (0x00U)

Not supported

LL_UCPD_TRANSWIN_DIV2 (0x01U)

Divide hbit_clk by 2

LL_UCPD_TRANSWIN_DIV3 (0x02U)

Divide hbit_clk by 3

LL_UCPD_TRANSWIN_DIV4 (0x03U)

Divide hbit_clk by 4

LL_UCPD_TRANSWIN_DIV5 (0x04U)

Divide hbit_clk by 5

LL_UCPD_TRANSWIN_DIV6 (0x05U)

Divide hbit_clk by 6

LL_UCPD_TRANSWIN_DIV7 (0x06U)

Divide hbit_clk by 7

LL_UCPD_TRANSWIN_DIV8 (0x07U)

Divide hbit_clk by 8

LL_UCPD_TRANSWIN_DIV9 (0x08U)

Divide hbit_clk by 9

LL_UCPD_TRANSWIN_DIV10 (0x09U)

Divide hbit_clk by 10

LL_UCPD_TRANSWIN_DIV11 (0x0AU)

Divide hbit_clk by 11

LL_UCPD_TRANSWIN_DIV12 (0x0BU)

Divide hbit_clk by 12

LL_UCPD_TRANSWIN_DIV13 (0x0CU)

Divide hbit_clk by 13

LL_UCPD_TRANSWIN_DIV14 (0x0DU)

Divide hbit_clk by 14

LL_UCPD_TRANSWIN_DIV15 (0x0EU)

Divide hbit_clk by 15

LL_UCPD_TRANSWIN_DIV16 (0x0FU)

Divide hbit_clk by 16

LL_UCPD_TRANSWIN_DIV17 (0x10U)

Divide hbit_clk by 17

LL_UCPD_TRANSWIN_DIV18 (0x11U)

Divide hbit_clk by 28

LL_UCPD_TRANSWIN_DIV19 (0x12U)

Divide hbit_clk by 19

LL_UCPD_TRANSWIN_DIV20 (0x13U)

Divide hbit_clk by 20

LL_UCPD_TRANSWIN_DIV21 (0x14U)

Divide hbit_clk by 21

LL_UCPD_TRANSWIN_DIV22 (0x15U)

Divide hbit_clk by 22

LL_UCPD_TRANSWIN_DIV23 (0x16U)

Divide hbit_clk by 23

LL_UCPD_TRANSWIN_DIV24 (0x17U)

Divide hbit_clk by 24

LL_UCPD_TRANSWIN_DIV25 (0x18U)

Divide hbit_clk by 25

LL_UCPD_TRANSWIN_DIV26 (0x19U)

Divide hbit_clk by 26

LL_UCPD_TRANSWIN_DIV27 (0x1AU)

Divide hbit_clk by 27

LL_UCPD_TRANSWIN_DIV28 (0x1BU)

Divide hbit_clk by 28

LL_UCPD_TRANSWIN_DIV29 (0x1CU)

Divide hbit_clk by 29

LL_UCPD_TRANSWIN_DIV30 (0x1DU)

Divide hbit_clk by 30

LL_UCPD_TRANSWIN_DIV31 (0x1EU)

Divide hbit_clk by 31

LL_UCPD_TRANSWIN_DIV32 (0x1FU)

Divide hbit_clk by 32

Divider for producing inter-frame gap timer clock from ucpd_clk

group UCPD_LL_EC_IFRGAPDIV

Defines

LL_UCPD_IFRGAP_DIVINVALID (0x00U)

Not supported

LL_UCPD_IFRGAP_DIV2 (0x01U)

Divide ucpd_clk by 2

LL_UCPD_IFRGAP_DIV3 (0x02U)

Divide ucpd_clk by 3

LL_UCPD_IFRGAP_DIV4 (0x03U)

Divide ucpd_clk by 4

LL_UCPD_IFRGAP_DIV5 (0x04U)

Divide ucpd_clk by 5

LL_UCPD_IFRGAP_DIV6 (0x05U)

Divide ucpd_clk by 6

LL_UCPD_IFRGAP_DIV7 (0x06U)

Divide ucpd_clk by 7

LL_UCPD_IFRGAP_DIV8 (0x07U)

Divide ucpd_clk by 8

LL_UCPD_IFRGAP_DIV9 (0x08U)

Divide ucpd_clk by 9

LL_UCPD_IFRGAP_DIV10 (0x09U)

Divide ucpd_clk by 10

LL_UCPD_IFRGAP_DIV11 (0x0AU)

Divide ucpd_clk by 11

LL_UCPD_IFRGAP_DIV12 (0x0BU)

Divide ucpd_clk by 12

LL_UCPD_IFRGAP_DIV13 (0x0CU)

Divide ucpd_clk by 13

LL_UCPD_IFRGAP_DIV14 (0x0DU)

Divide ucpd_clk by 14

LL_UCPD_IFRGAP_DIV15 (0x0EU)

Divide ucpd_clk by 15

LL_UCPD_IFRGAP_DIV16 (0x0FU)

Divide ucpd_clk by 16

LL_UCPD_IFRGAP_DIV17 (0x10U)

Divide ucpd_clk by 17

LL_UCPD_IFRGAP_DIV18 (0x11U)

Divide ucpd_clk by 28

LL_UCPD_IFRGAP_DIV19 (0x12U)

Divide ucpd_clk by 19

LL_UCPD_IFRGAP_DIV20 (0x13U)

Divide ucpd_clk by 20

LL_UCPD_IFRGAP_DIV21 (0x14U)

Divide ucpd_clk by 21

LL_UCPD_IFRGAP_DIV22 (0x15U)

Divide ucpd_clk by 22

LL_UCPD_IFRGAP_DIV23 (0x16U)

Divide ucpd_clk by 23

LL_UCPD_IFRGAP_DIV24 (0x17U)

Divide ucpd_clk by 24

LL_UCPD_IFRGAP_DIV25 (0x18U)

Divide ucpd_clk by 25

LL_UCPD_IFRGAP_DIV26 (0x19U)

Divide ucpd_clk by 26

LL_UCPD_IFRGAP_DIV27 (0x1AU)

Divide ucpd_clk by 27

LL_UCPD_IFRGAP_DIV28 (0x1BU)

Divide ucpd_clk by 28

LL_UCPD_IFRGAP_DIV29 (0x1CU)

Divide ucpd_clk by 29

LL_UCPD_IFRGAP_DIV30 (0x1DU)

Divide ucpd_clk by 30

LL_UCPD_IFRGAP_DIV31 (0x1EU)

Divide ucpd_clk by 31

LL_UCPD_IFRGAP_DIV32 (0x1FU)

Divide ucpd_clk by 32

BMC decoder Rx pre-filter sampling method

group UCPD_LL_EC_RXFILT2N3

Defines

LL_UCPD_RX_PREFILTER_3SAMPLES (0x0U)

3 samples method for BMC decoder Rx pre-filter

LL_UCPD_RX_PREFILTER_2SAMPLES (0x1U)

2 samples method for BMC decoder Rx pre-filter

CC pin enable

group UCPD_LL_EC_CCENABLE

Defines

LL_UCPD_CCENABLE_NONE (0x0U)

Neither PHY is activated

LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0

Controls apply to only CC1

LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1

Controls apply to only CC1

LL_UCPD_CCENABLE_CC1CC2

(UCPD_CR_CCENABLE_0 | \

UCPD_CR_CCENABLE_1)


Controls apply to both CC1 and CC2

CC pin selection

group UCPD_LL_EC_CCPIN

Defines

LL_UCPD_CCPIN_CC1 (0x0U)

Use CC1 IO for power delivery communication

LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL

Use CC2 IO for power delivery communication

Receiver mode

group UCPD_LL_EC_RXMODE

Defines

LL_UCPD_RXMODE_NORMAL (0x0U)

Normal receive mode

LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE

BIST receive mode (BIST Test Data Mode)

Type of Tx packet

group UCPD_LL_EC_TXMODE

Defines

LL_UCPD_TXMODE_NORMAL (0x0U)

Initiate the transfer of a Tx message

LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0

Trigger a the transfer of a Cable Reset sequence

LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1

Trigger a BIST test sequence send (BIST Carrier Mode 2)

Detected Rx ordered set code

group UCPD_LL_EC_RXORDSET

Defines

LL_UCPD_RX_ORDERED_SET_DETECT_SOP (0x0U)

< SOP code detected in receiver SOP’ code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_SOP1 UCPD_RX_ORDSETR_RXORDSET_0

SOP’’ code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_SOP2 UCPD_RX_ORDSETR_RXORDSET_1

SOP’ Debug code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_SOP1_DEBUG (UCPD_RX_ORDSETR_RXORDSET_0 | UCPD_RX_ORDSETR_RXORDSET_1)

SOP’’ Debug code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_SOP2_DEBUG UCPD_RX_ORDSETR_RXORDSET_2

Cable Reset code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_CABLE_RESET (UCPD_RX_ORDSETR_RXORDSET_2 | UCPD_RX_ORDSETR_RXORDSET_0)

SOP extension#1 code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_SOPEXT1 (UCPD_RX_ORDSETR_RXORDSET_2 | UCPD_RX_ORDSETR_RXORDSET_1)

SOP extension#2 code detected in receiver

LL_UCPD_RX_ORDERED_SET_DETECT_SOPEXT2

(UCPD_RX_ORDSETR_RXORDSET_2 | UCPD_RX_ORDSETR_RXORDSET_1 | \

UCPD_RX_ORDSETR_RXORDSET_0)