LL USART Constants ¶

Clear Flags Defines ¶

group USART_LL_EC_CLEAR_FLAG

Flags defines which can be used with LL_USART_WRITE_REG function.

Defines

LL_USART_ICR_PECF USART_ICR_PECF ¶: Parity error clear flag

LL_USART_ICR_FECF USART_ICR_FECF ¶: Framing error clear flag

LL_USART_ICR_NECF USART_ICR_NECF ¶: Noise error detected clear flag

LL_USART_ICR_ORECF USART_ICR_ORECF ¶: Overrun error clear flag

LL_USART_ICR_IDLECF USART_ICR_IDLECF ¶: Idle line detected clear flag

LL_USART_ICR_TXFECF USART_ICR_TXFECF ¶: TX FIFO Empty clear flag

LL_USART_ICR_TCCF USART_ICR_TCCF ¶: Transmission complete clear flag

LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF ¶: Transmission completed before guard time clear flag

LL_USART_ICR_LBDCF USART_ICR_LBDCF ¶: LIN break detection clear flag

LL_USART_ICR_CTSCF USART_ICR_CTSCF ¶: CTS clear flag

LL_USART_ICR_RTOCF USART_ICR_RTOCF ¶: Receiver timeout clear flag

LL_USART_ICR_EOBCF USART_ICR_EOBCF ¶: End of block clear flag

LL_USART_ICR_UDRCF USART_ICR_UDRCF ¶: SPI Slave Underrun clear flag

LL_USART_ICR_CMCF USART_ICR_CMCF ¶: Character match clear flag

group USART_LL_EC_CLEAR_FLAG

Flags defines which can be used with LL_USART_WRITE_REG function.

Defines

LL_USART_ICR_PECF USART_ICR_PECF: Parity error clear flag

LL_USART_ICR_FECF USART_ICR_FECF: Framing error clear flag

LL_USART_ICR_NECF USART_ICR_NECF: Noise error detected clear flag

LL_USART_ICR_ORECF USART_ICR_ORECF: Overrun error clear flag

LL_USART_ICR_IDLECF USART_ICR_IDLECF: Idle line detected clear flag

LL_USART_ICR_TXFECF USART_ICR_TXFECF: TX FIFO Empty clear flag

LL_USART_ICR_TCCF USART_ICR_TCCF: Transmission complete clear flag

LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF: Transmission completed before guard time clear flag

LL_USART_ICR_LBDCF USART_ICR_LBDCF: LIN break detection clear flag

LL_USART_ICR_CTSCF USART_ICR_CTSCF: CTS clear flag

LL_USART_ICR_RTOCF USART_ICR_RTOCF: Receiver timeout clear flag

LL_USART_ICR_EOBCF USART_ICR_EOBCF: End of block clear flag

LL_USART_ICR_UDRCF USART_ICR_UDRCF: SPI Slave Underrun clear flag

LL_USART_ICR_CMCF USART_ICR_CMCF: Character match clear flag

group USART_LL_EC_CLEAR_FLAG

Flags defines which can be used with LL_USART_WRITE_REG function.

Defines

LL_USART_ICR_PECF USART_ICR_PECF: Parity error clear flag

LL_USART_ICR_FECF USART_ICR_FECF: Framing error clear flag

LL_USART_ICR_NECF USART_ICR_NECF: Noise error detected clear flag

LL_USART_ICR_ORECF USART_ICR_ORECF: Overrun error clear flag

LL_USART_ICR_IDLECF USART_ICR_IDLECF: Idle line detected clear flag

LL_USART_ICR_TXFECF USART_ICR_TXFECF: TX FIFO Empty clear flag

LL_USART_ICR_TCCF USART_ICR_TCCF: Transmission complete clear flag

LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF: Transmission completed before guard time clear flag

LL_USART_ICR_LBDCF USART_ICR_LBDCF: LIN break detection clear flag

LL_USART_ICR_CTSCF USART_ICR_CTSCF: CTS clear flag

LL_USART_ICR_RTOCF USART_ICR_RTOCF: Receiver timeout clear flag

LL_USART_ICR_EOBCF USART_ICR_EOBCF: End of block clear flag

LL_USART_ICR_UDRCF USART_ICR_UDRCF: SPI Slave Underrun clear flag

LL_USART_ICR_CMCF USART_ICR_CMCF: Character match clear flag

Get Flags Defines ¶

group USART_LL_EC_GET_FLAG

Flags defines which can be used with LL_USART_READ_REG function.

Defines

LL_USART_ISR_PE USART_ISR_PE ¶: Parity error flag

LL_USART_ISR_FE USART_ISR_FE ¶: Framing error flag

LL_USART_ISR_NE USART_ISR_NE ¶: Noise detected flag

LL_USART_ISR_ORE USART_ISR_ORE ¶: Overrun error flag

LL_USART_ISR_IDLE USART_ISR_IDLE ¶: Idle line detected flag

LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE ¶: Read data register or RX FIFO not empty flag

LL_USART_ISR_TC USART_ISR_TC ¶: Transmission complete flag

LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF ¶: Transmit data register empty or TX FIFO Not Full flag

LL_USART_ISR_LBDF USART_ISR_LBDF ¶: LIN break detection flag

LL_USART_ISR_CTSIF USART_ISR_CTSIF ¶: CTS interrupt flag

LL_USART_ISR_CTS USART_ISR_CTS ¶: CTS flag

LL_USART_ISR_RTOF USART_ISR_RTOF ¶: Receiver timeout flag

LL_USART_ISR_EOBF USART_ISR_EOBF ¶: End of block flag

LL_USART_ISR_UDR USART_ISR_UDR ¶: SPI Slave underrun error flag

LL_USART_ISR_ABRE USART_ISR_ABRE ¶: Auto baud rate error flag

LL_USART_ISR_ABRF USART_ISR_ABRF ¶: Auto baud rate flag

LL_USART_ISR_BUSY USART_ISR_BUSY ¶: Busy flag

LL_USART_ISR_CMF USART_ISR_CMF ¶: Character match flag

LL_USART_ISR_SBKF USART_ISR_SBKF ¶: Send break flag

LL_USART_ISR_RWU USART_ISR_RWU ¶: Receiver wakeup from Mute mode flag

LL_USART_ISR_TEACK USART_ISR_TEACK ¶: Transmit enable acknowledge flag

LL_USART_ISR_REACK USART_ISR_REACK ¶: Receive enable acknowledge flag

LL_USART_ISR_TXFE USART_ISR_TXFE ¶: TX FIFO empty flag

LL_USART_ISR_RXFF USART_ISR_RXFF ¶: RX FIFO full flag

LL_USART_ISR_TCBGT USART_ISR_TCBGT ¶: Transmission complete before guard time completion flag

LL_USART_ISR_RXFT USART_ISR_RXFT ¶: RX FIFO threshold flag

LL_USART_ISR_TXFT USART_ISR_TXFT ¶: TX FIFO threshold flag

group USART_LL_EC_GET_FLAG

Flags defines which can be used with LL_USART_READ_REG function.

Defines

LL_USART_ISR_PE USART_ISR_PE: Parity error flag

LL_USART_ISR_FE USART_ISR_FE: Framing error flag

LL_USART_ISR_NE USART_ISR_NE: Noise detected flag

LL_USART_ISR_ORE USART_ISR_ORE: Overrun error flag

LL_USART_ISR_IDLE USART_ISR_IDLE: Idle line detected flag

LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE: Read data register or RX FIFO not empty flag

LL_USART_ISR_TC USART_ISR_TC: Transmission complete flag

LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF: Transmit data register empty or TX FIFO Not Full flag

LL_USART_ISR_LBDF USART_ISR_LBDF: LIN break detection flag

LL_USART_ISR_CTSIF USART_ISR_CTSIF: CTS interrupt flag

LL_USART_ISR_CTS USART_ISR_CTS: CTS flag

LL_USART_ISR_RTOF USART_ISR_RTOF: Receiver timeout flag

LL_USART_ISR_EOBF USART_ISR_EOBF: End of block flag

LL_USART_ISR_UDR USART_ISR_UDR: SPI Slave underrun error flag

LL_USART_ISR_ABRE USART_ISR_ABRE: Auto baud rate error flag

LL_USART_ISR_ABRF USART_ISR_ABRF: Auto baud rate flag

LL_USART_ISR_BUSY USART_ISR_BUSY: Busy flag

LL_USART_ISR_CMF USART_ISR_CMF: Character match flag

LL_USART_ISR_SBKF USART_ISR_SBKF: Send break flag

LL_USART_ISR_RWU USART_ISR_RWU: Receiver wakeup from Mute mode flag

LL_USART_ISR_TEACK USART_ISR_TEACK: Transmit enable acknowledge flag

LL_USART_ISR_REACK USART_ISR_REACK: Receive enable acknowledge flag

LL_USART_ISR_TXFE USART_ISR_TXFE: TX FIFO empty flag

LL_USART_ISR_RXFF USART_ISR_RXFF: RX FIFO full flag

LL_USART_ISR_TCBGT USART_ISR_TCBGT: Transmission complete before guard time completion flag

LL_USART_ISR_RXFT USART_ISR_RXFT: RX FIFO threshold flag

LL_USART_ISR_TXFT USART_ISR_TXFT: TX FIFO threshold flag

group USART_LL_EC_GET_FLAG

Flags defines which can be used with LL_USART_READ_REG function.

Defines

LL_USART_ISR_PE USART_ISR_PE: Parity error flag

LL_USART_ISR_FE USART_ISR_FE: Framing error flag

LL_USART_ISR_NE USART_ISR_NE: Noise detected flag

LL_USART_ISR_ORE USART_ISR_ORE: Overrun error flag

LL_USART_ISR_IDLE USART_ISR_IDLE: Idle line detected flag

LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE: Read data register or RX FIFO not empty flag

LL_USART_ISR_TC USART_ISR_TC: Transmission complete flag

LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF: Transmit data register empty or TX FIFO Not Full flag

LL_USART_ISR_LBDF USART_ISR_LBDF: LIN break detection flag

LL_USART_ISR_CTSIF USART_ISR_CTSIF: CTS interrupt flag

LL_USART_ISR_CTS USART_ISR_CTS: CTS flag

LL_USART_ISR_RTOF USART_ISR_RTOF: Receiver timeout flag

LL_USART_ISR_EOBF USART_ISR_EOBF: End of block flag

LL_USART_ISR_UDR USART_ISR_UDR: SPI Slave underrun error flag

LL_USART_ISR_ABRE USART_ISR_ABRE: Auto baud rate error flag

LL_USART_ISR_ABRF USART_ISR_ABRF: Auto baud rate flag

LL_USART_ISR_BUSY USART_ISR_BUSY: Busy flag

LL_USART_ISR_CMF USART_ISR_CMF: Character match flag

LL_USART_ISR_SBKF USART_ISR_SBKF: Send break flag

LL_USART_ISR_RWU USART_ISR_RWU: Receiver wakeup from Mute mode flag

LL_USART_ISR_TEACK USART_ISR_TEACK: Transmit enable acknowledge flag

LL_USART_ISR_REACK USART_ISR_REACK: Receive enable acknowledge flag

LL_USART_ISR_TXFE USART_ISR_TXFE: TX FIFO empty flag

LL_USART_ISR_RXFF USART_ISR_RXFF: RX FIFO full flag

LL_USART_ISR_TCBGT USART_ISR_TCBGT: Transmission complete before guard time completion flag

LL_USART_ISR_RXFT USART_ISR_RXFT: RX FIFO threshold flag

LL_USART_ISR_TXFT USART_ISR_TXFT: TX FIFO threshold flag

IT Defines ¶

group USART_LL_EC_IT

IT defines which can be used with LL_USART_READ_REG and LL_USART_WRITE_REG functions.

Defines

LL_USART_CR1_IDLEIE USART_CR1_IDLEIE ¶: IDLE interrupt enable

LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE ¶: Read data register and RXFIFO not empty interrupt enable

LL_USART_CR1_TCIE USART_CR1_TCIE ¶: Transmission complete interrupt enable

LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE ¶: Transmit data register empty and TX FIFO not full interrupt enable

LL_USART_CR1_PEIE USART_CR1_PEIE ¶: Parity error interrupt enable

LL_USART_CR1_CMIE USART_CR1_CMIE ¶: Character match interrupt enable

LL_USART_CR1_RTOIE USART_CR1_RTOIE ¶: Receiver timeout interrupt enable

LL_USART_CR1_EOBIE USART_CR1_EOBIE ¶: End of Block interrupt enable

LL_USART_CR1_TXFEIE USART_CR1_TXFEIE ¶: TX FIFO empty interrupt enable

LL_USART_CR1_RXFFIE USART_CR1_RXFFIE ¶: RX FIFO full interrupt enable

LL_USART_CR2_LBDIE USART_CR2_LBDIE ¶: LIN break detection interrupt enable

LL_USART_CR3_EIE USART_CR3_EIE ¶: Error interrupt enable

LL_USART_CR3_CTSIE USART_CR3_CTSIE ¶: CTS interrupt enable

LL_USART_CR3_TXFTIE USART_CR3_TXFTIE ¶: TX FIFO threshold interrupt enable

LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE ¶: Transmission complete before guard time interrupt enable

LL_USART_CR3_RXFTIE USART_CR3_RXFTIE ¶: RX FIFO threshold interrupt enable

group USART_LL_EC_IT

IT defines which can be used with LL_USART_READ_REG and LL_USART_WRITE_REG functions.

Defines

LL_USART_CR1_IDLEIE USART_CR1_IDLEIE: IDLE interrupt enable

LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE: Read data register and RXFIFO not empty interrupt enable

LL_USART_CR1_TCIE USART_CR1_TCIE: Transmission complete interrupt enable

LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE: Transmit data register empty and TX FIFO not full interrupt enable

LL_USART_CR1_PEIE USART_CR1_PEIE: Parity error interrupt enable

LL_USART_CR1_CMIE USART_CR1_CMIE: Character match interrupt enable

LL_USART_CR1_RTOIE USART_CR1_RTOIE: Receiver timeout interrupt enable

LL_USART_CR1_EOBIE USART_CR1_EOBIE: End of Block interrupt enable

LL_USART_CR1_TXFEIE USART_CR1_TXFEIE: TX FIFO empty interrupt enable

LL_USART_CR1_RXFFIE USART_CR1_RXFFIE: RX FIFO full interrupt enable

LL_USART_CR2_LBDIE USART_CR2_LBDIE: LIN break detection interrupt enable

LL_USART_CR3_EIE USART_CR3_EIE: Error interrupt enable

LL_USART_CR3_CTSIE USART_CR3_CTSIE: CTS interrupt enable

LL_USART_CR3_TXFTIE USART_CR3_TXFTIE: TX FIFO threshold interrupt enable

LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE: Transmission complete before guard time interrupt enable

LL_USART_CR3_RXFTIE USART_CR3_RXFTIE: RX FIFO threshold interrupt enable

group USART_LL_EC_IT

IT defines which can be used with LL_USART_READ_REG and LL_USART_WRITE_REG functions.

Defines

LL_USART_CR1_IDLEIE USART_CR1_IDLEIE: IDLE interrupt enable

LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE: Read data register and RXFIFO not empty interrupt enable

LL_USART_CR1_TCIE USART_CR1_TCIE: Transmission complete interrupt enable

LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE: Transmit data register empty and TX FIFO not full interrupt enable

LL_USART_CR1_PEIE USART_CR1_PEIE: Parity error interrupt enable

LL_USART_CR1_CMIE USART_CR1_CMIE: Character match interrupt enable

LL_USART_CR1_RTOIE USART_CR1_RTOIE: Receiver timeout interrupt enable

LL_USART_CR1_EOBIE USART_CR1_EOBIE: End of Block interrupt enable

LL_USART_CR1_TXFEIE USART_CR1_TXFEIE: TX FIFO empty interrupt enable

LL_USART_CR1_RXFFIE USART_CR1_RXFFIE: RX FIFO full interrupt enable

LL_USART_CR2_LBDIE USART_CR2_LBDIE: LIN break detection interrupt enable

LL_USART_CR3_EIE USART_CR3_EIE: Error interrupt enable

LL_USART_CR3_CTSIE USART_CR3_CTSIE: CTS interrupt enable

LL_USART_CR3_TXFTIE USART_CR3_TXFTIE: TX FIFO threshold interrupt enable

LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE: Transmission complete before guard time interrupt enable

LL_USART_CR3_RXFTIE USART_CR3_RXFTIE: RX FIFO threshold interrupt enable

FIFO Threshold ¶

group USART_LL_EC_FIFOTHRESHOLD

Defines

LL_USART_FIFO_THRESHOLD_1_8 0x00000000U ¶: FIFO reaches 1/8 of its depth

LL_USART_FIFO_THRESHOLD_1_4 0x00000001U ¶: FIFO reaches 1/4 of its depth

LL_USART_FIFO_THRESHOLD_1_2 0x00000002U ¶: FIFO reaches 1/2 of its depth

LL_USART_FIFO_THRESHOLD_3_4 0x00000003U ¶: FIFO reaches 3/4 of its depth

LL_USART_FIFO_THRESHOLD_7_8 0x00000004U ¶: FIFO reaches 7/8 of its depth

LL_USART_FIFO_THRESHOLD_8_8 0x00000005U ¶: FIFO becomes empty for TX and full for RX

group USART_LL_EC_FIFOTHRESHOLD

Defines

LL_USART_FIFO_THRESHOLD_1_8 0x00000000U: FIFO reaches 1/8 of its depth

LL_USART_FIFO_THRESHOLD_1_4 0x00000001U: FIFO reaches 1/4 of its depth

LL_USART_FIFO_THRESHOLD_1_2 0x00000002U: FIFO reaches 1/2 of its depth

LL_USART_FIFO_THRESHOLD_3_4 0x00000003U: FIFO reaches 3/4 of its depth

LL_USART_FIFO_THRESHOLD_7_8 0x00000004U: FIFO reaches 7/8 of its depth

LL_USART_FIFO_THRESHOLD_8_8 0x00000005U: FIFO becomes empty for TX and full for RX

group USART_LL_EC_FIFOTHRESHOLD

Defines

LL_USART_FIFO_THRESHOLD_1_8 0x00000000U: FIFO reaches 1/8 of its depth

LL_USART_FIFO_THRESHOLD_1_4 0x00000001U: FIFO reaches 1/4 of its depth

LL_USART_FIFO_THRESHOLD_1_2 0x00000002U: FIFO reaches 1/2 of its depth

LL_USART_FIFO_THRESHOLD_3_4 0x00000003U: FIFO reaches 3/4 of its depth

LL_USART_FIFO_THRESHOLD_7_8 0x00000004U: FIFO reaches 7/8 of its depth

LL_USART_FIFO_THRESHOLD_8_8 0x00000005U: FIFO becomes empty for TX and full for RX

Communication Direction ¶

group USART_LL_EC_DIRECTION

Defines

LL_USART_DIRECTION_NONE 0x00000000U ¶: Transmitter and Receiver are disabled

LL_USART_DIRECTION_RX USART_CR1_RE ¶: Transmitter is disabled and Receiver is enabled

LL_USART_DIRECTION_TX USART_CR1_TE ¶: Transmitter is enabled and Receiver is disabled

LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) ¶: Transmitter and Receiver are enabled

group USART_LL_EC_DIRECTION

Defines

LL_USART_DIRECTION_NONE 0x00000000U: Transmitter and Receiver are disabled

LL_USART_DIRECTION_RX USART_CR1_RE: Transmitter is disabled and Receiver is enabled

LL_USART_DIRECTION_TX USART_CR1_TE: Transmitter is enabled and Receiver is disabled

LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE): Transmitter and Receiver are enabled

group USART_LL_EC_DIRECTION

Defines

LL_USART_DIRECTION_NONE 0x00000000U: Transmitter and Receiver are disabled

LL_USART_DIRECTION_RX USART_CR1_RE: Transmitter is disabled and Receiver is enabled

LL_USART_DIRECTION_TX USART_CR1_TE: Transmitter is enabled and Receiver is disabled

LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE): Transmitter and Receiver are enabled

Parity Control ¶

group USART_LL_EC_PARITY

Defines

LL_USART_PARITY_NONE 0x00000000U ¶: Parity control disabled

LL_USART_PARITY_EVEN USART_CR1_PCE ¶: Parity control enabled and Even Parity is selected

LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) ¶: Parity control enabled and Odd Parity is selected

Wakeup ¶

group USART_LL_EC_WAKEUP

Defines

LL_USART_WAKEUP_METHOD_IDLE_LINE 0x00000000U ¶: USART wake up from Mute mode on Idle Line

LL_USART_WAKEUP_METHOD_ADDRESS_MARK USART_CR1_WAKE ¶: USART wake up from Mute mode on Address Mark

Datawidth ¶

group USART_LL_EC_DATAWIDTH

Defines

LL_USART_DATAWIDTH_7_BIT USART_CR1_M1 ¶: 7 bit word length : Start bit, 7 data bits, n stop bits

LL_USART_DATAWIDTH_8_BIT 0x00000000U ¶: 8 bit word length : Start bit, 8 data bits, n stop bits

LL_USART_DATAWIDTH_9_BIT USART_CR1_M0 ¶: 9 bit word length : Start bit, 9 data bits, n stop bits

Oversampling ¶

group USART_LL_EC_OVERSAMPLING

Defines

LL_USART_OVERSAMPLING_16 0x00000000U ¶: Oversampling by 16

LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 ¶: Oversampling by 8

Last Clock Pulse ¶

group USART_LL_EC_LASTCLKPULSE

Defines

LL_USART_LASTCLKPULSE_DISABLED 0x00000000U ¶: The clock pulse of the last data bit is not output to the SCLK pin

LL_USART_LASTCLKPULSE_ENABLED USART_CR2_LBCL ¶: The clock pulse of the last data bit is output to the SCLK pin

Clock Output ¶

group USART_LL_EC_CLOCKOUTPUT

Defines

LL_USART_CLOCK_OUTPUT_DISABLED 0x00000000U ¶: The clock signal output is disabled

LL_USART_CLOCK_OUTPUT_ENABLED USART_CR2_CLKEN ¶: The clock signal output is enabled

Clock Phase ¶

group USART_LL_EC_PHASE

Defines

LL_USART_PHASE_1_EDGE 0x00000000U ¶: The first clock transition is the first data capture edge

LL_USART_PHASE_2_EDGE USART_CR2_CPHA ¶: The second clock transition is the first data capture edge

Clock Polarity ¶

group USART_LL_EC_POLARITY

Defines

LL_USART_POLARITY_LOW 0x00000000U ¶: Steady low value on SCLK pin outside transmission window

LL_USART_POLARITY_HIGH USART_CR2_CPOL ¶: Steady high value on SCLK pin outside transmission window

Clock Source Prescaler ¶

group USART_LL_EC_PRESCALER

Defines

LL_USART_PRESCALER_DIV1 0x00000000U ¶: Input clock not divided

LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) ¶: Input clock divided by 2

LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) ¶: Input clock divided by 4

LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) ¶: Input clock divided by 6

LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) ¶: Input clock divided by 8

LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) ¶: Input clock divided by 10

LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) ¶: Input clock divided by 12

LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) ¶: Input clock divided by 16

LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) ¶: Input clock divided by 32

LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) ¶: Input clock divided by 64

LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) ¶: Input clock divided by 128

LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) ¶: Input clock divided by 256

group USART_LL_EC_PRESCALER

Defines

LL_USART_PRESCALER_DIV1 0x00000000U: Input clock not divided

LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0): Input clock divided by 2

LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1): Input clock divided by 4

LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0): Input clock divided by 6

LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2): Input clock divided by 8

LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0): Input clock divided by 10

LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1): Input clock divided by 12

LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0): Input clock divided by 16

LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3): Input clock divided by 32

LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0): Input clock divided by 64

LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1): Input clock divided by 128

LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0): Input clock divided by 256

group USART_LL_EC_PRESCALER

Defines

LL_USART_PRESCALER_DIV1 0x00000000U: Input clock not divided

LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0): Input clock divided by 2

LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1): Input clock divided by 4

LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0): Input clock divided by 6

LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2): Input clock divided by 8

LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0): Input clock divided by 10

LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1): Input clock divided by 12

LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0): Input clock divided by 16

LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3): Input clock divided by 32

LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0): Input clock divided by 64

LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1): Input clock divided by 128

LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0): Input clock divided by 256

SMARTCARD Clock Prescaler ¶

group SMARTCARD_LL_EC_PRESCALER

Defines

LL_USART_SMARTCARD_PRESCALER_DIV2 (0x00000001U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /2

LL_USART_SMARTCARD_PRESCALER_DIV4 (0x00000002U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /4

LL_USART_SMARTCARD_PRESCALER_DIV6 (0x00000003U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /6

LL_USART_SMARTCARD_PRESCALER_DIV8 (0x00000004U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /8

LL_USART_SMARTCARD_PRESCALER_DIV10 (0x00000005U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /10

LL_USART_SMARTCARD_PRESCALER_DIV12 (0x00000006U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /12

LL_USART_SMARTCARD_PRESCALER_DIV14 (0x00000007U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /14

LL_USART_SMARTCARD_PRESCALER_DIV16 (0x00000008U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /16

LL_USART_SMARTCARD_PRESCALER_DIV18 (0x00000009U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /18

LL_USART_SMARTCARD_PRESCALER_DIV20 (0x00000010U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /20

LL_USART_SMARTCARD_PRESCALER_DIV22 (0x00000011U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /22

LL_USART_SMARTCARD_PRESCALER_DIV24 (0x00000012U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /24

LL_USART_SMARTCARD_PRESCALER_DIV26 (0x00000013U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /26

LL_USART_SMARTCARD_PRESCALER_DIV28 (0x00000014U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /28

LL_USART_SMARTCARD_PRESCALER_DIV30 (0x00000015U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /30

LL_USART_SMARTCARD_PRESCALER_DIV32 (0x00000016U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /32

LL_USART_SMARTCARD_PRESCALER_DIV34 (0x00000017U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /34

LL_USART_SMARTCARD_PRESCALER_DIV36 (0x00000018U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /36

LL_USART_SMARTCARD_PRESCALER_DIV38 (0x00000019U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /38

LL_USART_SMARTCARD_PRESCALER_DIV40 (0x00000020U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /40

LL_USART_SMARTCARD_PRESCALER_DIV42 (0x00000021U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /42

LL_USART_SMARTCARD_PRESCALER_DIV44 (0x00000022U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /44

LL_USART_SMARTCARD_PRESCALER_DIV46 (0x00000023U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /46

LL_USART_SMARTCARD_PRESCALER_DIV48 (0x00000024U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /48

LL_USART_SMARTCARD_PRESCALER_DIV50 (0x00000025U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /50

LL_USART_SMARTCARD_PRESCALER_DIV52 (0x00000026U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /52

LL_USART_SMARTCARD_PRESCALER_DIV54 (0x00000027U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /54

LL_USART_SMARTCARD_PRESCALER_DIV56 (0x00000028U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /56

LL_USART_SMARTCARD_PRESCALER_DIV58 (0x00000029U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /58

LL_USART_SMARTCARD_PRESCALER_DIV60 (0x00000030U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /60

LL_USART_SMARTCARD_PRESCALER_DIV62 (0x00000031U << USART_GTPR_PSC_Pos) ¶: SMARTCARD Output CLK /62

group SMARTCARD_LL_EC_PRESCALER

Defines

LL_USART_SMARTCARD_PRESCALER_DIV2 (0x00000001U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /2

LL_USART_SMARTCARD_PRESCALER_DIV4 (0x00000002U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /4

LL_USART_SMARTCARD_PRESCALER_DIV6 (0x00000003U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /6

LL_USART_SMARTCARD_PRESCALER_DIV8 (0x00000004U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /8

LL_USART_SMARTCARD_PRESCALER_DIV10 (0x00000005U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /10

LL_USART_SMARTCARD_PRESCALER_DIV12 (0x00000006U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /12

LL_USART_SMARTCARD_PRESCALER_DIV14 (0x00000007U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /14

LL_USART_SMARTCARD_PRESCALER_DIV16 (0x00000008U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /16

LL_USART_SMARTCARD_PRESCALER_DIV18 (0x00000009U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /18

LL_USART_SMARTCARD_PRESCALER_DIV20 (0x00000010U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /20

LL_USART_SMARTCARD_PRESCALER_DIV22 (0x00000011U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /22

LL_USART_SMARTCARD_PRESCALER_DIV24 (0x00000012U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /24

LL_USART_SMARTCARD_PRESCALER_DIV26 (0x00000013U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /26

LL_USART_SMARTCARD_PRESCALER_DIV28 (0x00000014U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /28

LL_USART_SMARTCARD_PRESCALER_DIV30 (0x00000015U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /30

LL_USART_SMARTCARD_PRESCALER_DIV32 (0x00000016U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /32

LL_USART_SMARTCARD_PRESCALER_DIV34 (0x00000017U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /34

LL_USART_SMARTCARD_PRESCALER_DIV36 (0x00000018U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /36

LL_USART_SMARTCARD_PRESCALER_DIV38 (0x00000019U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /38

LL_USART_SMARTCARD_PRESCALER_DIV40 (0x00000020U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /40

LL_USART_SMARTCARD_PRESCALER_DIV42 (0x00000021U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /42

LL_USART_SMARTCARD_PRESCALER_DIV44 (0x00000022U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /44

LL_USART_SMARTCARD_PRESCALER_DIV46 (0x00000023U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /46

LL_USART_SMARTCARD_PRESCALER_DIV48 (0x00000024U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /48

LL_USART_SMARTCARD_PRESCALER_DIV50 (0x00000025U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /50

LL_USART_SMARTCARD_PRESCALER_DIV52 (0x00000026U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /52

LL_USART_SMARTCARD_PRESCALER_DIV54 (0x00000027U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /54

LL_USART_SMARTCARD_PRESCALER_DIV56 (0x00000028U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /56

LL_USART_SMARTCARD_PRESCALER_DIV58 (0x00000029U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /58

LL_USART_SMARTCARD_PRESCALER_DIV60 (0x00000030U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /60

LL_USART_SMARTCARD_PRESCALER_DIV62 (0x00000031U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /62

group SMARTCARD_LL_EC_PRESCALER

Defines

LL_USART_SMARTCARD_PRESCALER_DIV2 (0x00000001U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /2

LL_USART_SMARTCARD_PRESCALER_DIV4 (0x00000002U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /4

LL_USART_SMARTCARD_PRESCALER_DIV6 (0x00000003U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /6

LL_USART_SMARTCARD_PRESCALER_DIV8 (0x00000004U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /8

LL_USART_SMARTCARD_PRESCALER_DIV10 (0x00000005U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /10

LL_USART_SMARTCARD_PRESCALER_DIV12 (0x00000006U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /12

LL_USART_SMARTCARD_PRESCALER_DIV14 (0x00000007U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /14

LL_USART_SMARTCARD_PRESCALER_DIV16 (0x00000008U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /16

LL_USART_SMARTCARD_PRESCALER_DIV18 (0x00000009U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /18

LL_USART_SMARTCARD_PRESCALER_DIV20 (0x00000010U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /20

LL_USART_SMARTCARD_PRESCALER_DIV22 (0x00000011U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /22

LL_USART_SMARTCARD_PRESCALER_DIV24 (0x00000012U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /24

LL_USART_SMARTCARD_PRESCALER_DIV26 (0x00000013U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /26

LL_USART_SMARTCARD_PRESCALER_DIV28 (0x00000014U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /28

LL_USART_SMARTCARD_PRESCALER_DIV30 (0x00000015U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /30

LL_USART_SMARTCARD_PRESCALER_DIV32 (0x00000016U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /32

LL_USART_SMARTCARD_PRESCALER_DIV34 (0x00000017U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /34

LL_USART_SMARTCARD_PRESCALER_DIV36 (0x00000018U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /36

LL_USART_SMARTCARD_PRESCALER_DIV38 (0x00000019U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /38

LL_USART_SMARTCARD_PRESCALER_DIV40 (0x00000020U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /40

LL_USART_SMARTCARD_PRESCALER_DIV42 (0x00000021U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /42

LL_USART_SMARTCARD_PRESCALER_DIV44 (0x00000022U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /44

LL_USART_SMARTCARD_PRESCALER_DIV46 (0x00000023U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /46

LL_USART_SMARTCARD_PRESCALER_DIV48 (0x00000024U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /48

LL_USART_SMARTCARD_PRESCALER_DIV50 (0x00000025U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /50

LL_USART_SMARTCARD_PRESCALER_DIV52 (0x00000026U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /52

LL_USART_SMARTCARD_PRESCALER_DIV54 (0x00000027U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /54

LL_USART_SMARTCARD_PRESCALER_DIV56 (0x00000028U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /56

LL_USART_SMARTCARD_PRESCALER_DIV58 (0x00000029U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /58

LL_USART_SMARTCARD_PRESCALER_DIV60 (0x00000030U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /60

LL_USART_SMARTCARD_PRESCALER_DIV62 (0x00000031U << USART_GTPR_PSC_Pos): SMARTCARD Output CLK /62

Stop Bits ¶

group USART_LL_EC_STOPBITS

Defines

LL_USART_STOP_BIT_0_5 USART_CR2_STOP_0 ¶: 0.5 stop bit

LL_USART_STOP_BIT_1 0x00000000U ¶: 1 stop bit

LL_USART_STOP_BIT_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) ¶: 1.5 stop bits

LL_USART_STOP_BIT_2 USART_CR2_STOP_1 ¶: 2 stop bits

group USART_LL_EC_STOPBITS

Defines

LL_USART_STOP_BIT_0_5 USART_CR2_STOP_0: 0.5 stop bit

LL_USART_STOP_BIT_1 0x00000000U: 1 stop bit

LL_USART_STOP_BIT_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1): 1.5 stop bits

LL_USART_STOP_BIT_2 USART_CR2_STOP_1: 2 stop bits

group USART_LL_EC_STOPBITS

Defines

LL_USART_STOP_BIT_0_5 USART_CR2_STOP_0: 0.5 stop bit

LL_USART_STOP_BIT_1 0x00000000U: 1 stop bit

LL_USART_STOP_BIT_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1): 1.5 stop bits

LL_USART_STOP_BIT_2 USART_CR2_STOP_1: 2 stop bits

TX RX Pins Swap ¶

group USART_LL_EC_TXRX

Defines

LL_USART_TXRX_STANDARD 0x00000000U ¶: TX and RX pins are used as defined in standard pinout

LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) ¶: TX and RX pins functions are swapped.

RX Pin Active Level Inversion ¶

group USART_LL_EC_RXPIN_LEVEL

Defines

LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U ¶: RX pin signal works using the standard logic levels

LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) ¶: RX pin signal values are inverted.

TX Pin Active Level Inversion ¶

group USART_LL_EC_TXPIN_LEVEL

Defines

LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U ¶: TX pin signal works using the standard logic levels

LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) ¶: TX pin signal values are inverted.

Binary Data Inversion ¶

group USART_LL_EC_BINARY_LOGIC

Defines

LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U ¶: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV ¶: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Bit Order ¶

group USART_LL_EC_BITORDER

Defines

LL_USART_BITORDER_LSB_FIRST 0x00000000U ¶: data is transmitted/received with data bit 0 first, following the start bit

LL_USART_BITORDER_MSB_FIRST USART_CR2_MSBFIRST ¶: data is transmitted/received with the MSB first, following the start bit

Autobaud Detection ¶

group USART_LL_EC_AUTOBAUD_DETECT_ON

Defines

LL_USART_AUTO_BAUD_DETECT_ON_START_BIT 0x00000000U ¶: Measurement of the start bit is used to detect the baud rate

LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE USART_CR2_ABRMODE_0 ¶: Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME USART_CR2_ABRMODE_1 ¶: 0x7F frame detection

LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) ¶: 0x55 frame detection

group USART_LL_EC_AUTOBAUD_DETECT_ON

Defines

LL_USART_AUTO_BAUD_DETECT_ON_START_BIT 0x00000000U: Measurement of the start bit is used to detect the baud rate

LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE USART_CR2_ABRMODE_0: Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME USART_CR2_ABRMODE_1: 0x7F frame detection

LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0): 0x55 frame detection

group USART_LL_EC_AUTOBAUD_DETECT_ON

Defines

LL_USART_AUTO_BAUD_DETECT_ON_START_BIT 0x00000000U: Measurement of the start bit is used to detect the baud rate

LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE USART_CR2_ABRMODE_0: Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME USART_CR2_ABRMODE_1: 0x7F frame detection

LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0): 0x55 frame detection

Address Length Detection ¶

group USART_LL_EC_ADDRESS_DETECT

Defines

LL_USART_ADDRESS_DETECT_4_BIT 0x00000000U ¶: 4-bit address detection method selected

LL_USART_ADDRESS_DETECT_7_BIT USART_CR2_ADDM7 ¶: 7-bit address detection (in 8-bit data mode) method selected

Hardware Control ¶

group USART_LL_EC_HWCONTROL

Defines

LL_USART_HWCONTROL_NONE 0x00000000U ¶: CTS and RTS hardware flow control disabled

LL_USART_HWCONTROL_RTS USART_CR3_RTSE ¶: RTS output enabled, data is only requested when there is space in the receive buffer

LL_USART_HWCONTROL_CTS USART_CR3_CTSE ¶: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) ¶: CTS and RTS hardware flow control enabled

group USART_LL_EC_HWCONTROL

Defines

LL_USART_HWCONTROL_NONE 0x00000000U: CTS and RTS hardware flow control disabled

LL_USART_HWCONTROL_RTS USART_CR3_RTSE: RTS output enabled, data is only requested when there is space in the receive buffer

LL_USART_HWCONTROL_CTS USART_CR3_CTSE: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE): CTS and RTS hardware flow control enabled

group USART_LL_EC_HWCONTROL

Defines

LL_USART_HWCONTROL_NONE 0x00000000U: CTS and RTS hardware flow control disabled

LL_USART_HWCONTROL_RTS USART_CR3_RTSE: RTS output enabled, data is only requested when there is space in the receive buffer

LL_USART_HWCONTROL_CTS USART_CR3_CTSE: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE): CTS and RTS hardware flow control enabled

IrDA Power ¶

group USART_LL_EC_IRDA_POWER

Defines

LL_USART_IRDA_POWER_MODE_NORMAL 0x00000000U ¶: IrDA normal power mode

LL_USART_IRDA_POWER_MODE_LOW USART_CR3_IRLP ¶: IrDA low power mode

LIN Break Detection Length ¶

group USART_LL_EC_LINBREAK_DETECT

Defines

LL_USART_LIN_BREAK_DETECT_10_BIT 0x00000000U ¶: 10-bit break detection method selected

LL_USART_LIN_BREAK_DETECT_11_BIT USART_CR2_LBDL ¶: 11-bit break detection method selected

Driver Enable Polarity ¶

group USART_LL_EC_DE_POLARITY

Defines

LL_USART_DE_POLARITY_HIGH 0x00000000U ¶: DE signal is active high

LL_USART_DE_POLARITY_LOW USART_CR3_DEP ¶: DE signal is active low

DMA Register Data ¶

group USART_LL_EC_DMA_REG_DATA

Defines

LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U ¶: Get address of data register used for transmission

LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U ¶: Get address of data register used for reception

Autonomous Mode Trigger Selection ¶

group USART_LL_EC_AUTOCR_TRIGSEL

USART Autonomous Trigger selection.

Defines

LL_USART_TRIG_GPDMA1_CH0_TC (uint32_t)(0U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART GPDMA1 channel0 Internal Trigger

LL_USART_TRIG_GPDMA1_CH1_TC (uint32_t)(1U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART GPDMA1 channel1 Internal Trigger

LL_USART_TRIG_GPDMA1_CH2_TC (uint32_t)(2U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART GPDMA1 channel2 Internal Trigger

LL_USART_TRIG_GPDMA1_CH3_TC (uint32_t)(3U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART GPDMA1 channel3 Internal Trigger

LL_USART_TRIG_EXTI6 (uint32_t)(4U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART EXTI line 6 Internal Trigger

LL_USART_TRIG_EXTI9 (uint32_t)(5U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART EXTI line 9 Internal Trigger

LL_USART_TRIG_LPTIM1_CH1 (uint32_t)(6U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART LPTIM1 channel1 Internal Trigger

LL_USART_TRIG_LPTIM2_CH1 (uint32_t)(7U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART LPTIM2 channel1 Internal Trigger

LL_USART_TRIG_COMP1_OUT (uint32_t)(8U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART COMP1 out Internal Trigger

LL_USART_TRIG_COMP2_OUT (uint32_t)(9U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART COMP2 out Internal Trigger

LL_USART_TRIG_RTC_ALRA_TRG (uint32_t)(10U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART RTC alarm Internal Trigger

LL_USART_TRIG_RTC_WUT_TRG (uint32_t)(11U << USART_AUTOCR_TRIGSEL_Pos) ¶: USART RTC wakeup Internal Trigger

group USART_LL_EC_AUTOCR_TRIGSEL

USART Autonomous Trigger selection.

Defines

LL_USART_TRIG_GPDMA1_CH0_TC (uint32_t)(0U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel0 Internal Trigger

LL_USART_TRIG_GPDMA1_CH1_TC (uint32_t)(1U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel1 Internal Trigger

LL_USART_TRIG_GPDMA1_CH2_TC (uint32_t)(2U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel2 Internal Trigger

LL_USART_TRIG_GPDMA1_CH3_TC (uint32_t)(3U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel3 Internal Trigger

LL_USART_TRIG_EXTI6 (uint32_t)(4U << USART_AUTOCR_TRIGSEL_Pos): USART EXTI line 6 Internal Trigger

LL_USART_TRIG_EXTI9 (uint32_t)(5U << USART_AUTOCR_TRIGSEL_Pos): USART EXTI line 9 Internal Trigger

LL_USART_TRIG_LPTIM1_CH1 (uint32_t)(6U << USART_AUTOCR_TRIGSEL_Pos): USART LPTIM1 channel1 Internal Trigger

LL_USART_TRIG_LPTIM2_CH1 (uint32_t)(7U << USART_AUTOCR_TRIGSEL_Pos): USART LPTIM2 channel1 Internal Trigger

LL_USART_TRIG_COMP1_OUT (uint32_t)(8U << USART_AUTOCR_TRIGSEL_Pos): USART COMP1 out Internal Trigger

LL_USART_TRIG_COMP2_OUT (uint32_t)(9U << USART_AUTOCR_TRIGSEL_Pos): USART COMP2 out Internal Trigger

LL_USART_TRIG_RTC_ALRA_TRG (uint32_t)(10U << USART_AUTOCR_TRIGSEL_Pos): USART RTC alarm Internal Trigger

LL_USART_TRIG_RTC_WUT_TRG (uint32_t)(11U << USART_AUTOCR_TRIGSEL_Pos): USART RTC wakeup Internal Trigger

group USART_LL_EC_AUTOCR_TRIGSEL

USART Autonomous Trigger selection.

Defines

LL_USART_TRIG_GPDMA1_CH0_TC (uint32_t)(0U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel0 Internal Trigger

LL_USART_TRIG_GPDMA1_CH1_TC (uint32_t)(1U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel1 Internal Trigger

LL_USART_TRIG_GPDMA1_CH2_TC (uint32_t)(2U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel2 Internal Trigger

LL_USART_TRIG_GPDMA1_CH3_TC (uint32_t)(3U << USART_AUTOCR_TRIGSEL_Pos): USART GPDMA1 channel3 Internal Trigger

LL_USART_TRIG_EXTI6 (uint32_t)(4U << USART_AUTOCR_TRIGSEL_Pos): USART EXTI line 6 Internal Trigger

LL_USART_TRIG_EXTI9 (uint32_t)(5U << USART_AUTOCR_TRIGSEL_Pos): USART EXTI line 9 Internal Trigger

LL_USART_TRIG_LPTIM1_CH1 (uint32_t)(6U << USART_AUTOCR_TRIGSEL_Pos): USART LPTIM1 channel1 Internal Trigger

LL_USART_TRIG_LPTIM2_CH1 (uint32_t)(7U << USART_AUTOCR_TRIGSEL_Pos): USART LPTIM2 channel1 Internal Trigger

LL_USART_TRIG_COMP1_OUT (uint32_t)(8U << USART_AUTOCR_TRIGSEL_Pos): USART COMP1 out Internal Trigger

LL_USART_TRIG_RTC_ALRA_TRG (uint32_t)(10U << USART_AUTOCR_TRIGSEL_Pos): USART RTC alarm Internal Trigger

LL_USART_TRIG_RTC_WUT_TRG (uint32_t)(11U << USART_AUTOCR_TRIGSEL_Pos): USART RTC wakeup Internal Trigger

Autonomous Mode Trigger Polarity ¶

group USART_LL_EC_AUTOCR_TRIGPOL

USART Autonomous Trigger Polarity.

Defines

LL_USART_TRIG_POLARITY_RISING 0x00000000U ¶: USART triggered on rising edge

LL_USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL ¶: USART triggered on falling edge

Request ¶

group USART_LL_EC_Request

USART Request.

Defines

LL_USART_REQUEST_SEND_BREAK USART_RQR_SBKRQ ¶: Send Break Request

LL_USART_REQUEST_MUTE_MODE USART_RQR_MMRQ ¶: Mute Mode Request

LL_USART_REQUEST_RX_DATA_FLUSH USART_RQR_RXFRQ ¶: Receive Data flush Request

LL_USART_REQUEST_TX_DATA_FLUSH USART_RQR_TXFRQ ¶: Transmit Data flush Request

LL_USART_REQUEST_AUTO_BAUD_RATE USART_RQR_ABRRQ ¶: Auto Baud Rate Request

group USART_LL_EC_Request

USART Request.

Defines

LL_USART_REQUEST_SEND_BREAK USART_RQR_SBKRQ: Send Break Request

LL_USART_REQUEST_MUTE_MODE USART_RQR_MMRQ: Mute Mode Request

LL_USART_REQUEST_RX_DATA_FLUSH USART_RQR_RXFRQ: Receive Data flush Request

LL_USART_REQUEST_TX_DATA_FLUSH USART_RQR_TXFRQ: Transmit Data flush Request

LL_USART_REQUEST_AUTO_BAUD_RATE USART_RQR_ABRRQ: Auto Baud Rate Request

group USART_LL_EC_Request

USART Request.

Defines

LL_USART_REQUEST_SEND_BREAK USART_RQR_SBKRQ: Send Break Request

LL_USART_REQUEST_MUTE_MODE USART_RQR_MMRQ: Mute Mode Request

LL_USART_REQUEST_RX_DATA_FLUSH USART_RQR_RXFRQ: Receive Data flush Request

LL_USART_REQUEST_TX_DATA_FLUSH USART_RQR_TXFRQ: Transmit Data flush Request

LL_USART_REQUEST_AUTO_BAUD_RATE USART_RQR_ABRRQ: Auto Baud Rate Request

One Bit Sampling Enable ¶

group USART_LL_EC_One_Bit_Sampling

USART One Bit Sampling Enable.

Defines

LL_USART_ONE_BIT_SAMPLE_DISABLE 0x00000000U ¶

LL_USART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT ¶

LL_USART Interruptions Flag Mask ¶

group USART_LL_EC_Interruption_Mask

Defines

LL_USART_IT_MASK 0x001FU ¶: LL_USART interruptions flags mask

Slave Select ¶

group USART_LL_EC_Slave_Select

USART Slave Select.

Defines

LL_USART_NSS_IGNORED USART_CR2_DIS_NSS ¶

LL_USART_NSS_USED 0x00000000U ¶