LL DMA Constants ¶

Defines

LL_DMA_CHANNEL_0 0x00U ¶

LL DMA channel 0

LL_DMA_CHANNEL_1 0x01U ¶

LL DMA channel 1

LL_DMA_CHANNEL_2 0x02U ¶

LL DMA channel 2

LL_DMA_CHANNEL_3 0x03U ¶

LL DMA channel 3

LL_DMA_CHANNEL_4 0x04U ¶

LL DMA channel 4

LL_DMA_CHANNEL_5 0x05U ¶

LL DMA channel 5

LL_DMA_CHANNEL_6 0x06U ¶

LL DMA channel 6

LL_DMA_CHANNEL_7 0x07U ¶

LL DMA channel 7

LL_DMA_CHANNEL_8 0x08U ¶

LL DMA channel 8

LL_DMA_CHANNEL_9 0x09U ¶

LL DMA channel 9

LL_DMA_CHANNEL_10 0x0AU ¶

LL DMA channel 10

LL_DMA_CHANNEL_11 0x0BU ¶

LL DMA channel 11

LL_DMA_CHANNEL_12 0x0CU ¶

LL DMA channel 12

LL_DMA_CHANNEL_13 0x0DU ¶

LL DMA channel 13

LL_DMA_CHANNEL_14 0x0EU ¶

LL DMA channel 14

LL_DMA_CHANNEL_15 0x0FU ¶

LL DMA channel 15

Defines

LL_DMA_CHANNEL_0 0x00U

LL DMA channel 0

LL_DMA_CHANNEL_1 0x01U

LL DMA channel 1

LL_DMA_CHANNEL_2 0x02U

LL DMA channel 2

LL_DMA_CHANNEL_3 0x03U

LL DMA channel 3

LL_DMA_CHANNEL_4 0x04U

LL DMA channel 4

LL_DMA_CHANNEL_5 0x05U

LL DMA channel 5

LL_DMA_CHANNEL_6 0x06U

LL DMA channel 6

LL_DMA_CHANNEL_7 0x07U

LL DMA channel 7

LL_DMA_CHANNEL_8 0x08U

LL DMA channel 8

LL_DMA_CHANNEL_9 0x09U

LL DMA channel 9

LL_DMA_CHANNEL_10 0x0AU

LL DMA channel 10

LL_DMA_CHANNEL_11 0x0BU

LL DMA channel 11

LL_DMA_CHANNEL_12 0x0CU

LL DMA channel 12

LL_DMA_CHANNEL_13 0x0DU

LL DMA channel 13

LL_DMA_CHANNEL_14 0x0EU

LL DMA channel 14

LL_DMA_CHANNEL_15 0x0FU

LL DMA channel 15

Defines

LL_DMA_CHANNEL_0 0x00U

LL DMA channel 0

LL_DMA_CHANNEL_1 0x01U

LL DMA channel 1

LL_DMA_CHANNEL_2 0x02U

LL DMA channel 2

LL_DMA_CHANNEL_3 0x03U

LL DMA channel 3

LL_DMA_CHANNEL_4 0x04U

LL DMA channel 4

LL_DMA_CHANNEL_5 0x05U

LL DMA channel 5

LL_DMA_CHANNEL_6 0x06U

LL DMA channel 6

LL_DMA_CHANNEL_7 0x07U

LL DMA channel 7

LL_DMA_CHANNEL_8 0x08U

LL DMA channel 8

LL_DMA_CHANNEL_9 0x09U

LL DMA channel 9

LL_DMA_CHANNEL_10 0x0AU

LL DMA channel 10

LL_DMA_CHANNEL_11 0x0BU

LL DMA channel 11

LL_DMA_CHANNEL_12 0x0CU

LL DMA channel 12

LL_DMA_CHANNEL_13 0x0DU

LL DMA channel 13

LL_DMA_CHANNEL_14 0x0EU

LL DMA channel 14

LL_DMA_CHANNEL_15 0x0FU

LL DMA channel 15

Defines

LL_GPDMA1_CH0 GPDMA1_CH0 ¶

LL GPDMA1 channel 0

LL_GPDMA1_CH1 GPDMA1_CH1 ¶

LL GPDMA1 channel 1

LL_GPDMA1_CH2 GPDMA1_CH2 ¶

LL GPDMA1 channel 2

LL_GPDMA1_CH3 GPDMA1_CH3 ¶

LL GPDMA1 channel 3

LL_GPDMA1_CH4 GPDMA1_CH4 ¶

LL GPDMA1 channel 4

LL_GPDMA1_CH5 GPDMA1_CH5 ¶

LL GPDMA1 channel 5

LL_GPDMA1_CH6 GPDMA1_CH6 ¶

LL GPDMA1 channel 6

LL_GPDMA1_CH7 GPDMA1_CH7 ¶

LL GPDMA1 channel 7

LL_GPDMA1_CH8 GPDMA1_CH8 ¶

LL GPDMA1 channel 8

LL_GPDMA1_CH9 GPDMA1_CH9 ¶

LL GPDMA1 channel 9

LL_GPDMA1_CH10 GPDMA1_CH10 ¶

LL GPDMA1 channel 10

LL_GPDMA1_CH11 GPDMA1_CH11 ¶

LL GPDMA1 channel 11

LL_GPDMA1_CH12 GPDMA1_CH12 ¶

LL GPDMA1 channel 12

LL_GPDMA1_CH13 GPDMA1_CH13 ¶

LL GPDMA1 channel 13

LL_GPDMA1_CH14 GPDMA1_CH14 ¶

LL GPDMA1 channel 14

LL_GPDMA1_CH15 GPDMA1_CH15 ¶

LL GPDMA1 channel 15

LL_LPDMA1_CH0 LPDMA1_CH0 ¶

LL LPDMA1 channel 0

LL_LPDMA1_CH1 LPDMA1_CH1 ¶

LL LPDMA1 channel 1

LL_LPDMA1_CH2 LPDMA1_CH2 ¶

LL LPDMA1 channel 2

LL_LPDMA1_CH3 LPDMA1_CH3 ¶

LL LPDMA1 channel 3

Defines

LL_GPDMA1_CH0 GPDMA1_CH0

LL GPDMA1 channel 0

LL_GPDMA1_CH1 GPDMA1_CH1

LL GPDMA1 channel 1

LL_GPDMA1_CH2 GPDMA1_CH2

LL GPDMA1 channel 2

LL_GPDMA1_CH3 GPDMA1_CH3

LL GPDMA1 channel 3

LL_GPDMA1_CH4 GPDMA1_CH4

LL GPDMA1 channel 4

LL_GPDMA1_CH5 GPDMA1_CH5

LL GPDMA1 channel 5

LL_GPDMA1_CH6 GPDMA1_CH6

LL GPDMA1 channel 6

LL_GPDMA1_CH7 GPDMA1_CH7

LL GPDMA1 channel 7

LL_GPDMA1_CH8 GPDMA1_CH8

LL GPDMA1 channel 8

LL_GPDMA1_CH9 GPDMA1_CH9

LL GPDMA1 channel 9

LL_GPDMA1_CH10 GPDMA1_CH10

LL GPDMA1 channel 10

LL_GPDMA1_CH11 GPDMA1_CH11

LL GPDMA1 channel 11

LL_GPDMA1_CH12 GPDMA1_CH12

LL GPDMA1 channel 12

LL_GPDMA1_CH13 GPDMA1_CH13

LL GPDMA1 channel 13

LL_GPDMA1_CH14 GPDMA1_CH14

LL GPDMA1 channel 14

LL_GPDMA1_CH15 GPDMA1_CH15

LL GPDMA1 channel 15

LL_LPDMA1_CH0 LPDMA1_CH0

LL LPDMA1 channel 0

LL_LPDMA1_CH1 LPDMA1_CH1

LL LPDMA1 channel 1

LL_LPDMA1_CH2 LPDMA1_CH2

LL LPDMA1 channel 2

LL_LPDMA1_CH3 LPDMA1_CH3

LL LPDMA1 channel 3

Defines

LL_GPDMA1_CH0 GPDMA1_CH0

LL GPDMA1 channel 0

LL_GPDMA1_CH1 GPDMA1_CH1

LL GPDMA1 channel 1

LL_GPDMA1_CH2 GPDMA1_CH2

LL GPDMA1 channel 2

LL_GPDMA1_CH3 GPDMA1_CH3

LL GPDMA1 channel 3

LL_GPDMA1_CH4 GPDMA1_CH4

LL GPDMA1 channel 4

LL_GPDMA1_CH5 GPDMA1_CH5

LL GPDMA1 channel 5

LL_GPDMA1_CH6 GPDMA1_CH6

LL GPDMA1 channel 6

LL_GPDMA1_CH7 GPDMA1_CH7

LL GPDMA1 channel 7

LL_GPDMA1_CH8 GPDMA1_CH8

LL GPDMA1 channel 8

LL_GPDMA1_CH9 GPDMA1_CH9

LL GPDMA1 channel 9

LL_GPDMA1_CH10 GPDMA1_CH10

LL GPDMA1 channel 10

LL_GPDMA1_CH11 GPDMA1_CH11

LL GPDMA1 channel 11

LL_GPDMA1_CH12 GPDMA1_CH12

LL GPDMA1 channel 12

LL_GPDMA1_CH13 GPDMA1_CH13

LL GPDMA1 channel 13

LL_GPDMA1_CH14 GPDMA1_CH14

LL GPDMA1 channel 14

LL_GPDMA1_CH15 GPDMA1_CH15

LL GPDMA1 channel 15

LL_LPDMA1_CH0 LPDMA1_CH0

LL LPDMA1 channel 0

LL_LPDMA1_CH1 LPDMA1_CH1

LL LPDMA1 channel 1

LL_LPDMA1_CH2 LPDMA1_CH2

LL LPDMA1 channel 2

LL_LPDMA1_CH3 LPDMA1_CH3

LL LPDMA1 channel 3

Defines

LL_DMA_IT_TC DMA_CCR_TCIE ¶

Transfer complete interrupt

LL_DMA_IT_HT DMA_CCR_HTIE ¶

Half transfer complete interrupt

LL_DMA_IT_DTE DMA_CCR_DTEIE ¶

Data transfer error interrupt

LL_DMA_IT_ULE DMA_CCR_ULEIE ¶

Update linked-list item error interrupt

LL_DMA_IT_USE DMA_CCR_USEIE ¶

User setting error interrupt

LL_DMA_IT_SUSP DMA_CCR_SUSPIE ¶

Completed suspension interrupt

LL_DMA_IT_TO DMA_CCR_TOIE ¶

Trigger overrun interrupt

LL_DMA_IT_ALL

(DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_DTEIE | DMA_CCR_ULEIE | \

DMA_CCR_USEIE | DMA_CCR_SUSPIE | DMA_CCR_TOIE)

¶

All interrupts

LL_DMA_FLAG_IDLE DMA_CSR_IDLEF ¶

Idle flag

LL_DMA_FLAG_TC DMA_CSR_TCF ¶

Transfer complete flag

LL_DMA_FLAG_HT DMA_CSR_HTF ¶

Half transfer complete flag

LL_DMA_FLAG_DTE DMA_CSR_DTEF ¶

Data transfer error flag

LL_DMA_FLAG_ULE DMA_CSR_ULEF ¶

Update linked-list item error flag

LL_DMA_FLAG_USE DMA_CSR_USEF ¶

User setting error flag

LL_DMA_FLAG_SUSP DMA_CSR_SUSPF ¶

Completed suspension flag

LL_DMA_FLAG_TO DMA_CSR_TOF ¶

Trigger overrun flag

LL_DMA_FLAG_ALL

(DMA_CSR_TCF | DMA_CSR_HTF | DMA_CSR_DTEF | DMA_CSR_ULEF | \

DMA_CSR_USEF | DMA_CSR_SUSPF | DMA_CSR_TOF)

¶

All flags

Defines

LL_DMA_IT_TC DMA_CCR_TCIE

Transfer complete interrupt

LL_DMA_IT_HT DMA_CCR_HTIE

Half transfer complete interrupt

LL_DMA_IT_DTE DMA_CCR_DTEIE

Data transfer error interrupt

LL_DMA_IT_ULE DMA_CCR_ULEIE

Update linked-list item error interrupt

LL_DMA_IT_USE DMA_CCR_USEIE

User setting error interrupt

LL_DMA_IT_SUSP DMA_CCR_SUSPIE

Completed suspension interrupt

LL_DMA_IT_TO DMA_CCR_TOIE

Trigger overrun interrupt

LL_DMA_IT_ALL

(DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_DTEIE | DMA_CCR_ULEIE | \

DMA_CCR_USEIE | DMA_CCR_SUSPIE | DMA_CCR_TOIE)

All interrupts

LL_DMA_FLAG_IDLE DMA_CSR_IDLEF

Idle flag

LL_DMA_FLAG_TC DMA_CSR_TCF

Transfer complete flag

LL_DMA_FLAG_HT DMA_CSR_HTF

Half transfer complete flag

LL_DMA_FLAG_DTE DMA_CSR_DTEF

Data transfer error flag

LL_DMA_FLAG_ULE DMA_CSR_ULEF

Update linked-list item error flag

LL_DMA_FLAG_USE DMA_CSR_USEF

User setting error flag

LL_DMA_FLAG_SUSP DMA_CSR_SUSPF

Completed suspension flag

LL_DMA_FLAG_TO DMA_CSR_TOF

Trigger overrun flag

LL_DMA_FLAG_ALL

(DMA_CSR_TCF | DMA_CSR_HTF | DMA_CSR_DTEF | DMA_CSR_ULEF | \

DMA_CSR_USEF | DMA_CSR_SUSPF | DMA_CSR_TOF)

All flags

Defines

LL_DMA_IT_TC DMA_CCR_TCIE

Transfer complete interrupt

LL_DMA_IT_HT DMA_CCR_HTIE

Half transfer complete interrupt

LL_DMA_IT_DTE DMA_CCR_DTEIE

Data transfer error interrupt

LL_DMA_IT_ULE DMA_CCR_ULEIE

Update linked-list item error interrupt

LL_DMA_IT_USE DMA_CCR_USEIE

User setting error interrupt

LL_DMA_IT_SUSP DMA_CCR_SUSPIE

Completed suspension interrupt

LL_DMA_IT_TO DMA_CCR_TOIE

Trigger overrun interrupt

LL_DMA_IT_ALL

(DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_DTEIE | DMA_CCR_ULEIE | \

DMA_CCR_USEIE | DMA_CCR_SUSPIE | DMA_CCR_TOIE)

All interrupts

LL_DMA_FLAG_IDLE DMA_CSR_IDLEF

Idle flag

LL_DMA_FLAG_TC DMA_CSR_TCF

Transfer complete flag

LL_DMA_FLAG_HT DMA_CSR_HTF

Half transfer complete flag

LL_DMA_FLAG_DTE DMA_CSR_DTEF

Data transfer error flag

LL_DMA_FLAG_ULE DMA_CSR_ULEF

Update linked-list item error flag

LL_DMA_FLAG_USE DMA_CSR_USEF

User setting error flag

LL_DMA_FLAG_SUSP DMA_CSR_SUSPF

Completed suspension flag

LL_DMA_FLAG_TO DMA_CSR_TOF

Trigger overrun flag

LL_DMA_FLAG_ALL

(DMA_CSR_TCF | DMA_CSR_HTF | DMA_CSR_DTEF | DMA_CSR_ULEF | \

DMA_CSR_USEF | DMA_CSR_SUSPF | DMA_CSR_TOF)

All flags

Defines

LL_DMA_PRIORITY_LOW_WEIGHT_LOW 0x00000000U ¶

Priority level : Low Priority, Low Weight

LL_DMA_PRIORITY_LOW_WEIGHT_MID DMA_CCR_PRIO_0 ¶

Priority level : Low Priority, Mid Weight

LL_DMA_PRIORITY_LOW_WEIGHT_HIGH DMA_CCR_PRIO_1 ¶

Priority level : Low Priority, High Weight

LL_DMA_PRIORITY_HIGH DMA_CCR_PRIO ¶

Priority level : High Priority

Defines

LL_DMA_PRIORITY_LOW_WEIGHT_LOW 0x00000000U

Priority level : Low Priority, Low Weight

LL_DMA_PRIORITY_LOW_WEIGHT_MID DMA_CCR_PRIO_0

Priority level : Low Priority, Mid Weight

LL_DMA_PRIORITY_LOW_WEIGHT_HIGH DMA_CCR_PRIO_1

Priority level : Low Priority, High Weight

LL_DMA_PRIORITY_HIGH DMA_CCR_PRIO

Priority level : High Priority

Defines

LL_DMA_PRIORITY_LOW_WEIGHT_LOW 0x00000000U

Priority level : Low Priority, Low Weight

LL_DMA_PRIORITY_LOW_WEIGHT_MID DMA_CCR_PRIO_0

Priority level : Low Priority, Mid Weight

LL_DMA_PRIORITY_LOW_WEIGHT_HIGH DMA_CCR_PRIO_1

Priority level : Low Priority, High Weight

LL_DMA_PRIORITY_HIGH DMA_CCR_PRIO

Priority level : High Priority

Defines

LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U ¶

Linked List Allocated Port 0

LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP ¶

Linked List Allocated Port 1

Defines

LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U

Linked List Allocated Port 0

LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP

Linked List Allocated Port 1

Defines

LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U

Linked List Allocated Port 0

LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP

Linked List Allocated Port 1

Defines

LL_DMA_LINKEDLIST_EXECUTION_Q 0x00000000U ¶

channel executed for the full linked-list

LL_DMA_LINKEDLIST_EXECUTION_NODE DMA_CCR_LSM ¶

channel executed once for the current linked-list item

Defines

LL_DMA_LINKEDLIST_EXECUTION_Q 0x00000000U

channel executed for the full linked-list

LL_DMA_LINKEDLIST_EXECUTION_NODE DMA_CCR_LSM

channel executed once for the current linked-list item

Defines

LL_DMA_LINKEDLIST_EXECUTION_Q 0x00000000U

channel executed for the full linked-list

LL_DMA_LINKEDLIST_EXECUTION_NODE DMA_CCR_LSM

channel executed once for the current linked-list item

Defines

LL_DMA_DEST_HALFWORD_PRESERVED 0x00000000U ¶

When destination data width > Half-Word, no half-word-based exchange within word.

LL_DMA_DEST_HALFWORD_EXCHANGED DMA_CTR1_DHX ¶

When destination data width > Half-Word, The two consecutive half-words are exchanged in each destination word.

Defines

LL_DMA_DEST_HALFWORD_PRESERVED 0x00000000U

When destination data width > Half-Word, no half-word-based exchange within word.

LL_DMA_DEST_HALFWORD_EXCHANGED DMA_CTR1_DHX

When destination data width > Half-Word, The two consecutive half-words are exchanged in each destination word.

Defines

LL_DMA_DEST_HALFWORD_PRESERVED 0x00000000U

When destination data width > Half-Word, no half-word-based exchange within word.

LL_DMA_DEST_HALFWORD_EXCHANGED DMA_CTR1_DHX

When destination data width > Half-Word, The two consecutive half-words are exchanged in each destination word.

Defines

LL_DMA_DEST_BYTE_PRESERVED 0x00000000U ¶

When destination data width > Byte, no byte-based exchange within half-word.

LL_DMA_DEST_BYTE_EXCHANGED DMA_CTR1_DBX ¶

When destination data width > Byte, the two consecutive bytes are exchanged in each destination half-word.

Defines

LL_DMA_DEST_BYTE_PRESERVED 0x00000000U

When destination data width > Byte, no byte-based exchange within half-word.

LL_DMA_DEST_BYTE_EXCHANGED DMA_CTR1_DBX

When destination data width > Byte, the two consecutive bytes are exchanged in each destination half-word.

Defines

LL_DMA_DEST_BYTE_PRESERVED 0x00000000U

When destination data width > Byte, no byte-based exchange within half-word.

LL_DMA_DEST_BYTE_EXCHANGED DMA_CTR1_DBX

When destination data width > Byte, the two consecutive bytes are exchanged in each destination half-word.

Defines

LL_DMA_SRC_BYTE_PRESERVED 0x00000000U ¶

No byte-based exchange within the unaligned half-word of each source word.

LL_DMA_SRC_BYTE_EXCHANGED DMA_CTR1_SBX ¶

The two consecutive bytes within the unaligned half-word of each source word are exchanged.

Defines

LL_DMA_SRC_BYTE_PRESERVED 0x00000000U

No byte-based exchange within the unaligned half-word of each source word.

LL_DMA_SRC_BYTE_EXCHANGED DMA_CTR1_SBX

The two consecutive bytes within the unaligned half-word of each source word are exchanged.

Defines

LL_DMA_SRC_BYTE_PRESERVED 0x00000000U

No byte-based exchange within the unaligned half-word of each source word.

LL_DMA_SRC_BYTE_EXCHANGED DMA_CTR1_SBX

The two consecutive bytes within the unaligned half-word of each source word are exchanged.

Defines

LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U ¶

Source Allocated Port 0

LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP ¶

Source Allocated Port 1

Defines

LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U

Source Allocated Port 0

LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP

Source Allocated Port 1

Defines

LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U

Source Allocated Port 0

LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP

Source Allocated Port 1

Defines

LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U ¶

Destination Allocated Port 0

LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP ¶

Destination Allocated Port 1

Defines

LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U

Destination Allocated Port 0

LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP

Destination Allocated Port 1

Defines

LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U

Destination Allocated Port 0

LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP

Destination Allocated Port 1

Defines

LL_DMA_DEST_ADDR_FIXED 0x00000000U ¶

Destination fixed single/burst

LL_DMA_DEST_ADDR_INCREMENTED DMA_CTR1_DINC ¶

Destination incremented single/burst

Defines

LL_DMA_DEST_ADDR_FIXED 0x00000000U

Destination fixed single/burst

LL_DMA_DEST_ADDR_INCREMENTED DMA_CTR1_DINC

Destination incremented single/burst

Defines

LL_DMA_DEST_ADDR_FIXED 0x00000000U

Destination fixed single/burst

LL_DMA_DEST_ADDR_INCREMENTED DMA_CTR1_DINC

Destination incremented single/burst

Defines

LL_DMA_DEST_DATA_WIDTH_BYTE 0x00000000U ¶

Destination Data Width : Byte

LL_DMA_DEST_DATA_WIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 ¶

Destination Data Width : HalfWord

LL_DMA_DEST_DATA_WIDTH_WORD DMA_CTR1_DDW_LOG2_1 ¶

Destination Data Width : Word

Defines

LL_DMA_DEST_DATA_WIDTH_BYTE 0x00000000U

Destination Data Width : Byte

LL_DMA_DEST_DATA_WIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0

Destination Data Width : HalfWord

LL_DMA_DEST_DATA_WIDTH_WORD DMA_CTR1_DDW_LOG2_1

Destination Data Width : Word

Defines

LL_DMA_DEST_DATA_WIDTH_BYTE 0x00000000U

Destination Data Width : Byte

LL_DMA_DEST_DATA_WIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0

Destination Data Width : HalfWord

LL_DMA_DEST_DATA_WIDTH_WORD DMA_CTR1_DDW_LOG2_1

Destination Data Width : Word

Defines

LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO 0x00000000U ¶

If src data width < dest data width : => Right Aligned padded with 0 up to destination data width. If src data width > dest data width : => Right Aligned Left Truncated down to destination data width.

LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN DMA_CTR1_PAM_0 ¶

If src data width < dest data width : => Right Aligned padded with sign extended up to destination data width. If src data width > dest data width : => Left Aligned Right Truncated down to the destination data width

Defines

LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO 0x00000000U

If src data width < dest data width : => Right Aligned padded with 0 up to destination data width. If src data width > dest data width : => Right Aligned Left Truncated down to destination data width.

LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN DMA_CTR1_PAM_0

If src data width < dest data width : => Right Aligned padded with sign extended up to destination data width. If src data width > dest data width : => Left Aligned Right Truncated down to the destination data width

Defines

LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO 0x00000000U

If src data width < dest data width : => Right Aligned padded with 0 up to destination data width. If src data width > dest data width : => Right Aligned Left Truncated down to destination data width.

LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN DMA_CTR1_PAM_0

If src data width < dest data width : => Right Aligned padded with sign extended up to destination data width. If src data width > dest data width : => Left Aligned Right Truncated down to the destination data width

Defines

LL_DMA_DEST_DATA_PRESERVED 0x00000000U ¶

If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width

LL_DMA_DEST_DATA_PACKED_UNPACKED DMA_CTR1_PAM_1 ¶

If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width

Defines

LL_DMA_DEST_DATA_PRESERVED 0x00000000U

If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width

LL_DMA_DEST_DATA_PACKED_UNPACKED DMA_CTR1_PAM_1

If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width

Defines

LL_DMA_DEST_DATA_PRESERVED 0x00000000U

If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width

LL_DMA_DEST_DATA_PACKED_UNPACKED DMA_CTR1_PAM_1

If src data width < dest data width : => Packed at the destination data width If src data width > dest data width : => Unpacked at the destination data width

Defines

LL_DMA_SRC_ADDR_FIXED 0x00000000U ¶

Source fixed single/burst

LL_DMA_SRC_ADDR_INCREMENTED DMA_CTR1_SINC ¶

Source incremented single/burst

Defines

LL_DMA_SRC_ADDR_FIXED 0x00000000U

Source fixed single/burst

LL_DMA_SRC_ADDR_INCREMENTED DMA_CTR1_SINC

Source incremented single/burst

Defines

LL_DMA_SRC_ADDR_FIXED 0x00000000U

Source fixed single/burst

LL_DMA_SRC_ADDR_INCREMENTED DMA_CTR1_SINC

Source incremented single/burst

Defines

LL_DMA_SRC_DATA_WIDTH_BYTE 0x00000000U ¶

Source Data Width : Byte

LL_DMA_SRC_DATA_WIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 ¶

Source Data Width : HalfWord

LL_DMA_SRC_DATA_WIDTH_WORD DMA_CTR1_SDW_LOG2_1 ¶

Source Data Width : Word

Defines

LL_DMA_SRC_DATA_WIDTH_BYTE 0x00000000U

Source Data Width : Byte

LL_DMA_SRC_DATA_WIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0

Source Data Width : HalfWord

LL_DMA_SRC_DATA_WIDTH_WORD DMA_CTR1_SDW_LOG2_1

Source Data Width : Word

Defines

LL_DMA_SRC_DATA_WIDTH_BYTE 0x00000000U

Source Data Width : Byte

LL_DMA_SRC_DATA_WIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0

Source Data Width : HalfWord

LL_DMA_SRC_DATA_WIDTH_WORD DMA_CTR1_SDW_LOG2_1

Source Data Width : Word

Defines

LL_DMA_HARDWARE_REQUEST_BURST 0x00000000U ¶

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level

LL_DMA_HARDWARE_REQUEST_BLOCK DMA_CTR2_BREQ ¶

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level

Defines

LL_DMA_HARDWARE_REQUEST_BURST 0x00000000U

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level

LL_DMA_HARDWARE_REQUEST_BLOCK DMA_CTR2_BREQ

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level

Defines

LL_DMA_HARDWARE_REQUEST_BURST 0x00000000U

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level

LL_DMA_HARDWARE_REQUEST_BLOCK DMA_CTR2_BREQ

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level

Defines

LL_DMA_DIRECT_XFER_EVENT_BLOCK 0x00000000U ¶

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK DMA_CTR2_TCEM_0 ¶

The TC (and the HT) event is generated at the end (respectively half of the end) of the 2D/repeated block

LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK LL_DMA_DIRECT_XFER_EVENT_BLOCK ¶

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_LINKEDLIST_XFER_EVENT_REPEATED_BLOCK LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK ¶

The TC (and the HT) event is generated at the end (respectively half of the end) of the 2D/repeated block

LL_DMA_LINKEDLIST_XFER_EVENT_NODE DMA_CTR2_TCEM_1 ¶

The TC (and the HT) event is generated at the (respectively half) end of each linked-list item

LL_DMA_LINKEDLIST_XFER_EVENT_Q DMA_CTR2_TCEM ¶

The TC (and the HT) event is generated at the (respectively half) end of the last linked-list item

Defines

LL_DMA_DIRECT_XFER_EVENT_BLOCK 0x00000000U

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK DMA_CTR2_TCEM_0

The TC (and the HT) event is generated at the end (respectively half of the end) of the 2D/repeated block

LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK LL_DMA_DIRECT_XFER_EVENT_BLOCK

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_LINKEDLIST_XFER_EVENT_REPEATED_BLOCK LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK

The TC (and the HT) event is generated at the end (respectively half of the end) of the 2D/repeated block

LL_DMA_LINKEDLIST_XFER_EVENT_NODE DMA_CTR2_TCEM_1

The TC (and the HT) event is generated at the (respectively half) end of each linked-list item

LL_DMA_LINKEDLIST_XFER_EVENT_Q DMA_CTR2_TCEM

The TC (and the HT) event is generated at the (respectively half) end of the last linked-list item

Defines

LL_DMA_DIRECT_XFER_EVENT_BLOCK 0x00000000U

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK DMA_CTR2_TCEM_0

The TC (and the HT) event is generated at the end (respectively half of the end) of the 2D/repeated block

LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK LL_DMA_DIRECT_XFER_EVENT_BLOCK

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_LINKEDLIST_XFER_EVENT_REPEATED_BLOCK LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK

The TC (and the HT) event is generated at the end (respectively half of the end) of the 2D/repeated block

LL_DMA_LINKEDLIST_XFER_EVENT_NODE DMA_CTR2_TCEM_1

The TC (and the HT) event is generated at the (respectively half) end of each linked-list item

LL_DMA_LINKEDLIST_XFER_EVENT_Q DMA_CTR2_TCEM

The TC (and the HT) event is generated at the (respectively half) end of the last linked-list item

Defines

LL_DMA_TRIGGER_POLARITY_MASKED 0x00000000U ¶

No trigger of the selected DMA request. Masked trigger event

LL_DMA_TRIGGER_POLARITY_RISING DMA_CTR2_TRIGPOL_0 ¶

Trigger of the selected DMA request on the rising edge of the selected trigger event input

LL_DMA_TRIGGER_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 ¶

Trigger of the selected DMA request on the falling edge of the selected trigger event input

Defines

LL_DMA_TRIGGER_POLARITY_MASKED 0x00000000U

No trigger of the selected DMA request. Masked trigger event

LL_DMA_TRIGGER_POLARITY_RISING DMA_CTR2_TRIGPOL_0

Trigger of the selected DMA request on the rising edge of the selected trigger event input

LL_DMA_TRIGGER_POLARITY_FALLING DMA_CTR2_TRIGPOL_1

Trigger of the selected DMA request on the falling edge of the selected trigger event input

Defines

LL_DMA_TRIGGER_POLARITY_MASKED 0x00000000U

No trigger of the selected DMA request. Masked trigger event

LL_DMA_TRIGGER_POLARITY_RISING DMA_CTR2_TRIGPOL_0

Trigger of the selected DMA request on the rising edge of the selected trigger event input

LL_DMA_TRIGGER_POLARITY_FALLING DMA_CTR2_TRIGPOL_1

Trigger of the selected DMA request on the falling edge of the selected trigger event input

Defines

LL_DMA_TRIGGER_BLOCK_TRANSFER 0x00000000U ¶

A block transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 ¶

A repeated block transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_NODE_TRANSFER DMA_CTR2_TRIGM_1 ¶

A LLI link transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM ¶

A Single/Burst transfer is conditioned by (at least) one hit trigger

Defines

LL_DMA_TRIGGER_BLOCK_TRANSFER 0x00000000U

A block transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0

A repeated block transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_NODE_TRANSFER DMA_CTR2_TRIGM_1

A LLI link transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM

A Single/Burst transfer is conditioned by (at least) one hit trigger

Defines

LL_DMA_TRIGGER_BLOCK_TRANSFER 0x00000000U

A block transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0

A repeated block transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_NODE_TRANSFER DMA_CTR2_TRIGM_1

A LLI link transfer is conditioned by (at least) one hit trigger

LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM

A Single/Burst transfer is conditioned by (at least) one hit trigger

Defines

LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ ¶

Memory to memory direction

LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U ¶

Peripheral to memory direction

LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ ¶

Memory to peripheral direction

Defines

LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ

Memory to memory direction

LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ

Memory to peripheral direction

Defines

LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ

Memory to memory direction

LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ

Memory to peripheral direction

Defines

LL_DMA_BLOCK_SRC_ADDR_INCREMENTED 0x00000000U ¶

Source address pointer is incremented after each block transfer by source update value

LL_DMA_BLOCK_SRC_ADDR_DECREMENTED DMA_CBR1_BRSDEC ¶

Source address pointer is decremented after each block transfer by source update value

Defines

LL_DMA_BLOCK_SRC_ADDR_INCREMENTED 0x00000000U

Source address pointer is incremented after each block transfer by source update value

LL_DMA_BLOCK_SRC_ADDR_DECREMENTED DMA_CBR1_BRSDEC

Source address pointer is decremented after each block transfer by source update value

Defines

LL_DMA_BLOCK_SRC_ADDR_INCREMENTED 0x00000000U

Source address pointer is incremented after each block transfer by source update value

LL_DMA_BLOCK_SRC_ADDR_DECREMENTED DMA_CBR1_BRSDEC

Source address pointer is decremented after each block transfer by source update value

Defines

LL_DMA_BLOCK_DEST_ADDR_INCREMENTED 0x00000000U ¶

Destination address is incremented after each block transfer by destination update value

LL_DMA_BLOCK_DEST_ADDR_DECREMENTED DMA_CBR1_BRDDEC ¶

Destination address is decremented after each block transfer by destination update value

Defines

LL_DMA_BLOCK_DEST_ADDR_INCREMENTED 0x00000000U

Destination address is incremented after each block transfer by destination update value

LL_DMA_BLOCK_DEST_ADDR_DECREMENTED DMA_CBR1_BRDDEC

Destination address is decremented after each block transfer by destination update value

Defines

LL_DMA_BLOCK_DEST_ADDR_INCREMENTED 0x00000000U

Destination address is incremented after each block transfer by destination update value

LL_DMA_BLOCK_DEST_ADDR_DECREMENTED DMA_CBR1_BRDDEC

Destination address is decremented after each block transfer by destination update value

Defines

LL_DMA_BURST_SRC_ADDR_INCREMENTED 0x00000000U ¶

Source address pointer is incremented after each burst transfer by source update value

LL_DMA_BURST_SRC_ADDR_DECREMENTED DMA_CBR1_SDEC ¶

Source address pointer is decremented after each burst transfer by source update value

Defines

LL_DMA_BURST_SRC_ADDR_INCREMENTED 0x00000000U

Source address pointer is incremented after each burst transfer by source update value

LL_DMA_BURST_SRC_ADDR_DECREMENTED DMA_CBR1_SDEC

Source address pointer is decremented after each burst transfer by source update value

Defines

LL_DMA_BURST_SRC_ADDR_INCREMENTED 0x00000000U

Source address pointer is incremented after each burst transfer by source update value

LL_DMA_BURST_SRC_ADDR_DECREMENTED DMA_CBR1_SDEC

Source address pointer is decremented after each burst transfer by source update value

Defines

LL_DMA_BURST_DEST_ADDR_INCREMENTED 0x00000000U ¶

Destination address pointer is incremented after each burst transfer by destination update value

LL_DMA_BURST_DEST_ADDR_DECREMENTED DMA_CBR1_DDEC ¶

Destination address pointer is decremented after each burst transfer by destination update value

Defines

LL_DMA_BURST_DEST_ADDR_INCREMENTED 0x00000000U

Destination address pointer is incremented after each burst transfer by destination update value

LL_DMA_BURST_DEST_ADDR_DECREMENTED DMA_CBR1_DDEC

Destination address pointer is decremented after each burst transfer by destination update value

Defines

LL_DMA_BURST_DEST_ADDR_INCREMENTED 0x00000000U

Destination address pointer is incremented after each burst transfer by destination update value

LL_DMA_BURST_DEST_ADDR_DECREMENTED DMA_CBR1_DDEC

Destination address pointer is decremented after each burst transfer by destination update value

Defines

LL_DMA_ATTR_NSEC 0x00U ¶

Non Secure channel

LL_DMA_ATTR_SEC 0x01U ¶

Secure channel

Defines

LL_DMA_ATTR_NSEC 0x00U

Non Secure channel

LL_DMA_ATTR_SEC 0x01U

Secure channel

Defines

LL_DMA_ATTR_NSEC 0x00U

Non Secure channel

LL_DMA_ATTR_SEC 0x01U

Secure channel

Defines

LL_DMA_ATTR_NPRIV 0x00U ¶

Non Privileged channel

LL_DMA_ATTR_PRIV 0x01U ¶

Privileged channel

Defines

LL_DMA_ATTR_NPRIV 0x00U

Non Privileged channel

LL_DMA_ATTR_PRIV 0x01U

Privileged channel

Defines

LL_DMA_ATTR_NPRIV 0x00U

Non Privileged channel

LL_DMA_ATTR_PRIV 0x01U

Privileged channel

Defines

LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 ¶

Update CTR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 ¶

Update CTR2 register from memory : available for all DMA channels

LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 ¶

Update CBR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CSAR DMA_CLLR_USA ¶

Update CSAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CDAR DMA_CLLR_UDA ¶

Update CDAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 ¶

Update CTR3 register from memory : available only for 2D addressing DMA channels

LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 ¶

Update CBR2 register from memory : available only for 2D addressing DMA channels

LL_DMA_UPDATE_CLLR DMA_CLLR_ULL ¶

Update CLLR register from memory : available for all DMA channels

LL_DMA_UPDATE_ALL

(DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | \

DMA_CLLR_UDA | DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)

¶

Defines

LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1

Update CTR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2

Update CTR2 register from memory : available for all DMA channels

LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1

Update CBR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CSAR DMA_CLLR_USA

Update CSAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CDAR DMA_CLLR_UDA

Update CDAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3

Update CTR3 register from memory : available only for 2D addressing DMA channels

LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2

Update CBR2 register from memory : available only for 2D addressing DMA channels

LL_DMA_UPDATE_CLLR DMA_CLLR_ULL

Update CLLR register from memory : available for all DMA channels

LL_DMA_UPDATE_ALL

(DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | \

DMA_CLLR_UDA | DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)

Defines

LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1

Update CTR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2

Update CTR2 register from memory : available for all DMA channels

LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1

Update CBR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CSAR DMA_CLLR_USA

Update CSAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CDAR DMA_CLLR_UDA

Update CDAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3

Update CTR3 register from memory : available only for 2D addressing DMA channels

LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2

Update CBR2 register from memory : available only for 2D addressing DMA channels

LL_DMA_UPDATE_CLLR DMA_CLLR_ULL

Update CLLR register from memory : available for all DMA channels

LL_DMA_UPDATE_ALL

(DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | \

DMA_CLLR_UDA | DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)

Defines

LL_GPDMA1_REQUEST_ADC1 0U ¶

GPDMA1 HW Request is ADC1

LL_GPDMA1_REQUEST_ADC4 1U ¶

GPDMA1 HW Request is ADC4

LL_GPDMA1_REQUEST_DAC1_CH1 2U ¶

GPDMA1 HW Request is DAC1_CH1

LL_GPDMA1_REQUEST_DAC1_CH2 3U ¶

GPDMA1 HW Request is DAC1_CH2

LL_GPDMA1_REQUEST_TIM6_UPD 4U ¶

GPDMA1 HW Request is TIM6_UPD

LL_GPDMA1_REQUEST_TIM7_UPD 5U ¶

GPDMA1 HW Request is TIM7_UPD

LL_GPDMA1_REQUEST_SPI1_RX 6U ¶

GPDMA1 HW Request is SPI1_RX

LL_GPDMA1_REQUEST_SPI1_TX 7U ¶

GPDMA1 HW Request is SPI1_TX

LL_GPDMA1_REQUEST_SPI2_RX 8U ¶

GPDMA1 HW Request is SPI2_RX

LL_GPDMA1_REQUEST_SPI2_TX 9U ¶

GPDMA1 HW Request is SPI2_TX

LL_GPDMA1_REQUEST_SPI3_RX 10U ¶

GPDMA1 HW Request is SPI3_RX

LL_GPDMA1_REQUEST_SPI3_TX 11U ¶

GPDMA1 HW Request is SPI3_TX

LL_GPDMA1_REQUEST_I2C1_RX 12U ¶

GPDMA1 HW Request is I2C1_RX

LL_GPDMA1_REQUEST_I2C1_TX 13U ¶

GPDMA1 HW Request is I2C1_TX

LL_GPDMA1_REQUEST_I2C1_EVC 14U ¶

GPDMA1 HW Request is I2C1_EVC

LL_GPDMA1_REQUEST_I2C2_RX 15U ¶

GPDMA1 HW Request is I2C2_RX

LL_GPDMA1_REQUEST_I2C2_TX 16U ¶

GPDMA1 HW Request is I2C2_TX

LL_GPDMA1_REQUEST_I2C2_EVC 17U ¶

GPDMA1 HW Request is I2C2_EVC

LL_GPDMA1_REQUEST_I2C3_RX 18U ¶

GPDMA1 HW Request is I2C3_RX

LL_GPDMA1_REQUEST_I2C3_TX 19U ¶

GPDMA1 HW Request is I2C3_TX

LL_GPDMA1_REQUEST_I2C3_EVC 20U ¶

GPDMA1 HW Request is I2C3_EVC

LL_GPDMA1_REQUEST_I2C4_RX 21U ¶

GPDMA1 HW Request is I2C4_RX

LL_GPDMA1_REQUEST_I2C4_TX 22U ¶

GPDMA1 HW Request is I2C4_TX

LL_GPDMA1_REQUEST_I2C4_EVC 23U ¶

GPDMA1 HW Request is I2C4_EVC

LL_GPDMA1_REQUEST_USART1_RX 24U ¶

GPDMA1 HW Request is USART1_RX

LL_GPDMA1_REQUEST_USART1_TX 25U ¶

GPDMA1 HW Request is USART1_TX

LL_GPDMA1_REQUEST_USART2_RX 26U ¶

GPDMA1 HW Request is USART2_RX

LL_GPDMA1_REQUEST_USART2_TX 27U ¶

GPDMA1 HW Request is USART2_TX

LL_GPDMA1_REQUEST_USART3_RX 28U ¶

GPDMA1 HW Request is USART3_RX

LL_GPDMA1_REQUEST_USART3_TX 29U ¶

GPDMA1 HW Request is USART3_TX

LL_GPDMA1_REQUEST_UART4_RX 30U ¶

GPDMA1 HW Request is UART4_RX

LL_GPDMA1_REQUEST_UART4_TX 31U ¶

GPDMA1 HW Request is UART4_TX

LL_GPDMA1_REQUEST_UART5_RX 32U ¶

GPDMA1 HW Request is UART5_RX

LL_GPDMA1_REQUEST_UART5_TX 33U ¶

GPDMA1 HW Request is UART5_TX

LL_GPDMA1_REQUEST_LPUART1_RX 34U ¶

GPDMA1 HW Request is LPUART1_RX

LL_GPDMA1_REQUEST_LPUART1_TX 35U ¶

GPDMA1 HW Request is LPUART1_TX

LL_GPDMA1_REQUEST_SAI1_A 36U ¶

GPDMA1 HW Request is SAI1_A

LL_GPDMA1_REQUEST_SAI1_B 37U ¶

GPDMA1 HW Request is SAI1_B

LL_GPDMA1_REQUEST_SAI2_A 38U ¶

GPDMA1 HW Request is SAI2_A

LL_GPDMA1_REQUEST_SAI2_B 39U ¶

GPDMA1 HW Request is SAI2_B

LL_GPDMA1_REQUEST_OCTOSPI1 40U ¶

GPDMA1 HW Request is OCTOSPI1

LL_GPDMA1_REQUEST_OCTOSPI2 41U ¶

GPDMA1 HW Request is OCTOSPI2

LL_GPDMA1_REQUEST_TIM1_CC1 42U ¶

GPDMA1 HW Request is TIM1_CC1

LL_GPDMA1_REQUEST_TIM1_CC2 43U ¶

GPDMA1 HW Request is TIM1_CC2

LL_GPDMA1_REQUEST_TIM1_CC3 44U ¶

GPDMA1 HW Request is TIM1_CC3

LL_GPDMA1_REQUEST_TIM1_CC4 45U ¶

GPDMA1 HW Request is TIM1_CC4

LL_GPDMA1_REQUEST_TIM1_UPD 46U ¶

GPDMA1 HW Request is TIM1_UPD

LL_GPDMA1_REQUEST_TIM1_TRGI 47U ¶

GPDMA1 HW Request is TIM1_TRGI

LL_GPDMA1_REQUEST_TIM1_COM 48U ¶

GPDMA1 HW Request is TIM1_COM

LL_GPDMA1_REQUEST_TIM8_CC1 49U ¶

GPDMA1 HW Request is TIM8_CC1

LL_GPDMA1_REQUEST_TIM8_CC2 50U ¶

GPDMA1 HW Request is TIM8_CC2

LL_GPDMA1_REQUEST_TIM8_CC3 51U ¶

GPDMA1 HW Request is TIM8_CC3

LL_GPDMA1_REQUEST_TIM8_CC4 52U ¶

GPDMA1 HW Request is TIM8_CC4

LL_GPDMA1_REQUEST_TIM8_UPD 53U ¶

GPDMA1 HW Request is TIM8_UPD

LL_GPDMA1_REQUEST_TIM8_TRGI 54U ¶

GPDMA1 HW Request is TIM8_TRGI

LL_GPDMA1_REQUEST_TIM8_COM 55U ¶

GPDMA1 HW Request is TIM8_COM

LL_GPDMA1_REQUEST_TIM2_CC1 56U ¶

GPDMA1 HW Request is TIM2_CC1

LL_GPDMA1_REQUEST_TIM2_CC2 57U ¶

GPDMA1 HW Request is TIM2_CC2

LL_GPDMA1_REQUEST_TIM2_CC3 58U ¶

GPDMA1 HW Request is TIM2_CC3

LL_GPDMA1_REQUEST_TIM2_CC4 59U ¶

GPDMA1 HW Request is TIM2_CC4

LL_GPDMA1_REQUEST_TIM2_UPD 60U ¶

GPDMA1 HW Request is TIM2_UPD

LL_GPDMA1_REQUEST_TIM3_CC1 61U ¶

GPDMA1 HW Request is TIM3_CC1

LL_GPDMA1_REQUEST_TIM3_CC2 62U ¶

GPDMA1 HW Request is TIM3_CC2

LL_GPDMA1_REQUEST_TIM3_CC3 63U ¶

GPDMA1 HW Request is TIM3_CC3

LL_GPDMA1_REQUEST_TIM3_CC4 64U ¶

GPDMA1 HW Request is TIM3_CC4

LL_GPDMA1_REQUEST_TIM3_UPD 65U ¶

GPDMA1 HW Request is TIM3_UPD

LL_GPDMA1_REQUEST_TIM3_TRGI 66U ¶

GPDMA1 HW Request is TIM3_TRGI

LL_GPDMA1_REQUEST_TIM4_CC1 67U ¶

GPDMA1 HW Request is TIM4_CC1

LL_GPDMA1_REQUEST_TIM4_CC2 68U ¶

GPDMA1 HW Request is TIM4_CC2

LL_GPDMA1_REQUEST_TIM4_CC3 69U ¶

GPDMA1 HW Request is TIM4_CC3

LL_GPDMA1_REQUEST_TIM4_CC4 70U ¶

GPDMA1 HW Request is TIM4_CC4

LL_GPDMA1_REQUEST_TIM4_UPD 71U ¶

GPDMA1 HW Request is TIM4_UPD

LL_GPDMA1_REQUEST_TIM5_CC1 72U ¶

GPDMA1 HW Request is TIM5_CC1

LL_GPDMA1_REQUEST_TIM5_CC2 73U ¶

GPDMA1 HW Request is TIM5_CC2

LL_GPDMA1_REQUEST_TIM5_CC3 74U ¶

GPDMA1 HW Request is TIM5_CC3

LL_GPDMA1_REQUEST_TIM5_CC4 75U ¶

GPDMA1 HW Request is TIM5_CC4

LL_GPDMA1_REQUEST_TIM5_UPD 76U ¶

GPDMA1 HW Request is TIM5_UPD

LL_GPDMA1_REQUEST_TIM5_TRGI 77U ¶

GPDMA1 HW Request is TIM5_TRGI

LL_GPDMA1_REQUEST_TIM15_CC1 78U ¶

GPDMA1 HW Request is TIM15_CC1

LL_GPDMA1_REQUEST_TIM15_UPD 79U ¶

GPDMA1 HW Request is TIM15_UPD

LL_GPDMA1_REQUEST_TIM15_TRGI 80U ¶

GPDMA1 HW Request is TIM15_TRGI

LL_GPDMA1_REQUEST_TIM15_COM 81U ¶

GPDMA1 HW Request is TIM15_COM

LL_GPDMA1_REQUEST_TIM16_CC1 82U ¶

GPDMA1 HW Request is TIM16_CC1

LL_GPDMA1_REQUEST_TIM16_UPD 83U ¶

GPDMA1 HW Request is TIM16_UPD

LL_GPDMA1_REQUEST_TIM17_CC1 84U ¶

GPDMA1 HW Request is TIM17_CC1

LL_GPDMA1_REQUEST_TIM17_UPD 85U ¶

GPDMA1 HW Request is TIM17_UPD

LL_GPDMA1_REQUEST_DCMI_PSSI 86U ¶

GPDMA1 HW Request is DCMI_PSSI

LL_GPDMA1_REQUEST_AES_IN 87U ¶

GPDMA1 HW Request is AES_IN

LL_GPDMA1_REQUEST_AES_OUT 88U ¶

GPDMA1 HW Request is AES_OUT

LL_GPDMA1_REQUEST_HASH_IN 89U ¶

GPDMA1 HW Request is HASH_IN

LL_GPDMA1_REQUEST_UCPD1_TX 90U ¶

GPDMA1 HW Request is UCPD1_TX

LL_GPDMA1_REQUEST_UCPD1_RX 91U ¶

GPDMA1 HW Request is UCPD1_RX

LL_GPDMA1_REQUEST_MDF1_FLT0 92U ¶

GPDMA1 HW Request is MDF1_FLT0

LL_GPDMA1_REQUEST_MDF1_FLT1 93U ¶

GPDMA1 HW Request is MDF1_FLT1

LL_GPDMA1_REQUEST_MDF1_FLT2 94U ¶

GPDMA1 HW Request is MDF1_FLT2

LL_GPDMA1_REQUEST_MDF1_FLT3 95U ¶

GPDMA1 HW Request is MDF1_FLT3

LL_GPDMA1_REQUEST_MDF1_FLT4 96U ¶

GPDMA1 HW Request is MDF1_FLT4

LL_GPDMA1_REQUEST_MDF1_FLT5 97U ¶

GPDMA1 HW Request is MDF1_FLT5

LL_GPDMA1_REQUEST_ADF1_FLT0 98U ¶

GPDMA1 HW Request is ADF1_FLT0

LL_GPDMA1_REQUEST_FMAC_RD 99U ¶

GPDMA1 HW Request is FMAC_RD

LL_GPDMA1_REQUEST_FMAC_WR 100U ¶

GPDMA1 HW Request is FMAC_WR

LL_GPDMA1_REQUEST_CORDIC_RD 101U ¶

GPDMA1 HW Request is CORDIC_RD

LL_GPDMA1_REQUEST_CORDIC_WR 102U ¶

GPDMA1 HW Request is CORDIC_WR

LL_GPDMA1_REQUEST_SAES_IN 103U ¶

GPDMA1 HW Request is SAES_IN

LL_GPDMA1_REQUEST_SAES_OUT 104U ¶

GPDMA1 HW Request is SAES_OUT

LL_GPDMA1_REQUEST_LPTIM1_IC1 105U ¶

GPDMA1 HW Request is LPTIM1_IC1

LL_GPDMA1_REQUEST_LPTIM1_IC2 106U ¶

GPDMA1 HW Request is LPTIM1_IC2

LL_GPDMA1_REQUEST_LPTIM1_UE 107U ¶

GPDMA1 HW Request is LPTIM1_UE

LL_GPDMA1_REQUEST_LPTIM2_IC1 108U ¶

GPDMA1 HW Request is LPTIM2_IC1

LL_GPDMA1_REQUEST_LPTIM2_IC2 109U ¶

GPDMA1 HW Request is LPTIM2_IC2

LL_GPDMA1_REQUEST_LPTIM2_UE 110U ¶

GPDMA1 HW Request is LPTIM2_UE

LL_GPDMA1_REQUEST_LPTIM3_IC1 111U ¶

GPDMA1 HW Request is LPTIM3_IC1

LL_GPDMA1_REQUEST_LPTIM3_IC2 112U ¶

GPDMA1 HW Request is LPTIM3_IC2

LL_GPDMA1_REQUEST_LPTIM3_UE 113U ¶

GPDMA1 HW Request is LPTIM3_UE

LL_GPDMA1_REQUEST_HSPI1 114U ¶

GPDMA1 HW request is HSPI1

LL_GPDMA1_REQUEST_I2C5_RX 115U ¶

GPDMA1 HW request is I2C5_RX

LL_GPDMA1_REQUEST_I2C5_TX 116U ¶

GPDMA1 HW request is I2C5_TX

LL_GPDMA1_REQUEST_I2C5_EVC 117U ¶

GPDMA1 HW request is I2C5_EVC

LL_GPDMA1_REQUEST_I2C6_RX 118U ¶

GPDMA1 HW request is I2C6_RX

LL_GPDMA1_REQUEST_I2C6_TX 119U ¶

GPDMA1 HW request is I2C6_TX

LL_GPDMA1_REQUEST_I2C6_EVC 120U ¶

GPDMA1 HW request is I2C6_EVC

LL_GPDMA1_REQUEST_USART6_RX 121U ¶

GPDMA1 HW request is USART6_RX

LL_GPDMA1_REQUEST_USART6_TX 122U ¶

GPDMA1 HW request is USART6_TX

LL_GPDMA1_REQUEST_ADC2 123U ¶

GPDMA1 HW request is ADC2

LL_GPDMA1_REQUEST_JPEG_RX 124U ¶

GPDMA1 HW request is JPEG_TX

LL_GPDMA1_REQUEST_JPEG_TX 125U ¶

GPDMA1 HW request is JPEG_RX

LL_LPDMA1_REQUEST_LPUART1_RX 0U ¶

LPDMA1 HW Request is LPUART1_RX

LL_LPDMA1_REQUEST_LPUART1_TX 1U ¶

LPDMA1 HW Request is LPUART1_TX

LL_LPDMA1_REQUEST_SPI3_RX 2U ¶

LPDMA1 HW Request is SPI3_RX

LL_LPDMA1_REQUEST_SPI3_TX 3U ¶

LPDMA1 HW Request is SPI3_TX

LL_LPDMA1_REQUEST_I2C3_RX 4U ¶

LPDMA1 HW Request is I2C3_RX

LL_LPDMA1_REQUEST_I2C3_TX 5U ¶

LPDMA1 HW Request is I2C3_TX

LL_LPDMA1_REQUEST_I2C3_EVC 6U ¶

LPDMA1 HW Request is I2C3_EVC

LL_LPDMA1_REQUEST_ADC4 7U ¶

LPDMA1 HW Request is ADC4

LL_LPDMA1_REQUEST_DAC1_CH1 8U ¶

LPDMA1 HW Request is DAC1_CH1

LL_LPDMA1_REQUEST_DAC1_CH2 9U ¶

LPDMA1 HW Request is DAC1_CH2

LL_LPDMA1_REQUEST_ADF1_FLT0 10U ¶

LPDMA1 HW Request is ADF1_FLT0

LL_LPDMA1_REQUEST_LPTIM1_IC1 11U ¶

LPDMA1 HW Request is LPTIM1_IC1

LL_LPDMA1_REQUEST_LPTIM1_IC2 12U ¶

LPDMA1 HW Request is LPTIM1_IC2

LL_LPDMA1_REQUEST_LPTIM1_UE 13U ¶

LPDMA1 HW Request is LPTIM1_UE

LL_LPDMA1_REQUEST_LPTIM3_IC1 14U ¶

LPDMA1 HW Request is LPTIM3_IC1

LL_LPDMA1_REQUEST_LPTIM3_IC2 15U ¶

LPDMA1 HW Request is LPTIM3_IC2

LL_LPDMA1_REQUEST_LPTIM3_UE 16U ¶

LPDMA1 HW Request is LPTIM3_UE

Defines

LL_GPDMA1_REQUEST_ADC1 0U

GPDMA1 HW Request is ADC1

LL_GPDMA1_REQUEST_ADC4 1U

GPDMA1 HW Request is ADC4

LL_GPDMA1_REQUEST_DAC1_CH1 2U

GPDMA1 HW Request is DAC1_CH1

LL_GPDMA1_REQUEST_DAC1_CH2 3U

GPDMA1 HW Request is DAC1_CH2

LL_GPDMA1_REQUEST_TIM6_UPD 4U

GPDMA1 HW Request is TIM6_UPD

LL_GPDMA1_REQUEST_TIM7_UPD 5U

GPDMA1 HW Request is TIM7_UPD

LL_GPDMA1_REQUEST_SPI1_RX 6U

GPDMA1 HW Request is SPI1_RX

LL_GPDMA1_REQUEST_SPI1_TX 7U

GPDMA1 HW Request is SPI1_TX

LL_GPDMA1_REQUEST_SPI2_RX 8U

GPDMA1 HW Request is SPI2_RX

LL_GPDMA1_REQUEST_SPI2_TX 9U

GPDMA1 HW Request is SPI2_TX

LL_GPDMA1_REQUEST_SPI3_RX 10U

GPDMA1 HW Request is SPI3_RX

LL_GPDMA1_REQUEST_SPI3_TX 11U

GPDMA1 HW Request is SPI3_TX

LL_GPDMA1_REQUEST_I2C1_RX 12U

GPDMA1 HW Request is I2C1_RX

LL_GPDMA1_REQUEST_I2C1_TX 13U

GPDMA1 HW Request is I2C1_TX

LL_GPDMA1_REQUEST_I2C1_EVC 14U

GPDMA1 HW Request is I2C1_EVC

LL_GPDMA1_REQUEST_I2C2_RX 15U

GPDMA1 HW Request is I2C2_RX

LL_GPDMA1_REQUEST_I2C2_TX 16U

GPDMA1 HW Request is I2C2_TX

LL_GPDMA1_REQUEST_I2C2_EVC 17U

GPDMA1 HW Request is I2C2_EVC

LL_GPDMA1_REQUEST_I2C3_RX 18U

GPDMA1 HW Request is I2C3_RX

LL_GPDMA1_REQUEST_I2C3_TX 19U

GPDMA1 HW Request is I2C3_TX

LL_GPDMA1_REQUEST_I2C3_EVC 20U

GPDMA1 HW Request is I2C3_EVC

LL_GPDMA1_REQUEST_I2C4_RX 21U

GPDMA1 HW Request is I2C4_RX

LL_GPDMA1_REQUEST_I2C4_TX 22U

GPDMA1 HW Request is I2C4_TX

LL_GPDMA1_REQUEST_I2C4_EVC 23U

GPDMA1 HW Request is I2C4_EVC

LL_GPDMA1_REQUEST_USART1_RX 24U

GPDMA1 HW Request is USART1_RX

LL_GPDMA1_REQUEST_USART1_TX 25U

GPDMA1 HW Request is USART1_TX

LL_GPDMA1_REQUEST_USART2_RX 26U

GPDMA1 HW Request is USART2_RX

LL_GPDMA1_REQUEST_USART2_TX 27U

GPDMA1 HW Request is USART2_TX

LL_GPDMA1_REQUEST_USART3_RX 28U

GPDMA1 HW Request is USART3_RX

LL_GPDMA1_REQUEST_USART3_TX 29U

GPDMA1 HW Request is USART3_TX

LL_GPDMA1_REQUEST_UART4_RX 30U

GPDMA1 HW Request is UART4_RX

LL_GPDMA1_REQUEST_UART4_TX 31U

GPDMA1 HW Request is UART4_TX

LL_GPDMA1_REQUEST_UART5_RX 32U

GPDMA1 HW Request is UART5_RX

LL_GPDMA1_REQUEST_UART5_TX 33U

GPDMA1 HW Request is UART5_TX

LL_GPDMA1_REQUEST_LPUART1_RX 34U

GPDMA1 HW Request is LPUART1_RX

LL_GPDMA1_REQUEST_LPUART1_TX 35U

GPDMA1 HW Request is LPUART1_TX

LL_GPDMA1_REQUEST_SAI1_A 36U

GPDMA1 HW Request is SAI1_A

LL_GPDMA1_REQUEST_SAI1_B 37U

GPDMA1 HW Request is SAI1_B

LL_GPDMA1_REQUEST_SAI2_A 38U

GPDMA1 HW Request is SAI2_A

LL_GPDMA1_REQUEST_SAI2_B 39U

GPDMA1 HW Request is SAI2_B

LL_GPDMA1_REQUEST_OCTOSPI1 40U

GPDMA1 HW Request is OCTOSPI1

LL_GPDMA1_REQUEST_OCTOSPI2 41U

GPDMA1 HW Request is OCTOSPI2

LL_GPDMA1_REQUEST_TIM1_CC1 42U

GPDMA1 HW Request is TIM1_CC1

LL_GPDMA1_REQUEST_TIM1_CC2 43U

GPDMA1 HW Request is TIM1_CC2

LL_GPDMA1_REQUEST_TIM1_CC3 44U

GPDMA1 HW Request is TIM1_CC3

LL_GPDMA1_REQUEST_TIM1_CC4 45U

GPDMA1 HW Request is TIM1_CC4

LL_GPDMA1_REQUEST_TIM1_UPD 46U

GPDMA1 HW Request is TIM1_UPD

LL_GPDMA1_REQUEST_TIM1_TRGI 47U

GPDMA1 HW Request is TIM1_TRGI

LL_GPDMA1_REQUEST_TIM1_COM 48U

GPDMA1 HW Request is TIM1_COM

LL_GPDMA1_REQUEST_TIM8_CC1 49U

GPDMA1 HW Request is TIM8_CC1

LL_GPDMA1_REQUEST_TIM8_CC2 50U

GPDMA1 HW Request is TIM8_CC2

LL_GPDMA1_REQUEST_TIM8_CC3 51U

GPDMA1 HW Request is TIM8_CC3

LL_GPDMA1_REQUEST_TIM8_CC4 52U

GPDMA1 HW Request is TIM8_CC4

LL_GPDMA1_REQUEST_TIM8_UPD 53U

GPDMA1 HW Request is TIM8_UPD

LL_GPDMA1_REQUEST_TIM8_TRGI 54U

GPDMA1 HW Request is TIM8_TRGI

LL_GPDMA1_REQUEST_TIM8_COM 55U

GPDMA1 HW Request is TIM8_COM

LL_GPDMA1_REQUEST_TIM2_CC1 56U

GPDMA1 HW Request is TIM2_CC1

LL_GPDMA1_REQUEST_TIM2_CC2 57U

GPDMA1 HW Request is TIM2_CC2

LL_GPDMA1_REQUEST_TIM2_CC3 58U

GPDMA1 HW Request is TIM2_CC3

LL_GPDMA1_REQUEST_TIM2_CC4 59U

GPDMA1 HW Request is TIM2_CC4

LL_GPDMA1_REQUEST_TIM2_UPD 60U

GPDMA1 HW Request is TIM2_UPD

LL_GPDMA1_REQUEST_TIM3_CC1 61U

GPDMA1 HW Request is TIM3_CC1

LL_GPDMA1_REQUEST_TIM3_CC2 62U

GPDMA1 HW Request is TIM3_CC2

LL_GPDMA1_REQUEST_TIM3_CC3 63U

GPDMA1 HW Request is TIM3_CC3

LL_GPDMA1_REQUEST_TIM3_CC4 64U

GPDMA1 HW Request is TIM3_CC4

LL_GPDMA1_REQUEST_TIM3_UPD 65U

GPDMA1 HW Request is TIM3_UPD

LL_GPDMA1_REQUEST_TIM3_TRGI 66U

GPDMA1 HW Request is TIM3_TRGI

LL_GPDMA1_REQUEST_TIM4_CC1 67U

GPDMA1 HW Request is TIM4_CC1

LL_GPDMA1_REQUEST_TIM4_CC2 68U

GPDMA1 HW Request is TIM4_CC2

LL_GPDMA1_REQUEST_TIM4_CC3 69U

GPDMA1 HW Request is TIM4_CC3

LL_GPDMA1_REQUEST_TIM4_CC4 70U

GPDMA1 HW Request is TIM4_CC4

LL_GPDMA1_REQUEST_TIM4_UPD 71U

GPDMA1 HW Request is TIM4_UPD

LL_GPDMA1_REQUEST_TIM5_CC1 72U

GPDMA1 HW Request is TIM5_CC1

LL_GPDMA1_REQUEST_TIM5_CC2 73U

GPDMA1 HW Request is TIM5_CC2

LL_GPDMA1_REQUEST_TIM5_CC3 74U

GPDMA1 HW Request is TIM5_CC3

LL_GPDMA1_REQUEST_TIM5_CC4 75U

GPDMA1 HW Request is TIM5_CC4

LL_GPDMA1_REQUEST_TIM5_UPD 76U

GPDMA1 HW Request is TIM5_UPD

LL_GPDMA1_REQUEST_TIM5_TRGI 77U

GPDMA1 HW Request is TIM5_TRGI

LL_GPDMA1_REQUEST_TIM15_CC1 78U

GPDMA1 HW Request is TIM15_CC1

LL_GPDMA1_REQUEST_TIM15_UPD 79U

GPDMA1 HW Request is TIM15_UPD

LL_GPDMA1_REQUEST_TIM15_TRGI 80U

GPDMA1 HW Request is TIM15_TRGI

LL_GPDMA1_REQUEST_TIM15_COM 81U

GPDMA1 HW Request is TIM15_COM

LL_GPDMA1_REQUEST_TIM16_CC1 82U

GPDMA1 HW Request is TIM16_CC1

LL_GPDMA1_REQUEST_TIM16_UPD 83U

GPDMA1 HW Request is TIM16_UPD

LL_GPDMA1_REQUEST_TIM17_CC1 84U

GPDMA1 HW Request is TIM17_CC1

LL_GPDMA1_REQUEST_TIM17_UPD 85U

GPDMA1 HW Request is TIM17_UPD

LL_GPDMA1_REQUEST_DCMI_PSSI 86U

GPDMA1 HW Request is DCMI_PSSI

LL_GPDMA1_REQUEST_AES_IN 87U

GPDMA1 HW Request is AES_IN

LL_GPDMA1_REQUEST_AES_OUT 88U

GPDMA1 HW Request is AES_OUT

LL_GPDMA1_REQUEST_HASH_IN 89U

GPDMA1 HW Request is HASH_IN

LL_GPDMA1_REQUEST_UCPD1_TX 90U

GPDMA1 HW Request is UCPD1_TX

LL_GPDMA1_REQUEST_UCPD1_RX 91U

GPDMA1 HW Request is UCPD1_RX

LL_GPDMA1_REQUEST_MDF1_FLT0 92U

GPDMA1 HW Request is MDF1_FLT0

LL_GPDMA1_REQUEST_MDF1_FLT1 93U

GPDMA1 HW Request is MDF1_FLT1

LL_GPDMA1_REQUEST_MDF1_FLT2 94U

GPDMA1 HW Request is MDF1_FLT2

LL_GPDMA1_REQUEST_MDF1_FLT3 95U

GPDMA1 HW Request is MDF1_FLT3

LL_GPDMA1_REQUEST_MDF1_FLT4 96U

GPDMA1 HW Request is MDF1_FLT4

LL_GPDMA1_REQUEST_MDF1_FLT5 97U

GPDMA1 HW Request is MDF1_FLT5

LL_GPDMA1_REQUEST_ADF1_FLT0 98U

GPDMA1 HW Request is ADF1_FLT0

LL_GPDMA1_REQUEST_FMAC_RD 99U

GPDMA1 HW Request is FMAC_RD

LL_GPDMA1_REQUEST_FMAC_WR 100U

GPDMA1 HW Request is FMAC_WR

LL_GPDMA1_REQUEST_CORDIC_RD 101U

GPDMA1 HW Request is CORDIC_RD

LL_GPDMA1_REQUEST_CORDIC_WR 102U

GPDMA1 HW Request is CORDIC_WR

LL_GPDMA1_REQUEST_SAES_IN 103U

GPDMA1 HW Request is SAES_IN

LL_GPDMA1_REQUEST_SAES_OUT 104U

GPDMA1 HW Request is SAES_OUT

LL_GPDMA1_REQUEST_LPTIM1_IC1 105U

GPDMA1 HW Request is LPTIM1_IC1

LL_GPDMA1_REQUEST_LPTIM1_IC2 106U

GPDMA1 HW Request is LPTIM1_IC2

LL_GPDMA1_REQUEST_LPTIM1_UE 107U

GPDMA1 HW Request is LPTIM1_UE

LL_GPDMA1_REQUEST_LPTIM2_IC1 108U

GPDMA1 HW Request is LPTIM2_IC1

LL_GPDMA1_REQUEST_LPTIM2_IC2 109U

GPDMA1 HW Request is LPTIM2_IC2

LL_GPDMA1_REQUEST_LPTIM2_UE 110U

GPDMA1 HW Request is LPTIM2_UE

LL_GPDMA1_REQUEST_LPTIM3_IC1 111U

GPDMA1 HW Request is LPTIM3_IC1

LL_GPDMA1_REQUEST_LPTIM3_IC2 112U

GPDMA1 HW Request is LPTIM3_IC2

LL_GPDMA1_REQUEST_LPTIM3_UE 113U

GPDMA1 HW Request is LPTIM3_UE

LL_GPDMA1_REQUEST_HSPI1 114U

GPDMA1 HW request is HSPI1

LL_GPDMA1_REQUEST_I2C5_RX 115U

GPDMA1 HW request is I2C5_RX

LL_GPDMA1_REQUEST_I2C5_TX 116U

GPDMA1 HW request is I2C5_TX

LL_GPDMA1_REQUEST_I2C5_EVC 117U

GPDMA1 HW request is I2C5_EVC

LL_GPDMA1_REQUEST_I2C6_RX 118U

GPDMA1 HW request is I2C6_RX

LL_GPDMA1_REQUEST_I2C6_TX 119U

GPDMA1 HW request is I2C6_TX

LL_GPDMA1_REQUEST_I2C6_EVC 120U

GPDMA1 HW request is I2C6_EVC

LL_GPDMA1_REQUEST_USART6_RX 121U

GPDMA1 HW request is USART6_RX

LL_GPDMA1_REQUEST_USART6_TX 122U

GPDMA1 HW request is USART6_TX

LL_GPDMA1_REQUEST_ADC2 123U

GPDMA1 HW request is ADC2

LL_LPDMA1_REQUEST_LPUART1_RX 0U

LPDMA1 HW Request is LPUART1_RX

LL_LPDMA1_REQUEST_LPUART1_TX 1U

LPDMA1 HW Request is LPUART1_TX

LL_LPDMA1_REQUEST_SPI3_RX 2U

LPDMA1 HW Request is SPI3_RX

LL_LPDMA1_REQUEST_SPI3_TX 3U

LPDMA1 HW Request is SPI3_TX

LL_LPDMA1_REQUEST_I2C3_RX 4U

LPDMA1 HW Request is I2C3_RX

LL_LPDMA1_REQUEST_I2C3_TX 5U

LPDMA1 HW Request is I2C3_TX

LL_LPDMA1_REQUEST_I2C3_EVC 6U

LPDMA1 HW Request is I2C3_EVC

LL_LPDMA1_REQUEST_ADC4 7U

LPDMA1 HW Request is ADC4

LL_LPDMA1_REQUEST_DAC1_CH1 8U

LPDMA1 HW Request is DAC1_CH1

LL_LPDMA1_REQUEST_DAC1_CH2 9U

LPDMA1 HW Request is DAC1_CH2

LL_LPDMA1_REQUEST_ADF1_FLT0 10U

LPDMA1 HW Request is ADF1_FLT0

LL_LPDMA1_REQUEST_LPTIM1_IC1 11U

LPDMA1 HW Request is LPTIM1_IC1

LL_LPDMA1_REQUEST_LPTIM1_IC2 12U

LPDMA1 HW Request is LPTIM1_IC2

LL_LPDMA1_REQUEST_LPTIM1_UE 13U

LPDMA1 HW Request is LPTIM1_UE

LL_LPDMA1_REQUEST_LPTIM3_IC1 14U

LPDMA1 HW Request is LPTIM3_IC1

LL_LPDMA1_REQUEST_LPTIM3_IC2 15U

LPDMA1 HW Request is LPTIM3_IC2

LL_LPDMA1_REQUEST_LPTIM3_UE 16U

LPDMA1 HW Request is LPTIM3_UE