LL I2C Constants

Clear Flags Defines

group I2C_LL_EC_CLEAR_FLAG

Flags defines which can be used with LL_I2C_WRITE_REG function.

Defines

LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Get Flags Defines

group I2C_LL_EC_GET_FLAG

Flags defines which can be used with LL_I2C_READ_REG function.

Defines

LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

LL_I2C_ISR_DIR I2C_ISR_DIR

Direction

IT Defines

group I2C_LL_EC_IT

IT defines which can be used with LL_I2C_READ_REG and LL_I2C_WRITE_REG functions.

Defines

LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Peripheral Mode

group I2C_LL_EC_PERIPHERAL_MODE

Defines

LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

LL_I2C_MODE_SMBUS_SLAVE 0x00000000U

SMBus Slave default mode (Default address not acknowledge)

LL_I2C_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

SMBus Slave Default address acknowledge

Analog Filter Selection

group I2C_LL_EC_ANALOGFILTER_SELECTION

Defines

LL_I2C_ANALOGFILTER_ENABLE 0x00000000U

Analog filter is enabled.

LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Master Addressing Mode

group I2C_LL_EC_ADDRESSING_MODE

Defines

LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U

Master operates in 7-bit addressing mode.

LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Own Address 1 Length

group I2C_LL_EC_OWNADDRESS1

Defines

LL_I2C_OWNADDRESS1_7BIT 0x00000000U

Own address 1 is a 7-bit address.

LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Own Address 2 Masks

group I2C_LL_EC_OWNADDRESS2

Defines

LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Acknowledge Generation

group I2C_LL_EC_I2C_ACKNOWLEDGE

Defines

LL_I2C_ACK 0x00000000U

ACK is sent after current received byte.

LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Slave Address Length

group I2C_LL_EC_ADDRSLAVE

Defines

LL_I2C_ADDRSLAVE_7BIT 0x00000000U

Slave Address in 7-bit.

LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Transfer Request Direction

group I2C_LL_EC_REQUEST

Defines

LL_I2C_REQUEST_WRITE 0x00000000U

Master request a write transfer.

LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Transfer End Mode

group I2C_LL_EC_MODE

Defines

LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

LL_I2C_MODE_SOFTEND 0x00000000U

Enable I2C Software end mode with no HW PEC comparison.

LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)( LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)( LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Start And Stop Generation

group I2C_LL_EC_GENERATE

Defines

LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U

Don’t Generate Stop and Start condition.

LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Generate Stop condition (Size must be set to 0).

LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Start for write request.

LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 7Bit address.

LL_I2C_GENERATE_RESTART_10BIT_READ

(uint32_t)(0x80000000U | I2C_CR2_START | \

I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)


Generate Restart for read request, slave 10Bit address.

LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 10Bit address.

Read Write Direction

group I2C_LL_EC_DIRECTION

Defines

LL_I2C_DIRECTION_WRITE 0x00000000U

Write transfer request by master, slave enters receiver mode.

LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

DMA Register Data

group I2C_LL_EC_DMA_REG_DATA

Defines

LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

SMBus timeout_a Mode SCL SDA Timeout

group I2C_LL_EC_SMBUS_TIMEOUTA_MODE

Defines

LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U

timeout_a is used to detect SCL low level timeout.

LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

timeout_a is used to detect both SCL and SDA high level timeout.

SMBus Timeout Selection

group I2C_LL_EC_SMBUS_TIMEOUT_SELECTION

Defines

LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

timeout_a enable bit

LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

timeout_b (extended clock) enable bit

LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)( LL_I2C_SMBUS_TIMEOUTA | \ LL_I2C_SMBUS_TIMEOUTB )

timeout_a and timeout_b (extended clock) enable bits

Autonomous Trigger selection

group I2C_LL_EC_AUTOCR_TRIGSEL

I2C Autonomous Trigger selection.

Defines

LL_I2C_TRIG_GRP1 (0x10000000U)

Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product)

LL_I2C_TRIG_GRP2 (0x20000000U)

Trigger Group for I2C3

LL_I2C_TRIG_GRP1_GPDMA1_CH0_TC (uint32_t)( LL_I2C_TRIG_GRP1 | (0x00000000U))

HW Trigger signal is GPDMA_CH0

LL_I2C_TRIG_GRP1_GPDMA1_CH1_TC (uint32_t)( LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is GPDMA_CH1

LL_I2C_TRIG_GRP1_GPDMA1_CH2_TC (uint32_t)( LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is GPDMA_CH2

LL_I2C_TRIG_GRP1_GPDMA1_CH3_TC (uint32_t)( LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is GPDMA_CH3

LL_I2C_TRIG_GRP1_EXTI5 (uint32_t)( LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI5

LL_I2C_TRIG_GRP1_EXTI9 (uint32_t)( LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI9

LL_I2C_TRIG_GRP1_LPTIM1_CH1 (uint32_t)( LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM1_CH1

LL_I2C_TRIG_GRP1_LPTIM2_CH1 (uint32_t)( LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM2_CH1

LL_I2C_TRIG_GRP1_COMP1_OUT (uint32_t)( LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP1_OUT

LL_I2C_TRIG_GRP1_COMP2_OUT (uint32_t)( LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP2_OUT

LL_I2C_TRIG_GRP1_RTC_ALRA_TRG (uint32_t)( LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_ALRA_TRG

LL_I2C_TRIG_GRP1_RTC_WUT_TRG (uint32_t)( LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_WUT_TRG

LL_I2C_TRIG_GRP2_LPDMA1_CH0_TC (uint32_t)( LL_I2C_TRIG_GRP2 | (0x00000000U))

HW Trigger signal is LPDMA_CH0

LL_I2C_TRIG_GRP2_LPDMA1_CH1_TC (uint32_t)( LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPDMA_CH1

LL_I2C_TRIG_GRP2_LPDMA1_CH2_TC (uint32_t)( LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPDMA_CH2

LL_I2C_TRIG_GRP2_LPDMA1_CH3_TC (uint32_t)( LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPDMA_CH3

LL_I2C_TRIG_GRP2_EXTI5 (uint32_t)( LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI5

LL_I2C_TRIG_GRP2_EXTI8 (uint32_t)( LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI8

LL_I2C_TRIG_GRP2_LPTIM1_CH1 (uint32_t)( LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM1_CH1

LL_I2C_TRIG_GRP2_LPTIM3_CH1 (uint32_t)( LL_I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM3_CH1

LL_I2C_TRIG_GRP2_COMP1_OUT (uint32_t)( LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP1_OUT

LL_I2C_TRIG_GRP2_COMP2_OUT (uint32_t)( LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP2_OUT

LL_I2C_TRIG_GRP2_RTC_ALRA_TRG (uint32_t)( LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_ALRA_TRG

LL_I2C_TRIG_GRP2_RTC_WUT_TRG (uint32_t)( LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_WUT_TRG

Autonomous Trigger Polarity

group I2C_LL_EC_AUTOCR_TRIGPOL

I2C Autonomous Trigger Polarity.

Defines

LL_I2C_TRIG_POLARITY_RISING 0x00000000U

I2C triggered on rising edge

LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL

I2C triggered on falling edge