LL RCC Constants

LSI prescaler

group RCC_LL_EC_LSIPRE

Defines

LL_RCC_LSI_DIV_1 0x00000000U

LSI divided by 1

LL_RCC_LSI_DIV_128 RCC_BDCR_LSIPREDIV

LSI divided by 128

LSE oscillator drive capability

group RCC_LL_EC_LSEDRIVE

Defines

LL_RCC_LSEDRIVE_LOW 0x00000000U

Xtal mode lower driving capability

LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

Xtal mode medium low driving capability

LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

Xtal mode medium high driving capability

LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

MSI clock Trimming

group RCC_LL_EC_MSI_OSCILLATOR

Defines

LL_RCC_MSI_OSCILLATOR_0 0x00000000U

MSI clock trimming for ranges 0 to 3

LL_RCC_MSI_OSCILLATOR_1 0x00000005U

MSI clock trimming for ranges 4 to 7

LL_RCC_MSI_OSCILLATOR_2 0x0000000AU

MSI clock trimming for ranges 8 to 11

LL_RCC_MSI_OSCILLATOR_3 0x0000000FU

MSI clock trimming for ranges 12 to 15

MSIS Clock Range

group RCC_LL_EC_MSISRANGE

Defines

LL_RCC_MSISRANGE_0 0x00000000U

MSIS = 48 MHz

LL_RCC_MSISRANGE_1 RCC_ICSCR1_MSISRANGE_0

MSIS = 24 MHz

LL_RCC_MSISRANGE_2 RCC_ICSCR1_MSISRANGE_1

MSIS = 16 MHz

LL_RCC_MSISRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1)

MSIS = 12 MHz

LL_RCC_MSISRANGE_4 RCC_ICSCR1_MSISRANGE_2

MSIS = 4 MHz

LL_RCC_MSISRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2)

MSIS = 2 MHz

LL_RCC_MSISRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2)

MSIS = 1.5 MHz

LL_RCC_MSISRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2)

MSIS = 1 MHz

LL_RCC_MSISRANGE_8 RCC_ICSCR1_MSISRANGE_3

MSIS = 3.072 MHz

LL_RCC_MSISRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3)

MSIS = 1.536 MHz

LL_RCC_MSISRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3)

MSIS = 1.024 MHz

LL_RCC_MSISRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3)

MSIS = 768 kHz

LL_RCC_MSISRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3)

MSIS = 400 kHz

LL_RCC_MSISRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3)

MSIS = 200 kHz

LL_RCC_MSISRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3)

MSIS = 150 kHz

LL_RCC_MSISRANGE_15

(RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 | \

RCC_ICSCR1_MSISRANGE_3)


MSIS = 100 kHz

MSIK Clock Range

group RCC_LL_EC_MSIKRANGE

Defines

LL_RCC_MSIKRANGE_0 0x00000000U

MSIK = 48 MHz

LL_RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0

MSIK = 24 MHz

LL_RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1

MSIK = 16 MHz

LL_RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1)

MSIK = 12 MHz

LL_RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2

MSIK = 4 MHz

LL_RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2)

MSIK = 2 MHz

LL_RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2)

MSIK = 1.5 MHz

LL_RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2)

MSIK = 1 MHz

LL_RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3

MSIK = 3.072 MHz

LL_RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3)

MSIK = 1.536 MHz

LL_RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3)

MSIK = 1.024 MHz

LL_RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3)

MSIK = 768 kHz

LL_RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3)

MSIK = 400 kHz

LL_RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3)

MSIK = 200 kHz

LL_RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3)

MSIK = 150 kHz

LL_RCC_MSIKRANGE_15

(RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | \

RCC_ICSCR1_MSIKRANGE_3)


MSIK = 100 kHz

MSIS range after Standby mode

group RCC_LL_EC_MSISSRANGE

Defines

LL_RCC_MSISSRANGE_4 RCC_CSR_MSISSRANGE_2

MSIS = 4 MHz

LL_RCC_MSISSRANGE_5 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_0)

MSIS = 2 MHz

LL_RCC_MSISSRANGE_6 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1)

MSIS = 1.5 MHz

LL_RCC_MSISSRANGE_7 (RCC_CSR_MSISSRANGE_0 | RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1)

MSIS = 1 MHz

LL_RCC_MSISSRANGE_8 RCC_CSR_MSISSRANGE_3

MSIS = 3.072 MHz

MSIK range after Standby mode

group RCC_LL_EC_MSIKSRANGE

Defines

LL_RCC_MSIKSRANGE_4 RCC_CSR_MSIKSRANGE_2

MSIK = 4 MHz

LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0)

MSIK = 2 MHz

LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1)

MSIK = 1.5 MHz

LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0)

MSIK = 1 MHz

LL_RCC_MSIKSRANGE_8 RCC_CSR_MSIKSRANGE_3

MSIK = 3.072 MHz

MSIS/MSIK Pll Mode

group RCC_LL_EC_MSIPLLMODE

Defines

LL_RCC_PLLMODE_MSIK 0U

MSIK selection for Pll Mode

LL_RCC_PLLMODE_MSIS RCC_CR_MSIPLLSEL

MSIS selection for Pll Mode

MSI PLL mode fast startup

group RCC_LL_EC_MSIPLLFAST_ACTIVATION

Defines

LL_RCC_PLLFAST_NORMAL 0U

MSI PLL normal start-up

LL_RCC_PLLFAST_FAST RCC_CR_MSIPLLFAST

MSI PLL fast start-up

MSI BIAS Mode

group RCC_LL_EC_MSIBIASMODE

Defines

LL_RCC_MSIBIASMODE_SAMPLING RCC_ICSCR1_MSIBIAS

Sampling mode selection for MSI

LL_RCC_MSIBIASMODE_CONTINUOUS 0U

Continuous mode selection for MSI

EXTERNAL HSE Mode

group RCC_LL_EC_HSEEXT

Defines

LL_RCC_HSE_ANALOG_MODE 0U

HSE clock used as ANALOG clock source

LL_RCC_HSE_DIGITAL_MODE RCC_CR_HSEEXT

HSE clock used as DIGITAL clock source

LSCO Selection

group RCC_LL_EC_LSCO_CLKSOURCE

Defines

LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U

LSI selection for low speed clock

LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock

EPOD prescaler

group RCC_LL_EC_PLL1MBOOST_DIV

Defines

LL_RCC_PLL1MBOOST_DIV_1 0x00000000U

PLL1CLK not divided

LL_RCC_PLL1MBOOST_DIV_2 RCC_PLL1CFGR_PLL1MBOOST_0

PLL1CLK divided by 2

LL_RCC_PLL1MBOOST_DIV_4 RCC_PLL1CFGR_PLL1MBOOST_1

PLL1CLK divided by 4

LL_RCC_PLL1MBOOST_DIV_6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0)

PLL1CLK divided by 6

LL_RCC_PLL1MBOOST_DIV_8 RCC_PLL1CFGR_PLL1MBOOST_2

PLL1CLK divided by 8

LL_RCC_PLL1MBOOST_DIV_10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0)

PLL1CLK divided by 10

LL_RCC_PLL1MBOOST_DIV_12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1)

PLL1CLK divided by 12

LL_RCC_PLL1MBOOST_DIV_14

(RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1 | \

RCC_PLL1CFGR_PLL1MBOOST_0)


PLL1CLK divided by 14

LL_RCC_PLL1MBOOST_DIV_16 RCC_PLL1CFGR_PLL1MBOOST_3

PLL1CLK divided by 16

System clock switch

group RCC_LL_EC_SYS_CLKSOURCE

Defines

LL_RCC_SYS_CLKSOURCE_MSIS 0x00000000U

MSIS selection as system clock

LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR1_SW_0

HSI oscillator selection as system clock

LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1

HSE selection as system clock

LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0)

PLL selection as system clock

System clock switch status

group RCC_LL_EC_SYS_CLKSOURCE_STATUS

Defines

LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 0x00000000U

MSIS used as system clock

LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0

HSI used as system clock

LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1

HSE used as system clock

LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0)

PLL1 used as system clock

SYSTICK clock source selection

group RCC_LL_EC_SYSTICK_CLKSOURCE

Defines

LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U

HCLKDIV8 clock used as SYSTICK clock source

LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0

LSI clock used as SYSTICK clock source

LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1

LSE clock used as SYSTICK clock source

AHB prescaler

group RCC_LL_EC_SYSCLK_DIV

Defines

LL_RCC_HCLK_PRESCALER_1 0x00000000U

SYSCLK not divided

LL_RCC_HCLK_PRESCALER_2 RCC_CFGR2_HPRE_3

SYSCLK divided by 2

LL_RCC_HCLK_PRESCALER_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0)

SYSCLK divided by 4

LL_RCC_HCLK_PRESCALER_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1)

SYSCLK divided by 8

LL_RCC_HCLK_PRESCALER_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)

SYSCLK divided by 16

LL_RCC_HCLK_PRESCALER_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2)

SYSCLK divided by 64

LL_RCC_HCLK_PRESCALER_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0)

SYSCLK divided by 128

LL_RCC_HCLK_PRESCALER_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1)

SYSCLK divided by 256

LL_RCC_HCLK_PRESCALER_512 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0

SYSCLK divided by 512

APB low-speed prescaler (APB1)

group RCC_LL_EC_APB1_DIV

Defines

LL_RCC_APB1_PRESCALER_1 0x00000000U

HCLK not divided

LL_RCC_APB1_PRESCALER_2 RCC_CFGR2_PPRE1_2

HCLK divided by 2

LL_RCC_APB1_PRESCALER_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0)

HCLK divided by 4

LL_RCC_APB1_PRESCALER_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1)

HCLK divided by 8

LL_RCC_APB1_PRESCALER_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)

HCLK divided by 16

APB high-speed prescaler (APB2)

group RCC_LL_EC_APB2_DIV

Defines

LL_RCC_APB2_PRESCALER_1 0x00000000U

HCLK not divided

LL_RCC_APB2_PRESCALER_2 RCC_CFGR2_PPRE2_2

HCLK divided by 2

LL_RCC_APB2_PRESCALER_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0)

HCLK divided by 4

LL_RCC_APB2_PRESCALER_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1)

HCLK divided by 8

LL_RCC_APB2_PRESCALER_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)

HCLK divided by 16

APB high-speed prescaler (APB3)

group RCC_LL_EC_APB3_DIV

Defines

LL_RCC_APB3_PRESCALER_1 0x00000000U

HCLK not divided

LL_RCC_APB3_PRESCALER_2 RCC_CFGR3_PPRE3_2

HCLK divided by 2

LL_RCC_APB3_PRESCALER_4 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_0)

HCLK divided by 4

LL_RCC_APB3_PRESCALER_8 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1)

HCLK divided by 8

LL_RCC_APB3_PRESCALER_16 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1 | RCC_CFGR3_PPRE3_0)

HCLK divided by 16

DSI PHY clock prescaler (DCLK)

group RCC_LL_EC_DPHY_DIV

Defines

LL_RCC_DPHY_DIV_1 0x00000000U

DCLK not divided

LL_RCC_DPHY_DIV_2 RCC_CFGR2_PPRE_DPHY_2

DCLK divided by 2

LL_RCC_DPHY_DIV_4 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_0)

DCLK divided by 4

LL_RCC_DPHY_DIV_8 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1)

DCLK divided by 8

LL_RCC_DPHY_DIV_16 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1 | RCC_CFGR2_PPRE_DPHY_0)

DCLK divided by 16

Wakeup from Stop and CSS backup clock selection

group RCC_LL_EC_STOP_WAKEUPCLOCK

Defines

LL_RCC_STOP_WAKEUPCLOCK_MSIS 0x00000000U

MSIS selection after wake-up from STOP

LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK

HSI selection after wake-up from STOP

Wakeup from Stop kernel clock automatic enable selection

group RCC_LL_EC_STOP_WAKEUPKERCLOCK

Defines

LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 0x00000000U

MSIK oscillator automatically enabled when exiting Stop mode

LL_RCC_STOP_WAKEUPKERCLOCK_HSI RCC_CFGR1_STOPKERWUCK

HSI oscillator automatically enabled when exiting Stop mode

MCO1 SOURCE selection

group RCC_LL_EC_MCO1SOURCE

Defines

LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U

MCO output disabled, no clock on MCO

LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0

SYSCLK selection as MCO1 source

LL_RCC_MCO1SOURCE_MSIS RCC_CFGR1_MCOSEL_1

MSIS selection as MCO1 source

LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1)

HSI selection as MCO1 source

LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2

HSE selection as MCO1 source

LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2)

Main PLL selection as MCO1 source

LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2)

LSI selection as MCO1 source

LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2

LSE selection as MCO1 source

LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3

HSI48 selection as MCO1 source

LL_RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3)

MSIK selection as MCO1 source

MCO1 prescaler

group RCC_LL_EC_MCO1_DIV

Defines

LL_RCC_MCO1_PRESCALER_1 0x00000000U

MCO not divided

LL_RCC_MCO1_PRESCALER_2 RCC_CFGR1_MCOPRE_0

MCO divided by 2

LL_RCC_MCO1_PRESCALER_4 RCC_CFGR1_MCOPRE_1

MCO divided by 4

LL_RCC_MCO1_PRESCALER_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0)

MCO divided by 8

LL_RCC_MCO1_PRESCALER_16 RCC_CFGR1_MCOPRE_2

MCO divided by 16

RTC clock source selection

group RCC_LL_EC_RTC_CLKSOURCE

Defines

LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Peripheral USARTx clock source selection

group RCC_LL_EC_USART_CLKSOURCE

Defines

LL_RCC_USART1_CLKSOURCE_PCLK2 (( RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos << 16U))

PCLK2 clock used as USART1 clock source

LL_RCC_USART1_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC_CCIPR1_USART1SEL_Pos))

SYSCLK clock used as USART1 clock source

LL_RCC_USART1_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC_CCIPR1_USART1SEL_Pos))

HSI clock used as USART1 clock source

LL_RCC_USART1_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos))

LSE clock used as USART1 clock source

LL_RCC_USART2_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U))

PCLK1 clock used as USART2 clock source

LL_RCC_USART2_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC_CCIPR1_USART2SEL_Pos))

SYSCLK clock used as USART2 clock source

LL_RCC_USART2_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC_CCIPR1_USART2SEL_Pos))

HSI clock used as USART2 clock source

LL_RCC_USART2_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos))

LSE clock used as USART2 clock source

LL_RCC_USART3_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U))

PCLK3 clock used as USART3 clock source

LL_RCC_USART3_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_0 >> RCC_CCIPR1_USART3SEL_Pos))

SYSCLK clock used as USART3 clock source

LL_RCC_USART3_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_1 >> RCC_CCIPR1_USART3SEL_Pos))

HSI clock used as USART3 clock source

LL_RCC_USART3_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos))

LSE clock used as USART3 clock source

LL_RCC_USART6_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U))

PCLK1 clock used as USART6 clock source

LL_RCC_USART6_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_0 >> RCC_CCIPR2_USART6SEL_Pos))

SYSCLK clock used as USART6 clock source

LL_RCC_USART6_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_1 >> RCC_CCIPR2_USART6SEL_Pos))

HSI clock used as USART6 clock source

LL_RCC_USART6_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos))

LSE clock used as USART6 clock source

LL_RCC_USART6_CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK1

Peripheral UARTx clock source selection

group RCC_LL_EC_UART_CLKSOURCE

Defines

LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U)

PCLK1 clock used as UART4 clock source

LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0)

SYSCLK clock used as UART4 clock source

LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1)

HSI clock used as UART4 clock source

LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL)

LSE clock used as UART4 clock source

LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U)

PCLK1 clock used as UART5 clock source

LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0)

SYSCLK clock used as UART5 clock source

LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1)

HSI clock used as UART5 clock source

LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL)

LSE clock used as UART5 clock source

Peripheral LPUARTx clock source selection

group RCC_LL_EC_LPUART_CLKSOURCE

Defines

LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U

PCLK3 clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0

SYSCLK clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1

HSI clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1)

LSE clock used as LPUART1 clock source

LL_RCC_LPUART1_CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2

MSIK clock used as LPUART1 clock source

Peripheral I2Cx clock source selection

group RCC_LL_EC_I2C_CLKSOURCE

Defines

LL_RCC_I2C1_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U))

PCLK1 clock used as I2C1 clock source

LL_RCC_I2C1_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos))


SYSCLK clock used as I2C1 clock source

LL_RCC_I2C1_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos))


HSI clock used as I2C1 clock source

LL_RCC_I2C1_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos))


MSIK clock used as I2C1 clock source

LL_RCC_I2C2_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U))

PCLK1 clock used as I2C2 clock source

LL_RCC_I2C2_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos))


SYSCLK clock used as I2C2 clock source

LL_RCC_I2C2_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos))


HSI clock used as I2C2 clock source

LL_RCC_I2C2_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos))


MSIK clock used as I2C2 clock source

LL_RCC_I2C3_CLKSOURCE_PCLK3 (( RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U))

PCLK3 clock used as I2C3 clock source

LL_RCC_I2C3_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \

(RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos))


SYSCLK clock used as I2C3 clock source

LL_RCC_I2C3_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \

(RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos))


HSI clock used as I2C3 clock source

LL_RCC_I2C3_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \

(RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos))


MSIK clock used as I2C3 clock source

LL_RCC_I2C4_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U))

PCLK1 clock used as I2C4 clock source

LL_RCC_I2C4_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos))


SYSCLK clock used as I2C4 clock source

LL_RCC_I2C4_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos))


HSI clock used as I2C4 clock source

LL_RCC_I2C4_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos))


MSIK clock used as I2C4 clock source

LL_RCC_I2C5_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U))

PCLK1 clock used as I2C5 clock source

LL_RCC_I2C5_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos))


SYSCLK clock used as I2C5 clock source

LL_RCC_I2C5_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C5SEL_1 >> RCC_CCIPR2_I2C5SEL_Pos))


HSI clock used as I2C5 clock source

LL_RCC_I2C5_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos))


MSIK clock used as I2C5 clock source

LL_RCC_I2C6_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U))

PCLK1 clock used as I2C6 clock source

LL_RCC_I2C6_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C6SEL_0 >> RCC_CCIPR2_I2C6SEL_Pos))


SYSCLK clock used as I2C6 clock source

LL_RCC_I2C6_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C6SEL_1 >> RCC_CCIPR2_I2C6SEL_Pos))


HSI clock used as I2C6 clock source

LL_RCC_I2C6_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos))


MSIK clock used as I2C6 clock source

Peripheral SPIx clock source selection

group RCC_LL_EC_SPI_CLKSOURCE

Defines

LL_RCC_SPI1_CLKSOURCE_PCLK2 (( RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U))

PCLK2 clock used as SPI1 clock source

LL_RCC_SPI1_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos))


SYSCLK clock used as SPI1 clock source

LL_RCC_SPI1_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos))


HSI clock used as SPI1 clock source

LL_RCC_SPI1_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos))


MSIK clock used as SPI1 clock source

LL_RCC_SPI2_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U))

PCLK1 clock used as SPI2 clock source

LL_RCC_SPI2_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos))


SYSCLK clock used as SPI2 clock source

LL_RCC_SPI2_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos))


HSI clock used as SPI2 clock source

LL_RCC_SPI2_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos))


MSIK clock used as SPI2 clock source

LL_RCC_SPI3_CLKSOURCE_PCLK3 (( RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U))

PCLK3 clock used as SPI3 clock source

LL_RCC_SPI3_CLKSOURCE_SYSCLK (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \

(RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos))


SYSCLK clock used as SPI3 clock source

LL_RCC_SPI3_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \

(RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos))


HSI clock used as SPI3 clock source

LL_RCC_SPI3_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \

(RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos))


MSIK clock used as SPI3 clock source

Peripheral LPTIMx clock source selection

group RCC_LL_EC_LPTIM_CLKSOURCE

Defines

LL_RCC_LPTIM1_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U))

MSIK clock used as LPTIM1 clock source

LL_RCC_LPTIM1_CLKSOURCE_LSI (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos))


LSI clock used as LPTIM1 clock source

LL_RCC_LPTIM1_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos))


HSI clock used as LPTIM1 clock source

LL_RCC_LPTIM1_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos))


LSE clock used as LPTIM1 clock source

LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (( RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U))

PCLK1 clock used as LPTIM2 clock source

LL_RCC_LPTIM2_CLKSOURCE_LSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \

(RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos))


LSI clock used as LPTIM2 clock source

LL_RCC_LPTIM2_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \

(RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos))


HSI clock used as LPTIM2 clock source

LL_RCC_LPTIM2_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \

(RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos))


LSE clock used as LPTIM2 clock source

LL_RCC_LPTIM34_CLKSOURCE_MSIK (( RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U))

MSIK clock used as LPTIM34 clock source

LL_RCC_LPTIM34_CLKSOURCE_LSI (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM34SEL_0 >> RCC_CCIPR3_LPTIM34SEL_Pos))


LSI clock used as LPTIM34 clock source

LL_RCC_LPTIM34_CLKSOURCE_HSI (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM34SEL_1 >> RCC_CCIPR3_LPTIM34SEL_Pos))


HSI clock used as LPTIM34 clock source

LL_RCC_LPTIM34_CLKSOURCE_LSE (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos))


LSE clock used as LPTIM34 clock source

Peripheral FDCAN kernel clock source selection

group RCC_LL_EC_FDCAN_CLKSOURCE

Defines

LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U

HSE clock used as FDCAN kernel clock source

LL_RCC_FDCAN_CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0

PLL1 Q clock used as FDCAN kernel clock source

LL_RCC_FDCAN_CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1

PLL2 P clock used as FDCAN kernel clock source

Peripheral SAIx clock source selection

group RCC_LL_EC_SAI_CLKSOURCE

Defines

LL_RCC_SAI1_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI1SEL << 16U)

PLL2 clock used as SAI1 clock source

LL_RCC_SAI1_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0)

PLL3 clock used as SAI1 clock source

LL_RCC_SAI1_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1)

PLL1 clock used as SAI1 clock source

LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2)

HSI clock used as SAI1 clock source

LL_RCC_SAI1_CLKSOURCE_PIN

((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \

RCC_CCIPR2_SAI1SEL_0))


External input clock used as SAI1 clock source

LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U)

PLL2 clock used as SAI2 clock source

LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0)

PLL3 clock used as SAI2 clock source

LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1)

PLL1clock used as SAI2 clock source

LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2)

HSI clock used as SAI2 clock source

LL_RCC_SAI2_CLKSOURCE_PIN

((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \

RCC_CCIPR2_SAI2SEL_0))


External input clock used as SAI2 clock source

Peripheral SDMMC1/2 kernel clock source selection

group RCC_LL_EC_SDMMC_KERNELCLKSOURCE

Defines

LL_RCC_SDMMC12_KERCLKSOURCE_48CLK 0x00000000U

48MHz clock from internal multiplexor used as SDMMC1/2 clock source

LL_RCC_SDMMC12_KERCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL

PLL1 “P” used as SDMMC1/2 clock source

Peripheral SDMMC clock source selection

group RCC_LL_EC_SDMMC12_CLKSOURCE

Defines

LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U

HSI48 clock used as SDMMC1/2 clock source

LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0

PLL2 “Q” clock used as SDMMC1/2 clock source

LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1

PLL1 “Q” clock used as SDMMC1/2 clock source

LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL

MSIK clock used as SDMMC1/2 clock source

Peripheral RNG clock source selection

group RCC_LL_EC_RNG_CLKSOURCE

Defines

LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U

HSI48 clock used as RNG clock source

LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0

HSI48/2 clock used as RNG clock source

LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1

HSI clock used as RNG clock source

Peripheral USB clock source selection

group RCC_LL_EC_USB_CLKSOURCE

Defines

LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U

HSI48 clock used as USB clock source

LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0

PLL2 “Q” clock used as USB clock source

LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1

PLL1 “Q” clock used as USB clock source

LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL

MSIK clock used as USB clock source

Peripheral ADCx and DAC1 clock source selection

group RCC_LL_EC_ADCDAC_CLKSOURCE

Defines

LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U

No clock used as ADCx/DAC1 clock source

LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0

SYSCLK clock used as ADCx/DAC1 clock source

LL_RCC_ADCDAC_CLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1

PLL2 clock used as ADCx/DAC1 clock source

LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2

HSI clock used as ADCx/DAC1 clock source

LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_1 | RCC_CCIPR3_ADCDACSEL_0)

HSE clock used as ADCx/DAC1 clock source

LL_RCC_ADCDAC_CLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_2 | RCC_CCIPR3_ADCDACSEL_0)

MSIK clock used as ADCx/DAC1 clock source

Peripheral DAC1 clock source selection

group RCC_LL_EC_DAC1_CLKSOURCE

Defines

LL_RCC_DAC1_CLKSOURCE_LSE 0x00000000U

LSE clock used as DAC1 clock

LL_RCC_DAC1_CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL

LSI clock used as DAC1 clock

Peripheral ADF1 clock source selection

group RCC_LL_EC_ADF1_CLKSOURCE

Defines

LL_RCC_ADF1_CLKSOURCE_HCLK 0x00000000U

HCLK clock used as ADF1 clock

LL_RCC_ADF1_CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0

PLL1 clock used as ADF1 clock

LL_RCC_ADF1_CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1

PLL3 clock used as ADF1 clock

LL_RCC_ADF1_CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2

MSIK clock used as ADF1 clock

LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_1 | RCC_CCIPR3_ADF1SEL_0)

PIN SAI1_EXTCLK clock used as ADF1 clock

Peripheral MDF1 clock source selection

group RCC_LL_EC_MDF1_CLKSOURCE

Defines

LL_RCC_MDF1_CLKSOURCE_HCLK 0x00000000U

HCLK clock used as MDF1 clock

LL_RCC_MDF1_CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0

PLL1 clock used as MDF1 clock

LL_RCC_MDF1_CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1

PLL3 clock used as MDF1 clock

LL_RCC_MDF1_CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2

MSIK clock used as MDF1 clock

LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_1 | RCC_CCIPR2_MDF1SEL_0)

PIN SAI1_EXTCLK clock used as MDF1 clock

Peripheral OCTOSPI kernel clock source selection

group RCC_LL_EC_OCTOSPI_CLKSOURCE

Defines

LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U

SYSCLK clock used as OctoSPI kernel clock source

LL_RCC_OCTOSPI_CLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0

MSIK clock used as OctoSPI kernel clock source

LL_RCC_OCTOSPI_CLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1

PLL1 “Q” clock used as OctoSPI kernel clock source

LL_RCC_OCTOSPI_CLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0)

PLL2 “Q” clock used as OctoSPI kernel clock source

Peripheral HSPI1 kernel clock source selection

group RCC_LL_EC_HSPI1_CLKSOURCE

Defines

LL_RCC_HSPI_CLKSOURCE_SYSCLK 0U
LL_RCC_HSPI_CLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0
LL_RCC_HSPI_CLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1
LL_RCC_HSPI_CLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL

TIM Input capture clock source selection

group RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource

Defines

LL_RCC_TIMIC_CLKSOURCE_NONE 0x00000000U

No clock available for TIM16/TIM17 and LPTIM2 input capture

LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL_2

HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture

LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 RCC_CCIPR1_TIMICSEL_2

MSIS/1024 selected for TIM16/TIM17 and LPTIM2 input capture

LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1)

MSIS/4 selected for TIM16/TIM17 and LPTIM2 input capture

LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0)

MSIK/4 selected for TIM16/TIM17 and LPTIM2 input capture

LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024

(RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | \

RCC_CCIPR1_TIMICSEL_0)


MSIK/1024 selected for TIM16/TIM17 and LPTIM2 input capture

Peripheral SAES clock source selection

group RCC_LL_EC_SAES_CLKSOURCE

Defines

LL_RCC_SAES_CLKSOURCE_SHSI 0x00000000U

SHSI clock used as SAES clock source

LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL

SHSI_DIV2 clock used as SAES clock source

Peripheral USARTx get clock source

group RCC_LL_EC_USART

Defines

LL_RCC_USART1_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_USART1SEL_Pos << 16U) | \

(RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos))


USART1 Clock source selection

LL_RCC_USART2_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_USART2SEL_Pos << 16U) | \

(RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos))


USART2 Clock source selection

LL_RCC_USART3_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_USART3SEL_Pos << 16U) | \

(RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos))


USART3 Clock source selection

LL_RCC_USART6_CLKSOURCE (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | \

(RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos))


USART6 Clock source selection

Peripheral UARTx get clock source

group RCC_LL_EC_UART

Defines

LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL

UART4 Clock source selection

LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL

UART5 Clock source selection

Peripheral SPIx get clock source

group RCC_LL_EC_SPI

Defines

LL_RCC_SPI1_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos))


SPI1 Clock source selection

LL_RCC_SPI2_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \

(RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos))


SPI2 Clock source selection

LL_RCC_SPI3_CLKSOURCE (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \

(RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos))


SPI3 Clock source selection

Peripheral LPUARTx get clock source

group RCC_LL_EC_LPUART

Defines

LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL

LPUART1 Clock source selection

Peripheral DSI clock source selection

group RCC_LL_EC_DSI_CLKSOURCE

Defines

LL_RCC_DSI_CLKSOURCE_PLL3 0U

PLL3 “P” (pll3_p_ck) selected

LL_RCC_DSI_CLKSOURCE_PHY RCC_CCIPR2_DSIHOSTSEL

DSI PHY PLL output selected

Peripheral LTDC clock source selection

group RCC_LL_EC_LTDC_CLKSOURCE

Defines

LL_RCC_LTDC_CLKSOURCE_PLL3 0U

PLL3 “R” (pll3_r_ck) selected

LL_RCC_LTDC_CLKSOURCE_PLL2 RCC_CCIPR2_LTDCSEL

PLL2 “R” (pll2_r_ck) selected

Peripheral USB HS PHY clock source selection

group RCC_LL_EC_USBPHY_CLKSOURCE

Defines

LL_RCC_USBHSPHYCLKSOURCE_HSE 0U

HSE clock selected as USB HS PHY clock

LL_RCC_USBHSPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_OTGHSSEL_1

HSE clock divided by 2 selected as USB HS PHY clock

LL_RCC_USBHSPHYCLKSOURCE_PLL1 RCC_CCIPR2_OTGHSSEL_0

PLL1 divider P selected as USB HS PHY clock

LL_RCC_USBHSPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_OTGHSSEL_1 | RCC_CCIPR2_OTGHSSEL_0)

PLL1 divider P divided by 2 selected as USB HS PHY clock

Peripheral I2Cx get clock source

group RCC_LL_EC_I2C

Defines

LL_RCC_I2C1_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos))


I2C1 Clock source selection

LL_RCC_I2C2_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos))


I2C2 Clock source selection

LL_RCC_I2C3_CLKSOURCE (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \

(RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos))


I2C3 Clock source selection

LL_RCC_I2C4_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \

(RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos))


I2C4 Clock source selection

LL_RCC_I2C5_CLKSOURCE (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos))


I2C1 Clock source selection

LL_RCC_I2C6_CLKSOURCE (( RCC_OFFSET_CCIPR2

<< 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \

(RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos))


I2C1 Clock source selection

Peripheral LPTIMx get clock source

group RCC_LL_EC_LPTIM

Defines

LL_RCC_LPTIM1_CLKSOURCE (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos))


LPTIM1 Clock source selection

LL_RCC_LPTIM2_CLKSOURCE (( RCC_OFFSET_CCIPR1

<< 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \

(RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos))


LPTIM2 Clock source selection

LL_RCC_LPTIM34_CLKSOURCE (( RCC_OFFSET_CCIPR3

<< 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \

(RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos))


LPTIM3 and LPTIM4 Clock source selection

Peripheral SAIx get clock source

group RCC_LL_EC_SAI

Defines

LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL

SAI1 Clock source selection

LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL

SAI2 Clock source selection

Peripheral SDMMC get kernel clock source

group RCC_LL_EC_SDMMC_KERNEL

Defines

LL_RCC_SDMMC_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL

SDMMC1/2 Kernel Clock source selection

Peripheral SDMMC get clock source

group RCC_LL_EC_SDMMC1_2

Defines

LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_ICLKSEL

SDMMC1/2 Clock source selection

Peripheral RNG get clock source

group RCC_LL_EC_RNG

Defines

LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL

RNG Clock source selection

Peripheral USB get clock source

group RCC_LL_EC_USB

Defines

LL_RCC_USB_CLKSOURCE RCC_CCIPR1_ICLKSEL

USB Clock source selection

Peripheral ADCDAC get clock source

group RCC_LL_EC_ADCDAC

Defines

LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR3_ADCDACSEL

ADCDACs Clock source selection

Peripheral MDF1 get clock source

group RCC_LL_EC_MDF1

Defines

LL_RCC_MDF1_CLKSOURCE RCC_CCIPR2_MDF1SEL /* MDF1 Clock source selection */

Peripheral DAC1 get clock source

group RCC_LL_EC_DAC1

Defines

LL_RCC_DAC1_CLKSOURCE RCC_CCIPR3_DAC1SEL /* DAC1 Clock source selection */

Peripheral ADF1 get clock source

group RCC_LL_EC_ADF1

Defines

LL_RCC_ADF1_CLKSOURCE RCC_CCIPR3_ADF1SEL

ADF1 Clock source selection

Peripheral FDCAN get kernel clock source

group RCC_LL_EC_FDCAN

Defines

LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL

FDCAN Kernel Clock source selection

Peripheral OCTOSPI get clock source

group RCC_LL_EC_OCTOSPI

Defines

LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OCTOSPISEL

OctoSPI Clock source selection

Peripheral HSPI get clock source

group RCC_LL_EC_HSPI

Defines

LL_RCC_HSPI_CLKSOURCE RCC_CCIPR2_HSPISEL

HSPI Clock source selection

Peripheral SAES get clock source

group RCC_LL_EC_SAES

Defines

LL_RCC_SAES_CLKSOURCE RCC_CCIPR2_SAESSEL

SAES Clock source selection

Peripheral DSI get clock source

group RCC_LL_EC_DSI

Defines

LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSIHOSTSEL

DSI Clock source selection

Peripheral LTDC get clock source

group RCC_LL_EC_LTDC

Defines

LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_LTDCSEL

LTDC Clock source selection

Peripheral USB HS PHY get clock source

group RCC_LL_EC_USBPHY

Defines

LL_RCC_USBHSPHY_CLKSOURCE RCC_CCIPR2_OTGHSSEL

USB HS PHY Clock source selection

PLL1 entry clock source

group RCC_LL_EC_PLL1SOURCE

Defines

LL_RCC_PLL1SOURCE_NONE 0x00000000U

No clock selected as main PLL1 entry clock source

LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0

MSIS clock selected as main PLL1 entry clock source

LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1

HSI clock selected as main PLL1 entry clock source

LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1)

HSE clock selected as main PLL1 entry clock source

PLL1 Clock Output

group RCC_LL_EC_PLL1_OUTPUT

Defines

LL_RCC_PLL1_OUTPUT_P RCC_PLL1CFGR_PLL1PEN

pll1_p_ck output enabled

LL_RCC_PLL1_OUTPUT_Q RCC_PLL1CFGR_PLL1QEN

pll1_q_ck output enabled

LL_RCC_PLL1_OUTPUT_R RCC_PLL1CFGR_PLL1REN

pll1_r_ck output enabled

All PLLs input ranges

group RCC_LL_EC_PLLINPUTRANGE

Defines

LL_RCC_PLLINPUTRANGE_4_8 0x00000000U

VCO input range: 4 to 8 MHz

LL_RCC_PLLINPUTRANGE_8_16 RCC_PLL1CFGR_PLL1RGE

VCO input range: 8 to 16 MHz

PLL2 entry clock source

group RCC_LL_EC_PLL2SOURCE

Defines

LL_RCC_PLL2SOURCE_NONE 0x00000000U

No clock selected as main PLL2 entry clock source

LL_RCC_PLL2SOURCE_MSIS RCC_PLL2CFGR_PLL2SRC_0

MSIS clock selected as main PLL2 entry clock source

LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_1

HSI clock selected as main PLL2 entry clock source

LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1)

HSE clock selected as main PLL2 entry clock source

PLL2 Clock Output

group RCC_LL_EC_PLL2_OUTPUT

Defines

LL_RCC_PLL2_OUTPUT_P RCC_PLL2CFGR_PLL2PEN

pll2_p_ck output enabled

LL_RCC_PLL2_OUTPUT_Q RCC_PLL2CFGR_PLL2QEN

pll2_q_ck output enabled

LL_RCC_PLL2_OUTPUT_R RCC_PLL2CFGR_PLL2REN

pll2_r_ck output enabled

PLL3 entry clock source

group RCC_LL_EC_PLL3SOURCE

Defines

LL_RCC_PLL3SOURCE_NONE 0x00000000U

No clock selected as main PLL3 entry clock source

LL_RCC_PLL3SOURCE_MSIS RCC_PLL3CFGR_PLL3SRC_0

MSIS clock selected as main PLL3 entry clock source

LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_1

HSI clock selected as main PLL3 entry clock source

LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1)

HSE clock selected as main PLL3 entry clock source

PLL3 Clock Output

group RCC_LL_EC_PLL3_OUTPUT

Defines

LL_RCC_PLL3_OUTPUT_P RCC_PLL3CFGR_PLL3PEN

pll3_p_ck output enabled

LL_RCC_PLL3_OUTPUT_Q RCC_PLL3CFGR_PLL3QEN

pll3_q_ck output enabled

LL_RCC_PLL3_OUTPUT_R RCC_PLL3CFGR_PLL3REN

pll3_r_ck output enabled

MSI clock range selection

group RCC_LL_EC_MSIRANGESEL

Defines

LL_RCC_MSIRANGESEL_STANDBY 0U

MSI Range is provided by MSISRANGE

LL_RCC_MSIRANGESEL_RUN 1U

MSI Range is provided by MSISRANGE

RCC Flags

group RCC_LL_FLAGS

Defines

LL_RCC_IT_LSIRDY RCC_CIFR_LSIRDYF

LSI Ready interrupt flag

LL_RCC_IT_LSERDY RCC_CIFR_LSERDYF

LSE Ready interrupt flag

LL_RCC_IT_MSIRDY RCC_CIFR_MSISRDYF

MSI Ready interrupt flag

LL_RCC_IT_HSIRDY RCC_CIFR_HSIRDYF

HSI16 Ready interrupt flag

LL_RCC_IT_HSERDY RCC_CIFR_HSERDYF

HSE Ready interrupt flag

LL_RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF

HSI48 Ready interrupt flag

LL_RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF

PLL1 Ready interrupt flag

LL_RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF

PLL2 Ready interrupt flag

LL_RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF

PLL3 Ready interrupt flag

LL_RCC_IT_HSECSS RCC_CIFR_CSSF

Clock Security System interrupt flag

LL_RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF

MSIK Ready interrupt flag

LL_RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF

SHSI Ready interrupt flag

Security Services

group RCC_LL_EC_Security_Services

Note

Only available when system implements security (TZEN=1).

Defines

LL_RCC_ALL_NSEC 0U

No security on RCC resources (default)

LL_RCC_ALL_SEC RCC_SECURE_MASK

Security on all RCC resources

LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC

HSI clock configuration security

LL_RCC_HSI_NSEC 0U

HSI clock configuration secure/non-secure access

LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC

HSE clock configuration security

LL_RCC_HSE_NSEC 0U

HSE clock configuration secure/non-secure access

LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC

MSI clock configuration security

LL_RCC_MSI_NSEC 0U

MSI clock configuration secure/non-secure access

LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC

LSE clock configuration security

LL_RCC_LSE_NSEC 0U

LSE clock configuration secure/non-secure access

LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC

LSI clock configuration security

LL_RCC_LSI_NSEC 0U

LSI clock configuration secure/non-secure access

LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC

SYSCLK clock; STOPWUCK and MCO output configuration security

LL_RCC_SYSCLK_NSEC 0U

SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access

LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC

AHBx/APBx prescaler configuration security

LL_RCC_PRESCALERS_NSEC 0U

AHBx/APBx prescaler configuration secure/non-secure access

LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC

PLL1 clock configuration security

LL_RCC_PLL1_NSEC 0U

main PLL1 clock configuration secure/non-secure access

LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC

PLL2 clock configuration security

LL_RCC_PLL2_NSEC 0U

main PLL2 clock configuration secure/non-secure access

LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC

PLL3 clock configuration security

LL_RCC_PLL3_NSEC 0U

main PLL3 clock configuration secure/non-secure access

LL_RCC_ICLK_SEC RCC_SECCFGR_ICLKSEC

ICLK clock source selection security

LL_RCC_ICLK_NSEC 0U

ICLK clock source selection secure/non-secure access

LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC

HSI48 clock configuration security

LL_RCC_HSI48_NSEC 0U

HSI48 clock configuration secure/non-secure access

LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC

Remove reset flag security

LL_RCC_RESET_FLAGS_NSEC 0U