LL SPI Constants

Get Flags Defines

group SPI_LL_EC_GET_FLAG

Flags defines which can be used with LL_SPI_ReadReg function.

Defines

LL_SPI_FLAG_RXP (SPI_SR_RXP)
LL_SPI_FLAG_TXP (SPI_SR_TXP)
LL_SPI_FLAG_DXP (SPI_SR_DXP)
LL_SPI_FLAG_EOT (SPI_SR_EOT)
LL_SPI_FLAG_TXTF (SPI_SR_TXTF)
LL_SPI_FLAG_UDR (SPI_SR_UDR)
LL_SPI_FLAG_CRCE (SPI_SR_CRCE)
LL_SPI_FLAG_MODF (SPI_SR_MODF)
LL_SPI_FLAG_OVR (SPI_SR_OVR)
LL_SPI_FLAG_TIFRE (SPI_SR_TIFRE)
LL_SPI_FLAG_SUSP (SPI_SR_SUSP)
LL_SPI_FLAG_TXC (SPI_SR_TXC)
LL_SPI_FLAG_RXWNE (SPI_SR_RXWNE)

IT Defines

group SPI_LL_EC_IT

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Defines

LL_SPI_IT_RXP (SPI_IER_RXPIE)
LL_SPI_IT_TXP (SPI_IER_TXPIE)
LL_SPI_IT_DXP (SPI_IER_DXPIE)
LL_SPI_IT_EOT (SPI_IER_EOTIE)
LL_SPI_IT_TXTF (SPI_IER_TXTFIE)
LL_SPI_IT_UDR (SPI_IER_UDRIE)
LL_SPI_IT_OVR (SPI_IER_OVRIE)
LL_SPI_IT_CRCE (SPI_IER_CRCEIE)
LL_SPI_IT_TIFRE (SPI_IER_TIFREIE)
LL_SPI_IT_MODF (SPI_IER_MODFIE)

Mode

group SPI_LL_EC_MODE

Defines

LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
LL_SPI_MODE_SLAVE (0x00000000UL)

SS Level

group SPI_LL_EC_SS_LEVEL

Defines

LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
LL_SPI_SS_LEVEL_LOW (0x00000000UL)

Master Slave Select Idleness

group SPI_LL_EC_NSS_MSSI

Defines

LL_SPI_MSSI_DELAY_0_CYCLE (0x00000000UL)

No extra delay

LL_SPI_MSSI_DELAY_1_CYCLE (SPI_CFG2_MSSI_0)

1 clock cycle period delay added

LL_SPI_MSSI_DELAY_2_CYCLE (SPI_CFG2_MSSI_1)

2 clock cycle period delay added

LL_SPI_MSSI_DELAY_3_CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)

3 clock cycle period delay added

LL_SPI_MSSI_DELAY_4_CYCLE (SPI_CFG2_MSSI_2)

4 clock cycle period delay added

LL_SPI_MSSI_DELAY_5_CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)

5 clock cycle period delay added

LL_SPI_MSSI_DELAY_6_CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)

6 clock cycle period delay added

LL_SPI_MSSI_DELAY_7_CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

7 clock cycle period delay added

LL_SPI_MSSI_DELAY_8_CYCLE (SPI_CFG2_MSSI_3)

8 clock cycle period delay added

LL_SPI_MSSI_DELAY_9_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)

9 clock cycle period delay added

LL_SPI_MSSI_DELAY_10_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)

10 clock cycle period delay added

LL_SPI_MSSI_DELAY_11_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

11 clock cycle period delay added

LL_SPI_MSSI_DELAY_12_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)

12 clock cycle period delay added

LL_SPI_MSSI_DELAY_13_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)

13 clock cycle period delay added

LL_SPI_MSSI_DELAY_14_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)

14 clock cycle period delay added

LL_SPI_MSSI_DELAY_15_CYCLE

(SPI_CFG2_MSSI_3\

| SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)


15 clock cycle period delay added

Master Inter-Data Idleness

group SPI_LL_EC_ID_IDLENESS

Defines

LL_SPI_MIDI_DELAY_0_CYCLE (0x00000000UL)

No delay

LL_SPI_MIDI_DELAY_1_CYCLE (SPI_CFG2_MIDI_0)

1 clock cycle period delay

LL_SPI_MIDI_DELAY_2_CYCLE (SPI_CFG2_MIDI_1)

2 clock cycles period delay

LL_SPI_MIDI_DELAY_3_CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)

3 clock cycles period delay

LL_SPI_MIDI_DELAY_4_CYCLE (SPI_CFG2_MIDI_2)

4 clock cycles period delay

LL_SPI_MIDI_DELAY_5_CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)

5 clock cycles period delay

LL_SPI_MIDI_DELAY_6_CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)

6 clock cycles period delay

LL_SPI_MIDI_DELAY_7_CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

7 clock cycles period delay

LL_SPI_MIDI_DELAY_8_CYCLE (SPI_CFG2_MIDI_3)

8 clock cycles period delay

LL_SPI_MIDI_DELAY_9_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)

9 clock cycles period delay

LL_SPI_MIDI_DELAY_10_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)

10 clock cycles period delay

LL_SPI_MIDI_DELAY_11_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

11 clock cycles period delay

LL_SPI_MIDI_DELAY_12_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)

12 clock cycles period delay

LL_SPI_MIDI_DELAY_13_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)

13 clock cycles period delay

LL_SPI_MIDI_DELAY_14_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)

14 clock cycles period delay

LL_SPI_MIDI_DELAY_15_CYCLE

(SPI_CFG2_MIDI_3\

| SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)


15 clock cycles period delay

TXCRC Init All

group SPI_LL_EC_TXCRCINIT_ALL

Defines

LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO (0x00000000UL)

CRC TX Initialization patterns configured to zero

LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE (SPI_CR1_TCRCINI)

CRC TX Initialization patterns configured to one

RXCRC Init All

group SPI_LL_EC_RXCRCINIT_ALL

Defines

LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO (0x00000000UL)

CRC RX Initialization patterns configured to zero

LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE (SPI_CR1_RCRCINI)

CRC RX Initialization patterns configured to one

UDR Config Register

group SPI_LL_EC_UDR_CONFIG_REGISTER

Defines

LL_SPI_UNDERRUN_CONFIG_REGISTER_PATTERN (0x00000000UL)
LL_SPI_UNDERRUN_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)

Slave repeats lastly received data from master

Protocol

group SPI_LL_EC_PROTOCOL

Defines

LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)

MOTOROLA protocol is used (most common protocol)

LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)

TI protocol is used

Phase

group SPI_LL_EC_PHASE

Defines

LL_SPI_CLOCK_PHASE_1_EDGE (0x00000000UL)

The first clock transition is the first data capture edge

LL_SPI_CLOCK_PHASE_2_EDGE (SPI_CFG2_CPHA)

The second clock transition is the first data capture edge

Polarity

group SPI_LL_EC_POLARITY

Defines

LL_SPI_CLOCK_POLARITY_LOW (0x00000000UL)

SCK signal is at 0 when idle

LL_SPI_CLOCK_POLARITY_HIGH (SPI_CFG2_CPOL)

SCK signal is at 1 when idle

NSS Polarity

group SPI_LL_EC_NSS_POLARITY

Defines

LL_SPI_NSS_POLARITY_LOW (0x00000000UL)

Low level is active for slave select signal

LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)

High level is active for slave select signal

Baud Rate Prescaler

group SPI_LL_EC_BAUDRATEPRESCALER

Defines

LL_SPI_BAUD_RATE_PRESCALER_BYPASS (SPI_CFG1_BPASS)

Bypass from RCC in Master mode

LL_SPI_BAUD_RATE_PRESCALER_2 (0x00000000UL)

SPI master clock/2

LL_SPI_BAUD_RATE_PRESCALER_4 (SPI_CFG1_MBR_0)

SPI master clock/4

LL_SPI_BAUD_RATE_PRESCALER_8 (SPI_CFG1_MBR_1)

SPI master clock/8

LL_SPI_BAUD_RATE_PRESCALER_16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

SPI master clock/16

LL_SPI_BAUD_RATE_PRESCALER_32 (SPI_CFG1_MBR_2)

SPI master clock/32

LL_SPI_BAUD_RATE_PRESCALER_64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)

SPI master clock/64

LL_SPI_BAUD_RATE_PRESCALER_128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)

SPI master clock/128

LL_SPI_BAUD_RATE_PRESCALER_256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

SPI master clock/256

Bit Order

group SPI_LL_EC_BIT_ORDER

Defines

LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)

LSB transmitted first

LL_SPI_MSB_FIRST (0x00000000UL)

MSB transmitted first

Transfer Direction

group SPI_LL_EC_TRANSFER_DIRECTION

Direction defines.

Note

LL_SPI_SetHalfDuplexDirection must be used to select the transfer direction in half duplex

Defines

LL_SPI_FULL_DUPLEX (0x00000000UL)

Full-duplex communication

LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)

Simplex communication mode: Transmit only

LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)

Simplex communication mode: Receive only

LL_SPI_HALF_DUPLEX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)

Half-duplex communication

Half Duplex Direction

group SPI_LL_EC_HALF_DUPLEX_DIRECTION

Defines

LL_SPI_HALF_DUPLEX_RX (0x00000000UL)

Half-duplex in reception mode

LL_SPI_HALF_DUPLEX_TX (SPI_CR1_HDDIR)

Half-duplex in transmission mode

Data Width

group SPI_LL_EC_DATAWIDTH

Defines

LL_SPI_DATA_WIDTH_4_BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_5_BIT (SPI_CFG1_DSIZE_2)
LL_SPI_DATA_WIDTH_6_BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_7_BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_8_BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_9_BIT (SPI_CFG1_DSIZE_3)
LL_SPI_DATA_WIDTH_10_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_11_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_12_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_13_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
LL_SPI_DATA_WIDTH_14_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_15_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_16_BIT

(SPI_CFG1_DSIZE_3\

| SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)


LL_SPI_DATA_WIDTH_17_BIT (SPI_CFG1_DSIZE_4)
LL_SPI_DATA_WIDTH_18_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_19_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_20_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_21_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
LL_SPI_DATA_WIDTH_22_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_23_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_24_BIT

(SPI_CFG1_DSIZE_4\

| SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)


LL_SPI_DATA_WIDTH_25_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
LL_SPI_DATA_WIDTH_26_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
LL_SPI_DATA_WIDTH_27_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
LL_SPI_DATA_WIDTH_28_BIT

(SPI_CFG1_DSIZE_4\

| SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)


LL_SPI_DATA_WIDTH_29_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
LL_SPI_DATA_WIDTH_30_BIT

(SPI_CFG1_DSIZE_4\

| SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)


LL_SPI_DATA_WIDTH_31_BIT

(SPI_CFG1_DSIZE_4\

| SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)


LL_SPI_DATA_WIDTH_32_BIT

(SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\

| SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)


FIFO Threshold

group SPI_LL_EC_FIFO_TH

Defines

LL_SPI_FIFO_THRESHOLD_1_DATA (0x00000000UL)
LL_SPI_FIFO_THRESHOLD_2_DATA (SPI_CFG1_FTHLV_0)
LL_SPI_FIFO_THRESHOLD_3_DATA (SPI_CFG1_FTHLV_1)
LL_SPI_FIFO_THRESHOLD_4_DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
LL_SPI_FIFO_THRESHOLD_5_DATA (SPI_CFG1_FTHLV_2)
LL_SPI_FIFO_THRESHOLD_6_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
LL_SPI_FIFO_THRESHOLD_7_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
LL_SPI_FIFO_THRESHOLD_8_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
LL_SPI_FIFO_THRESHOLD_9_DATA (SPI_CFG1_FTHLV_3)
LL_SPI_FIFO_THRESHOLD_10_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
LL_SPI_FIFO_THRESHOLD_11_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
LL_SPI_FIFO_THRESHOLD_12_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
LL_SPI_FIFO_THRESHOLD_13_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
LL_SPI_FIFO_THRESHOLD_14_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
LL_SPI_FIFO_THRESHOLD_15_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
LL_SPI_FIFO_THRESHOLD_16_DATA

(SPI_CFG1_FTHLV_3\

| SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)


CRC

group SPI_LL_EC_CRC

Defines

LL_SPI_CRC_LENGTH_4_BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_5_BIT (SPI_CFG1_CRCSIZE_2)
LL_SPI_CRC_LENGTH_6_BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_7_BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_8_BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_9_BIT (SPI_CFG1_CRCSIZE_3)
LL_SPI_CRC_LENGTH_10_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_11_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_12_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_13_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
LL_SPI_CRC_LENGTH_14_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_15_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_16_BIT

(SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 \

| SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)


LL_SPI_CRC_LENGTH_17_BIT (SPI_CFG1_CRCSIZE_4)
LL_SPI_CRC_LENGTH_18_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_19_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_20_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_21_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
LL_SPI_CRC_LENGTH_22_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_23_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_24_BIT

(SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 \

| SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)


LL_SPI_CRC_LENGTH_25_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
LL_SPI_CRC_LENGTH_26_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
LL_SPI_CRC_LENGTH_27_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
LL_SPI_CRC_LENGTH_28_BIT

(SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \

| SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)


LL_SPI_CRC_LENGTH_29_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
LL_SPI_CRC_LENGTH_30_BIT

(SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \

| SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)


LL_SPI_CRC_LENGTH_31_BIT

(SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \

| SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)


LL_SPI_CRC_LENGTH_32_BIT

(SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \

| SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)


NSS Mode

group SPI_LL_EC_NSS_MODE

Defines

LL_SPI_NSS_SOFT (SPI_CFG2_SSM)

In this configuration the Slave select is driven internally. The external slave select pin is free for other application uses.

LL_SPI_NSS_HARD_INPUT (0x00000000UL)

In Slave mode, the slave select pin works as a standard chip select input and the slave is selected while the slave select line is at its active level. In Master mode, this configuration allows multi-master capability. If the slave select pin is pulled into an active level in this mode, the SPI enters Master mode fault state and the SPI device is automatically reconfigured in Slave mode (MASTER = 0)

LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)

This configuration is only used when the MCU is set as master (multi-master not allowed). The slave select pin active level is managed by the hardware. The functionality is tied to CSTART and EOT control.

RxFIFO Packing LeVel

group SPI_LL_EC_RX_FIFO

Defines

LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

Autonomous Trigger selection

group SPI_LL_EC_AUTOCR_TRIGSEL

SPI Autonomous Trigger selection.

Defines

LL_SPI_TRIG_GRP1 (0x10000000U)

Trigger Group for SPI1 and SPI2

LL_SPI_TRIG_GRP2 (0x20000000U)

Trigger Group for SPI3

LL_SPI_TRIG_GRP1_GPDMA1_CH0_TC (uint32_t)( LL_SPI_TRIG_GRP1 | (0x00000000U))

< HW Trigger signal is GPDMA1_CH0_TC HW Trigger signal is GPDMA1_CH1_TC

LL_SPI_TRIG_GRP1_GPDMA1_CH1_TC (uint32_t)( LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is GPDMA1_CH2_TC

LL_SPI_TRIG_GRP1_GPDMA1_CH2_TC (uint32_t)( LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is GPDMA1_CH3_TC

LL_SPI_TRIG_GRP1_GPDMA1_CH3_TC (uint32_t)( LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI4

LL_SPI_TRIG_GRP1_EXTI4 (uint32_t)( LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI9

LL_SPI_TRIG_GRP1_EXTI9 (uint32_t)( LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM1_CH1

LL_SPI_TRIG_GRP1_LPTIM1_CH1 (uint32_t)( LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM2_CH1

LL_SPI_TRIG_GRP1_LPTIM2_CH1 (uint32_t)( LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP1_OUT

LL_SPI_TRIG_GRP1_COMP1_OUT (uint32_t)( LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP2_OUT

LL_SPI_TRIG_GRP1_COMP2_OUT (uint32_t)( LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_ALRA_TRG

LL_SPI_TRIG_GRP1_RTC_ALRA_TRG (uint32_t)( LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_WUT_TRG

LL_SPI_TRIG_GRP1_RTC_WUT_TRG (uint32_t)( LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPDMA1_CH0_TC

LL_SPI_TRIG_GRP2_LPDMA1_CH0_TC (uint32_t)( LL_SPI_TRIG_GRP2 | (0x00000000U))

HW Trigger signal is LPDMA1_CH1_TC

LL_SPI_TRIG_GRP2_LPDMA1_CH1_TC (uint32_t)( LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPDMA1_CH2_TC

LL_SPI_TRIG_GRP2_LPDMA1_CH2_TC (uint32_t)( LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPDMA1_CH3_TC

LL_SPI_TRIG_GRP2_LPDMA1_CH3_TC (uint32_t)( LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI4

LL_SPI_TRIG_GRP2_EXTI4 (uint32_t)( LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is EXTI8

LL_SPI_TRIG_GRP2_EXTI8 (uint32_t)( LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM1_CH1

LL_SPI_TRIG_GRP2_LPTIM1_CH1 (uint32_t)( LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is LPTIM3_CH1

LL_SPI_TRIG_GRP2_LPTIM3_CH1 (uint32_t)( LL_SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP1_OUT

LL_SPI_TRIG_GRP2_COMP1_OUT (uint32_t)( LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is COMP2_OUT

LL_SPI_TRIG_GRP2_COMP2_OUT (uint32_t)( LL_SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_ALRA_TRG

LL_SPI_TRIG_GRP2_RTC_ALRA_TRG (uint32_t)( LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))

HW Trigger signal is RTC_WUT_TRG

LL_SPI_TRIG_GRP2_RTC_WUT_TRG (uint32_t)( LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))

Autonomous Trigger Polarity

group SPI_LL_EC_AUTOCR_TRIGPOL

SPI Autonomous Trigger Polarity.

Defines

LL_SPI_AM_TRIG_RISING 0x00000000U
LL_SPI_AM_TRIG_FALLING SPI_AUTOCR_TRIGPOL

Master Receiver Automatic Suspension

group SPI_LL_EC_CR1_MASRX

SPI Master Receiver Automatic Suspension.

Defines

LL_SPI_MASTER_RX_AUTO_SUSPEND_DISABLE 0x00000000U
LL_SPI_MASTER_RX_AUTO_SUSPEND_ENABLE SPI_CR1_MASRX

Keep IO State

group SPI_LL_EC_CFG2_AFCNTR

SPI Keep IO State.

Defines

LL_SPI_MASTER_KEEP_IO_STATE_DISABLE 0x00000000U
LL_SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR

NSS Pulse Mode

group SPI_LL_EC_NSSP_Mode

SPI NSS Pulse Mode.

Defines

LL_SPI_NSS_PULSE_DISABLE (0x00000000UL)

Slave select IO pin is kept at active level till data transfer is \ completed, it becomes inactive with EOT flag

LL_SPI_NSS_PULSE_ENABLE (SPI_CFG2_SSOM)

SPI data frames are interleaved with slave select IO pin non active \ pulses when MIDI[3:0]>1

Swap MISO and MOSI pins

group SPI_LL_EC_MOSI_MISO_SWAP

SPI Swap MISO and MOSI pins.

Defines

LL_SPI_MOSI_MISO_SWAP_DISABLE (0x00000000UL)
LL_SPI_MOSI_MISO_SWAP_ENABLE (SPI_CFG2_IOSWP)

Ready pin input/output polarity

group SPI_LL_EC_RDY_PIN_POLARITY

SPI Ready pin input/output polarity.

Defines

LL_SPI_READY_PIN_POLARITY_HIGH (0x00000000UL)
LL_SPI_READY_PIN_POLARITY_LOW (SPI_CFG2_RDIOP)

Ready Pin Input Master Management

group SPI_LL_EC_RDY_PIN_MASTER_MANAGEMENT

SPI Ready Pin Input Master Management.

Defines

LL_SPI_READY_PIN_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL)
LL_SPI_READY_PIN_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIOM