LL SYSCFG Constants

LL SYSCFG Constants

group SYSCFG_LL_Exported_Constants

Defines

LL_SYSCFG_CCELL_VDDIO SYSCFG_CCCSR_EN1

Compensation cell selection for VDDIO

LL_SYSCFG_CCELL_VDDIO2 SYSCFG_CCCSR_EN2

Compensation cell selection for VDDIO2

LL_SYSCFG_CCELL_HSPIIO SYSCFG_CCCSR_EN3

Compensation cell selection for HSPIIO

LL_SYSCFG_CCELL_ALL (SYSCFG_CCCSR_EN1 | SYSCFG_CCCSR_EN2 | SYSCFG_CCCSR_EN3)

SYSCFG fast mode plus

group SYSCFG_LL_EC_FASTMODEPLUS

Defines

LL_SYSCFG_DRIVE_PB6 SYSCFG_CFGR1_PB6_FMP

Enables the Fast Mode Plus on PB6

LL_SYSCFG_DRIVE_PB7 SYSCFG_CFGR1_PB7_FMP

Enables the Fast Mode Plus on PB7

LL_SYSCFG_DRIVE_PB8 SYSCFG_CFGR1_PB8_FMP

Enables the Fast Mode Plus on PB8

LL_SYSCFG_DRIVE_PB9 SYSCFG_CFGR1_PB9_FMP

Enables the Fast Mode Plus on PB9

LL_SYSCFG_DRIVE_ALL

(SYSCFG_CFGR1_PB6_FMP | SYSCFG_CFGR1_PB7_FMP | \

SYSCFG_CFGR1_PB8_FMP | SYSCFG_CFGR1_PB9_FMP)


Enables all Fast mode plus driving capability

SYSCFG floating point unit interrupts

group SYSCFG_LL_EC_FLOATING_POINT_UNIT_INTERRUPTs

Defines

LL_SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0

Invalid operation interrupt

LL_SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1

Divide-by-zero interrupt

LL_SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2

underflow interrupt

LL_SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3

Overflow interrupt

LL_SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4

Input abnormal interrupt

LL_SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5

Inexact interrupt

LL_SYSCFG_IT_FPU_ALL

(SYSCFG_FPUIMR_FPU_IE_0 | SYSCFG_FPUIMR_FPU_IE_1 | SYSCFG_FPUIMR_FPU_IE_2 | \

SYSCFG_FPUIMR_FPU_IE_3 | SYSCFG_FPUIMR_FPU_IE_4 | SYSCFG_FPUIMR_FPU_IE_5)


All floating point unit interrupts interrupt

SYSCFG TIMER BREAK

group SYSCFG_LL_EC_TIMBREAK

Defines

LL_SYSCFG_FLASH_ECC_DOUBLE_ERROR SYSCFG_CFGR2_ECCL

Enables and locks the FLASH ECC error signal with Break Input of TIM1/8/15/16/17

LL_SYSCFG_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

LL_SYSCFG_SRAM_ECC_DOUBLE_ERROR SYSCFG_CFGR2_SPL

Enables and locks the SRAM ECC double error signal with Break Input of TIM1/8/15/16/17

LL_SYSCFG_LOCKUP_OUT SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM33 with Break Input of TIM1/15/16/17

LL_SYSCFG_TIM_BREAK_INPUTS_ALL

(SYSCFG_CFGR2_ECCL | SYSCFG_CFGR2_PVDL | \

SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_CLL)


Enables and locks the all with Break Input of TIM1/15/16/17

SYSCFG USB PHY Reference Clock frequency

group SYSCFG_USB_PHY_RefenceClockFrequency

Defines

LL_SYSCFG_USBHSPHY_16MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1)

Clock frequency 16 MHz

LL_SYSCFG_USBHSPHY_19_2MHZ SYSCFG_OTGHSPHYCR_CLKSEL_3

Clock frequency 19.2 MHz

LL_SYSCFG_USBHSPHY_20MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3)

Clock frequency 20 MHz

LL_SYSCFG_USBHSPHY_24MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3)

Clock frequency 24 MHz

LL_SYSCFG_USBHSPHY_26MHZ

(SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | \

SYSCFG_OTGHSPHYCR_CLKSEL_3)


Clock frequency 26 MHz

LL_SYSCFG_USBHSPHY_32MHZ

(SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | \

SYSCFG_OTGHSPHYCR_CLKSEL_3)


Clock frequency 32 MHz

SYSCFG USB HS PHY transmitter preemphasis current

group SYSCFG_USBHSPHY_TRANSMITTER_PREEMPHASIS_CURRENT

Defines

LL_SYSCFG_SRC_CURRENT_NO 0U

Transmitter preemphasis disabled

LL_SYSCFG_SRC_CURRENT_1 SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0

Transmitter preemphasis circuit sources 1x

LL_SYSCFG_SRC_CURRENT_2 SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1

Transmitter preemphasis circuit sources 2x

LL_SYSCFG_SRC_CURRENT_3 SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE

Transmitter preemphasis circuit sources 3x

SYSCFG squelch threshold adjustment

group SYSCFG_SQUELCH_THRESHOLD_ADJUSTMENT

Defines

LL_SYSCFG_SQUELCH_ADJUST_0_PERCENT

(SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 \

| SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1)


0% (default value)

LL_SYSCFG_SQUELCH_ADJUST_PLUS_15_PERCENT 0U

+15% (recommended value)

SYSCFG disconnect threshold adjustment

group SYSCFG_DISCONNECT_THRESHOLD_ADJUSTMENT

Defines

LL_SYSCFG_DIS_ADJUST_0_PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0

Adjusts the voltage level for the threshold used to detect a disconnect event at the host by 0% (default value)

LL_SYSCFG_DIS_ADJUST_PLUS_5_9_PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1

Adjusts the voltage level for the threshold used to detect a disconnect event at the host by +5.9% (recommended value)

Secure attributes

group SYSCFG_LL_EC_SECURE_ATTRIBUTES

Note

Only available when syscfg implements security (TZEN=1)

Defines

LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC

SYSCFG clock configuration secure-only access

LL_SYSCFG_CLOCK_NSEC 0U

SYSCFG clock configuration secure/non-secure access

LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC

Class B configuration secure-only access

LL_SYSCFG_CLASSB_NSEC 0U

Class B configuration secure/non-secure access

LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC

FPU configuration secure-only access

LL_SYSCFG_FPU_NSEC 0U

FPU configuration secure/non-secure access