STM32CubeMX2 Configuration Limitations

Contents

  • This page lists the Configuration Limitations when using STM32C5 SW Packs with STM32CubeMX2 version V1.0.0.

  • These limitations will be addressed in a future release, planned for early Q3 2026.

General

  • No .ioc2 files provided for examples using below SW components, as they are not configurable in STM32CubeMX2:

    • Middleware: Filex, Levelx, USBX, Lwip, STFCF, STCryptoLib

    • Utilities: Advanced Trace, EEPROM Emulation, Sequencer, Thread Safe LibC

    • Part drivers: LAN8742, W25N01GVXX, W25QL28J

    • RoT: RoT_provisioning

  • Start from board menu in STM32CubeMX2 does not pre-configure the Part drivers. An example_template_start_from_nucleo is provided to show how to start a project with button, LED and console activated.

  • The Generated Functions Calls feature is available in STM32CubeMX, but not in STM32CubeMX2. To achieve similar functionality in STM32CubeMX2, end-user should manually implement function calls in the user code sections after code generation.

STM32C5xx HAL Drivers Configuration

  • HAL/LL

    • The list of interconnects retrieved from the hardware capabilities may be incorrect because some peripherals are not available on certain STM32 devices. End-user should refer to the device datasheet to verify peripheral availability.

    • IRQ handler aliases for Debug pins configured with EXTI are not generated in the mx_hal_def.h file. To resolve this, manually add the required IRQ handler aliases in the user code section of the mx_hal_def.h file.

    • Resolution of components for STM32C5xx HAL Drivers Pack in integrated development environments other than STM32CubeMX2 is not automatic. End user should manually resolve STM32C5xx HAL Drivers Pack components when using other IDEs.

    • The privilege configuration for STM32C5xx HAL Drivers is not available in STM32CubeMX2.

  • CORTEX

    • Management of CORTEX exception is not disabled by default.

  • DMA

    • Interconnect warnings are not displayed for trigger sources used by DMA. To ensure correct configuration, update the DMA panel and verify the trigger source settings. This issue does not block operation; it is intended to help the end-user should configure the trigger source correctly.

  • ETH

    • When starting project from board (NUCLEO-C5A3ZG), the Ethernet (ETH) pins are not automatically reserved. When activating the ETH peripheral, end-user must manually assign the pins to the correct board pin configurations.

  • LPTIM

    • When using an external asynchronous clock for LPTIM, the LPTIM_IN1 GPIO must be configured in alternate-function mode before calling HAL_LPTIM_SetConfig. Otherwise the timer kernel will not be clocked, and subsequent configuration will not take effect.

  • RTC

    • For STM32C542 and STM32C53x devices, the RTC panel configuration features are incomplete. In the Main features section, under Mode, only Free running BCD calendar is available in the pick list. The options Free running binary and Free running BCD calendar and binary must also be displayed.

  • TIM

    • When selecting STM32C531xx, enabling TIM2 channels, input selection of Channel displays FDCAN1 and FDCAN2 whereas it is not possible. As a consequence, an error when compiling the generated code could happen.

  • Timebase

    • When HAL timebase is set to timer or RTC, user must set manually the peripheral interruption priority to lowest values (15 for instance).

FreeRTOS Configuration