Fault exceptions

Arm® Cortex®-M processors implement an efficient exception model that traps illegal memory accesses and several incorrect program conditions.

The HardFault exception is always enabled and has a fixed priority. It has the highest priority over all other interrupts and exceptions, but lower than a Non-maskable Interrupt (NMI). The HardFault exception is therefore executed in cases where a fault exception is disabled or when a fault occurs during the execution of a fault exception handler.

All other fault exceptions, such as MemManage fault, BusFault, UsageFault, and so on, have a programmable priority. After reset, these exceptions are disabled and can be enabled in the system or application software using the registers in the system control block (SCB).

In the examples, main.c provides a specific HardFault handler. All faults are escalated here by default. This handler updates the example execution status and can be used to track back the origin of the fault.

Note

The line numbers in the code snippet above are indicative. The actual line numbers may vary depending on the example used. This function is usually the last one in the file.