HAL2 Migrator
LL DMA APIs listing for migration ¶
There are a few API changes in the LL layer. This page lists only the modified LL APIs. Others not listed here are unchanged between HAL1 and HAL2.
LL DMA constants ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_DMA_CLLR_OFFSET0 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET1 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET2 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET3 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET4 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET5 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET6 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_CLLR_OFFSET7 |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_LOW_PRIORITY_LOW_WEIGHT |
H5, U5 |
LL_DMA_PRIORITY_LOW_WEIGHT_LOW |
|
LL_DMA_LOW_PRIORITY_MID_WEIGHT |
H5, U5 |
LL_DMA_PRIORITY_LOW_WEIGHT_MID |
|
LL_DMA_LOW_PRIORITY_HIGH_WEIGHT |
H5, U5 |
LL_DMA_PRIORITY_LOW_WEIGHT_HIGH |
|
LL_DMA_HIGH_PRIORITY |
H5, U5 |
LL_DMA_PRIORITY_HIGH |
|
LL_DMA_LSM_FULL_EXECUTION |
H5, U5 |
LL_DMA_LINKEDLIST_EXECUTION_Q |
|
LL_DMA_LSM_1LINK_EXECUTION |
H5, U5 |
LL_DMA_LINKEDLIST_EXECUTION_NODE |
|
LL_DMA_DEST_HALFWORD_PRESERVE |
H5, U5 |
LL_DMA_DEST_HALFWORD_PRESERVED |
|
LL_DMA_DEST_HALFWORD_EXCHANGE |
H5, U5 |
LL_DMA_DEST_HALFWORD_EXCHANGED |
|
LL_DMA_DEST_BYTE_PRESERVE |
H5, U5 |
LL_DMA_DEST_BYTE_PRESERVED |
|
LL_DMA_DEST_BYTE_EXCHANGE |
H5, U5 |
LL_DMA_DEST_BYTE_EXCHANGED |
|
LL_DMA_SRC_BYTE_PRESERVE |
H5, U5 |
LL_DMA_SRC_BYTE_PRESERVED |
|
LL_DMA_SRC_BYTE_EXCHANGE |
H5, U5 |
LL_DMA_SRC_BYTE_EXCHANGED |
|
LL_DMA_DEST_FIXED |
H5, U5 |
LL_DMA_DEST_ADDR_FIXED |
|
LL_DMA_DEST_INCREMENT |
H5, U5 |
LL_DMA_DEST_ADDR_INCREMENTED |
|
LL_DMA_DEST_DATAWIDTH_BYTE |
H5, U5 |
LL_DMA_DEST_DATA_WIDTH_BYTE |
|
LL_DMA_DEST_DATAWIDTH_HALFWORD |
H5, U5 |
LL_DMA_DEST_DATA_WIDTH_HALFWORD |
|
LL_DMA_DEST_DATAWIDTH_WORD |
H5, U5 |
LL_DMA_DEST_DATA_WIDTH_WORD |
|
LL_DMA_DATA_ALIGN_ZEROPADD |
H5, U5 |
LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO |
|
LL_DMA_DATA_ALIGN_SIGNEXTPADD |
H5, U5 |
LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN |
|
LL_DMA_DATA_PACK_UNPACK |
H5, U5 |
LL_DMA_DEST_DATA_PACKED_UNPACKED |
|
LL_DMA_SRC_FIXED |
H5, U5 |
LL_DMA_SRC_ADDR_FIXED |
|
LL_DMA_SRC_INCREMENT |
H5, U5 |
LL_DMA_SRC_ADDR_INCREMENTED |
|
LL_DMA_SRC_DATAWIDTH_BYTE |
H5, U5 |
LL_DMA_SRC_DATA_WIDTH_BYTE |
|
LL_DMA_SRC_DATAWIDTH_HALFWORD |
H5, U5 |
LL_DMA_SRC_DATA_WIDTH_HALFWORD |
|
LL_DMA_SRC_DATAWIDTH_WORD |
H5, U5 |
LL_DMA_SRC_DATA_WIDTH_WORD |
|
LL_DMA_HWREQUEST_SINGLEBURST |
H5, U5 |
LL_DMA_HARDWARE_REQUEST_BURST |
|
LL_DMA_HWREQUEST_BLK |
H5, U5 |
LL_DMA_HARDWARE_REQUEST_BLOCK |
|
LL_DMA_TCEM_BLK_TRANSFER |
H5, U5 |
LL_DMA_DIRECT_XFER_EVENT_BLOCK |
|
LL_DMA_TCEM_RPT_BLK_TRANSFER |
H5, U5 |
LL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK |
|
LL_DMA_TCEM_EACH_LLITEM_TRANSFER |
H5, U5 |
LL_DMA_LINKEDLIST_XFER_EVENT_NODE |
|
LL_DMA_TCEM_LAST_LLITEM_TRANSFER |
H5, U5 |
LL_DMA_LINKEDLIST_XFER_EVENT_Q |
|
LL_DMA_TRIG_POLARITY_MASKED |
H5, U5 |
LL_DMA_TRIGGER_POLARITY_MASKED |
|
LL_DMA_TRIG_POLARITY_RISING |
H5, U5 |
LL_DMA_TRIGGER_POLARITY_RISING |
|
LL_DMA_TRIG_POLARITY_FALLING |
H5, U5 |
LL_DMA_TRIGGER_POLARITY_FALLING |
|
LL_DMA_TRIGM_BLK_TRANSFER |
H5, U5 |
LL_DMA_TRIGGER_BLOCK_TRANSFER |
|
LL_DMA_TRIGM_RPT_BLK_TRANSFER |
H5, U5 |
LL_DMA_TRIGGER_REPEATED_BLOCK_TRANSFER |
|
LL_DMA_TRIGM_LLI_LINK_TRANSFER |
H5, U5 |
LL_DMA_TRIGGER_NODE_TRANSFER |
|
LL_DMA_TRIGM_SINGLBURST_TRANSFER |
H5, U5 |
LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER |
|
LL_DMA_BLKRPT_SRC_ADDR_INCREMENT |
H5, U5 |
LL_DMA_BLOCK_SRC_ADDR_INCREMENTED |
|
LL_DMA_BLKRPT_SRC_ADDR_DECREMENT |
H5, U5 |
LL_DMA_BLOCK_SRC_ADDR_DECREMENTED |
|
LL_DMA_BLKRPT_DEST_ADDR_INCREMENT |
H5, U5 |
LL_DMA_BLOCK_DEST_ADDR_INCREMENTED |
|
LL_DMA_BLKRPT_DEST_ADDR_DECREMENT |
H5, U5 |
LL_DMA_BLOCK_DEST_ADDR_DECREMENTED |
|
LL_DMA_BURST_SRC_ADDR_INCREMENT |
H5, U5 |
LL_DMA_BURST_SRC_ADDR_INCREMENTED |
|
LL_DMA_BURST_SRC_ADDR_DECREMENT |
H5, U5 |
LL_DMA_BURST_SRC_ADDR_DECREMENTED |
|
LL_DMA_BURST_DEST_ADDR_INCREMENT |
H5, U5 |
LL_DMA_BURST_DEST_ADDR_INCREMENTED |
|
LL_DMA_BURST_DEST_ADDR_DECREMENT |
H5, U5 |
LL_DMA_BURST_DEST_ADDR_DECREMENTED |
|
LL_DMA_LPDMA_LINEAR_NODE |
H5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_GPDMA_LINEAR_NODE |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_DMA_GPDMA_2D_NODE |
H5, U5 |
Removed: No logical operations within the LL driver. |
|
LL_GPDMA1_REQUEST_TIM15_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM15_CC1 |
|
LL_GPDMA1_REQUEST_TIM15_TRIG |
H5, U5 |
LL_GPDMA1_REQUEST_TIM15_TRGI |
|
LL_GPDMA1_REQUEST_TIM15_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM15_UPD |
|
LL_GPDMA1_REQUEST_TIM16_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM16_CC1 |
|
LL_GPDMA1_REQUEST_TIM16_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM16_UPD |
|
LL_GPDMA1_REQUEST_TIM17_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM17_CC1 |
|
LL_GPDMA1_REQUEST_TIM17_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM17_UPD |
|
LL_GPDMA1_REQUEST_TIM1_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM1_CC1 |
|
LL_GPDMA1_REQUEST_TIM1_CH2 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM1_CC2 |
|
LL_GPDMA1_REQUEST_TIM1_CH3 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM1_CC3 |
|
LL_GPDMA1_REQUEST_TIM1_CH4 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM1_CC4 |
|
LL_GPDMA1_REQUEST_TIM1_TRIG |
H5, U5 |
LL_GPDMA1_REQUEST_TIM1_TRGI |
|
LL_GPDMA1_REQUEST_TIM1_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM1_UPD |
|
LL_GPDMA1_REQUEST_TIM2_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM2_CC1 |
|
LL_GPDMA1_REQUEST_TIM2_CH2 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM2_CC2 |
|
LL_GPDMA1_REQUEST_TIM2_CH3 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM2_CC3 |
|
LL_GPDMA1_REQUEST_TIM2_CH4 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM2_CC4 |
|
LL_GPDMA1_REQUEST_TIM2_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM2_UPD |
|
LL_GPDMA1_REQUEST_TIM3_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM3_CC1 |
|
LL_GPDMA1_REQUEST_TIM3_CH2 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM3_CC2 |
|
LL_GPDMA1_REQUEST_TIM3_CH3 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM3_CC3 |
|
LL_GPDMA1_REQUEST_TIM3_CH4 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM3_CC4 |
|
LL_GPDMA1_REQUEST_TIM3_TRIG |
H5, U5 |
LL_GPDMA1_REQUEST_TIM3_TRGI |
|
LL_GPDMA1_REQUEST_TIM3_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM3_UPD |
|
LL_GPDMA1_REQUEST_TIM4_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM4_CC1 |
|
LL_GPDMA1_REQUEST_TIM4_CH2 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM4_CC2 |
|
LL_GPDMA1_REQUEST_TIM4_CH3 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM4_CC3 |
|
LL_GPDMA1_REQUEST_TIM4_CH4 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM4_CC4 |
|
LL_GPDMA1_REQUEST_TIM4_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM4_UPD |
|
LL_GPDMA1_REQUEST_TIM5_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM5_CC1 |
|
LL_GPDMA1_REQUEST_TIM5_CH2 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM5_CC2 |
|
LL_GPDMA1_REQUEST_TIM5_CH3 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM5_CC3 |
|
LL_GPDMA1_REQUEST_TIM5_CH4 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM5_CC4 |
|
LL_GPDMA1_REQUEST_TIM5_TRIG |
H5, U5 |
LL_GPDMA1_REQUEST_TIM5_TRGI |
|
LL_GPDMA1_REQUEST_TIM5_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM5_UPD |
|
LL_GPDMA1_REQUEST_TIM6_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM6_UPD |
|
LL_GPDMA1_REQUEST_TIM7_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM7_UPD |
|
LL_GPDMA1_REQUEST_TIM8_CH1 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM8_CC1 |
|
LL_GPDMA1_REQUEST_TIM8_CH2 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM8_CC2 |
|
LL_GPDMA1_REQUEST_TIM8_CH3 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM8_CC3 |
|
LL_GPDMA1_REQUEST_TIM8_CH4 |
H5, U5 |
LL_GPDMA1_REQUEST_TIM8_CC4 |
|
LL_GPDMA1_REQUEST_TIM8_TRIG |
H5, U5 |
LL_GPDMA1_REQUEST_TIM8_TRGI |
|
LL_GPDMA1_REQUEST_TIM8_UP |
H5, U5 |
LL_GPDMA1_REQUEST_TIM8_UPD |
|
LL_GPDMA1_TRIGGER_GFXTIM_EVT0 |
H5 |
LL_GPDMA1_TRIGGER_GFXTIM_EVT1 |
|
LL_DMA_NORMAL |
H5, U5 |
Not implemented yet in HAL2. |
|
LL_DMA_PFCTRL |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_LPTIM5_IC1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_LPTIM5_IC2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_LPTIM5_UE |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_LPTIM6_IC1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_LPTIM6_IC2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_LPTIM6_UE |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_UART12_RX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_UART12_TX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_USART11_RX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_REQUEST_USART11_TX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_EVENTOUT |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_LPTIM4_AIT |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_LPTIM5_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_LPTIM5_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_LPTIM6_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA1_TRIGGER_LPTIM6_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_CORDIC_READ |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_CORDIC_WRITE |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_DAC1_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_DCMI |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_FMAC_READ |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_FMAC_WRITE |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_LPTIM5_IC1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_LPTIM5_IC2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_LPTIM5_UE |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_LPTIM6_IC1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_LPTIM6_IC2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_LPTIM6_UE |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_OCTOSPI1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM15_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM15_TRIG |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM15_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM16_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM16_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM17_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM17_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM1_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM1_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM1_CH3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM1_CH4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM1_TRIG |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM1_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM2_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM2_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM2_CH3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM2_CH4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM2_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM3_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM3_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM3_CH3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM3_CH4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM3_TRIG |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM3_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM4_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM4_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM4_CH3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM4_CH4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM4_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM5_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM5_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM5_CH3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM5_CH4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM5_TRIG |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM5_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM6_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM7_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM8_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM8_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM8_CH3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM8_CH4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM8_TRIG |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_TIM8_UP |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_UART12_RX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_UART12_TX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_USART11_RX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_REQUEST_USART11_TX |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_COMP1_OUT |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EVENTOUT |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE0 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE3 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE4 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE5 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE6 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_EXTI_LINE7 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_LPTIM4_AIT |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_LPTIM5_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_LPTIM5_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_LPTIM6_CH1 |
H5 |
Not implemented yet in HAL2. |
|
LL_GPDMA2_TRIGGER_LPTIM6_CH2 |
H5 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CCR_SOIE |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CCR_SOIE |
|
LL_DMAMUX_CFR_CSOF0 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CFR_CSOF |
|
LL_DMAMUX_CHANNEL_0 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH0 |
|
LL_DMAMUX_CHANNEL_1 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH1 |
|
LL_DMAMUX_CHANNEL_2 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH2 |
|
LL_DMAMUX_CHANNEL_3 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH3 |
|
LL_DMAMUX_CHANNEL_4 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH4 |
|
LL_DMAMUX_CHANNEL_5 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH5 |
|
LL_DMAMUX_CHANNEL_6 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CH6 |
|
LL_DMAMUX_CSR_SOF0 |
H7, G4, G0, L4, C0 |
LL_DMAMUX_CSR_SOF |
|
LL_DMAMUX_REQ_ADC1 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_ADC1 |
|
LL_DMAMUX_REQ_GENERATOR0 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_GENERATOR0 |
|
LL_DMAMUX_REQ_GENERATOR1 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_GENERATOR1 |
|
LL_DMAMUX_REQ_GENERATOR2 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_GENERATOR2 |
|
LL_DMAMUX_REQ_GENERATOR3 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_GENERATOR3 |
|
LL_DMAMUX_REQ_GEN_DMAMUX_CH0 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_DMAMUX_CH0 |
|
LL_DMAMUX_REQ_GEN_DMAMUX_CH1 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_DMAMUX_CH1 |
|
LL_DMAMUX_REQ_GEN_DMAMUX_CH2 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_DMAMUX_CH2 |
|
LL_DMAMUX_REQ_GEN_DMAMUX_CH3 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_DMAMUX_CH3 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE0 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE0 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE1 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE1 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE10 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE10 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE11 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE11 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE12 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE12 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE13 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE13 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE14 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE14 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE15 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE15 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE2 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE2 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE3 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE3 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE4 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE4 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE5 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE5 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE6 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE6 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE7 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE7 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE8 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE8 |
|
LL_DMAMUX_REQ_GEN_EXTI_LINE9 |
G4, G0, L4, C0 |
LL_DMAMUX1_REQ_GEN_EXTI_LINE9 |
|
LL_DMAMUX_REQ_GEN_TIM14_OC |
G0, C0 |
LL_DMAMUX1_REQ_GEN_TIM14_OC |
|
LL_DMAMUX_REQ_I2C1_RX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_I2C1_RX |
|
LL_DMAMUX_REQ_I2C1_TX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_I2C1_TX |
|
LL_DMAMUX_REQ_I2C2_RX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_I2C2_RX |
|
LL_DMAMUX_REQ_I2C2_TX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_I2C2_TX |
|
LL_DMAMUX_REQ_SPI1_RX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_SPI1_RX |
|
LL_DMAMUX_REQ_SPI1_TX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_SPI1_TX |
|
LL_DMAMUX_REQ_SPI2_RX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_SPI2_RX |
|
LL_DMAMUX_REQ_SPI2_TX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_SPI2_TX |
|
LL_DMAMUX_REQ_TIM15_CH1 |
L4, G4, G0, C0 |
LL_DMAMUX_REQ_TIM15_CC1 |
|
LL_DMAMUX_REQ_TIM15_CH2 |
G0, C0 |
LL_DMAMUX_REQ_TIM15_CC2 |
|
LL_DMAMUX_REQ_TIM15_TRIG_COM |
G0, C0 |
LL_DMAMUX1_REQ_TIM15_TRGI_COM |
|
LL_DMAMUX_REQ_TIM15_UP |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_TIM15_UPD |
|
LL_DMAMUX_REQ_TIM16_CH1 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_TIM16_CC1 |
|
LL_DMAMUX_REQ_TIM16_TRIG_COM |
U5, H7, L4, H5, G4, G0, F4, C0 |
LL_DMAMUX1_REQ_TIM16_TRGI_COM |
|
LL_DMAMUX_REQ_TIM16_UP |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_TIM16_UPD |
|
LL_DMAMUX_REQ_TIM17_CH1 |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_TIM17_CC1 |
|
LL_DMAMUX_REQ_TIM17_TRIG_COM |
C0 |
LL_DMAMUX1_REQ_TIM17_TRGI_COM |
|
LL_DMAMUX_REQ_TIM17_UP |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM17_UPD |
|
LL_DMAMUX_REQ_TIM1_CH1 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM1_CC1 |
|
LL_DMAMUX_REQ_TIM1_CH2 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM1_CC2 |
|
LL_DMAMUX_REQ_TIM1_CH3 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM1_CC3 |
|
LL_DMAMUX_REQ_TIM1_CH4 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM1_CC4 |
|
LL_DMAMUX_REQ_TIM1_TRIG_COM |
G0 |
LL_DMAMUX1_REQ_TIM1_TRGI_COM |
|
LL_DMAMUX_REQ_TIM1_UP |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM1_UPD |
|
LL_DMAMUX_REQ_TIM2_CH1 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM2_CC1 |
|
LL_DMAMUX_REQ_TIM2_CH2 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM2_CC2 |
|
LL_DMAMUX_REQ_TIM2_CH3 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM2_CC3 |
|
LL_DMAMUX_REQ_TIM2_CH4 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM2_CC4 |
|
LL_DMAMUX_REQ_TIM2_TRIG |
G0 |
LL_DMAMUX1_REQ_TIM2_TRGI_COM |
|
LL_DMAMUX_REQ_TIM2_UP |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM2_UPD |
|
LL_DMAMUX_REQ_TIM3_CH1 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM3_CC1 |
|
LL_DMAMUX_REQ_TIM3_CH2 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM3_CC2 |
|
LL_DMAMUX_REQ_TIM3_CH3 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM3_CC3 |
|
LL_DMAMUX_REQ_TIM3_CH4 |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM3_CC4 |
|
LL_DMAMUX_REQ_TIM3_TRIG |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM3_TRGI_COM |
|
LL_DMAMUX_REQ_TIM3_UP |
L4, G4, G0 |
LL_DMAMUX1_REQ_TIM3_UPD |
|
LL_DMAMUX_REQ_USART1_RX |
L4, G4, G0 |
LL_DMAMUX1_REQ_USART1_RX |
|
LL_DMAMUX_REQ_USART1_TX |
L4, G4, G0 |
LL_DMAMUX1_REQ_USART1_TX |
|
LL_DMAMUX_REQ_USART2_RX |
L4, G4, G0 |
LL_DMAMUX1_REQ_USART2_RX |
|
LL_DMAMUX_REQ_USART2_TX |
L4, G4, G0, C0 |
LL_DMAMUX1_REQ_USART2_TX |
|
LL_DMAMUX_REQ_USART3_RX |
L4, G4, G0 |
LL_DMAMUX1_REQ_USART3_RX |
|
LL_DMAMUX_REQ_USART3_TX |
L4, G4, G0 |
LL_DMAMUX1_REQ_USART3_TX |
|
LL_DMAMUX_REQ_USART4_RX |
G0 |
LL_DMAMUX1_REQ_USART4_RX |
|
LL_DMAMUX_REQ_USART4_TX |
G0 |
LL_DMAMUX1_REQ_USART4_TX |
|
LL_DMAMUX_RGCFR_RGCOF0 |
H7, G4, G0, L4 |
LL_DMAMUX_RGCFR_RGCOF |
|
LL_DMAMUX_RGSR_RGOF0 |
H7, G4, G0, L4 |
LL_DMAMUX_RGSR_RGOF |
|
LL_DMAMUX_SYNC_DMAMUX_CH0 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_DMAMUX_CH0 |
|
LL_DMAMUX_SYNC_DMAMUX_CH1 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_DMAMUX_CH0 |
|
LL_DMAMUX_SYNC_DMAMUX_CH2 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_DMAMUX_CH2 |
|
LL_DMAMUX_SYNC_DMAMUX_CH3 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_DMAMUX_CH3 |
|
LL_DMAMUX_SYNC_EXTI_LINE0 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE0 |
|
LL_DMAMUX_SYNC_EXTI_LINE1 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE1 |
|
LL_DMAMUX_SYNC_EXTI_LINE10 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE10 |
|
LL_DMAMUX_SYNC_EXTI_LINE11 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE11 |
|
LL_DMAMUX_SYNC_EXTI_LINE12 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE12 |
|
LL_DMAMUX_SYNC_EXTI_LINE13 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE13 |
|
LL_DMAMUX_SYNC_EXTI_LINE14 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE14 |
|
LL_DMAMUX_SYNC_EXTI_LINE15 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE15 |
|
LL_DMAMUX_SYNC_EXTI_LINE2 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE2 |
|
LL_DMAMUX_SYNC_EXTI_LINE3 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE3 |
|
LL_DMAMUX_SYNC_EXTI_LINE4 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE4 |
|
LL_DMAMUX_SYNC_EXTI_LINE5 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE5 |
|
LL_DMAMUX_SYNC_EXTI_LINE6 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE6 |
|
LL_DMAMUX_SYNC_EXTI_LINE7 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE7 |
|
LL_DMAMUX_SYNC_EXTI_LINE8 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE8 |
|
LL_DMAMUX_SYNC_EXTI_LINE9 |
G4, G0, L4 |
LL_DMAMUX1_SYNC_EXTI_LINE9 |
|
LL_DMAMUX_SYNC_TIM14_OC |
G0 |
LL_DMAMUX1_SYNC_TIM14_OC |
|
LL_DMA_CURRENTTARGETMEM0 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_CURRENTTARGETMEM1 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_DOUBLEBUFFER_MODE_DISABLE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_DOUBLEBUFFER_MODE_ENABLE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOMODE_DISABLE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOMODE_ENABLE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOSTATUS_0_25 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOSTATUS_25_50 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOSTATUS_50_75 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOSTATUS_75_100 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOSTATUS_EMPTY |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOSTATUS_FULL |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOTHRESHOLD_1_2 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOTHRESHOLD_1_4 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOTHRESHOLD_3_4 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_FIFOTHRESHOLD_FULL |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_MBURST_INC16 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_MBURST_INC4 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_MBURST_INC8 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_MBURST_SINGLE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_MODE_PFCTRL |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_OFFSETSIZE_FIXEDTO4 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_OFFSETSIZE_PSIZE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_PBURST_INC16 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_PBURST_INC4 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_PBURST_INC8 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_PBURST_SINGLE |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_0 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_1 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_2 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_3 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_4 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_5 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_6 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_7 |
H7 |
Not implemented yet in HAL2. |
|
LL_DMA_STREAM_ALL |
H7 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF10 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF11 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF5 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF6 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF7 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF8 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF9 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_10 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_11 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_7 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_8 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_9 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF10 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF11 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF5 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF6 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF7 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF8 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF9 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_MAX_REQ |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_AES_IN |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_AES_OUT |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC1_CH1 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC1_CH2 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_LPTIM1_OUT |
G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_LPTIM2_OUT |
G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_I2C3_RX |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_I2C3_TX |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_LPUART1_RX |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_LPUART1_TX |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_LPUART2_RX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_LPUART2_TX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SPI3_RX |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SPI3_TX |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM16_COM |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM17_COM |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM4_CH1 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM4_CH2 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM4_CH3 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM4_CH4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM4_TRIG |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM4_UP |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM6_UP |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM7_UP |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UCPD1_RX |
G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UCPD1_TX |
G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UCPD2_RX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UCPD2_TX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_USART5_RX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_USART5_TX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_USART6_RX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_USART6_TX |
G0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_LPTIM1_OUT |
G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_LPTIM2_OUT |
G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF12 |
H7, G4, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF13 |
H7, G4, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF14 |
H7, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF15 |
H7, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_12 |
H7, G4, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_13 |
H7, G4, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_14 |
H7, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CHANNEL_15 |
H7, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF12 |
H7, G4, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF13 |
H7, G4, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF14 |
H7, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF15 |
H7, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_ADC2 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_ADC3 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_ADC4 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_ADC5 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_CORDIC_READ |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_CORDIC_WRITE |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC2_CH1 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC3_CH1 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC3_CH2 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC4_CH1 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DAC4_CH2 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_FMAC_READ |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_FMAC_WRITE |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_A |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_B |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_C |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_D |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_E |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_F |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HRTIM1_M |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_I2C4_RX |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_I2C4_TX |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_QSPI |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SAI1_A |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SAI1_B |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SPI4_RX |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SPI4_TX |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM15_COM |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM15_TRIG |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM1_COM |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM1_TRIG |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_CH1 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_CH2 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_CH3 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_CH4 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_COM |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_TRIG |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM20_UP |
G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM5_CH1 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM5_CH2 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM5_CH3 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM5_CH4 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM5_TRIG |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM5_UP |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_CH1 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_CH2 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_CH3 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_CH4 |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_COM |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_TRIG |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_TIM8_UP |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UART4_RX |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UART4_TX |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UART5_RX |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_UART5_TX |
L4, G4 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CGIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CHTIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTCIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTEIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_GIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_HTIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TCIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TEIF8 |
G4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_0 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_1 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_2 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_3 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_4 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_5 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_6 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_REQUEST_7 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DCMI |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DCMI_PSSI |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DFSDM1_FLT0 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DFSDM1_FLT1 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DFSDM1_FLT2 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_DFSDM1_FLT3 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_DMA2D_TX_END |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_DSI_REFRESH_END |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_DSI_TE |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_LTDC_LINE_IT |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_HASH_IN |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_OSPI1 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_OSPI2 |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SAI2_A |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_SAI2_B |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_DMA2D_TX_END |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_DSI_REFRESH_END |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_DSI_TE |
L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_LTDC_LINE_IT |
L4 |
Not implemented yet in HAL2. |
|
LL_DMA_CHANNEL_ALL |
L4, H5, G4, G0, C0 |
Use One of DMA channels : LL_DMA_CHANNEL_X |
|
LL_GPDMA1_REQUEST_CORDIC_READ |
H5 |
LL_GPDMA1_REQUEST_CORDIC_RD |
|
LL_GPDMA1_REQUEST_CORDIC_WRITE |
H5 |
LL_GPDMA1_REQUEST_CORDIC_WR |
|
LL_GPDMA1_REQUEST_DCMI |
H5 |
LL_GPDMA1_REQUEST_DCMI_PSSI |
|
LL_GPDMA1_REQUEST_FMAC_READ |
H5 |
LL_GPDMA1_REQUEST_FMAC_RD |
|
LL_GPDMA1_REQUEST_FMAC_WRITE |
H5 |
LL_GPDMA1_REQUEST_FMAC_WR |
|
LL_DMA_CCR_HTIE |
L4, G4, G0 |
LL_DMA_CCR_HTIE |
|
LL_DMA_CCR_TCIE |
L4, G4, G0 |
LL_DMA_CCR_TCIE |
|
LL_DMA_CCR_TEIE |
L4, G4, G0 |
LL_DMA_CCR_TEIE |
|
LL_DMA_IFCR_CGIF1 |
L4, G4, G0 |
LL_DMA_IFCR_CGIF1 |
|
LL_DMA_IFCR_CGIF2 |
L4, G4, G0 |
LL_DMA_IFCR_CGIF2 |
|
LL_DMA_IFCR_CGIF3 |
L4, G4, G0 |
LL_DMA_IFCR_CGIF3 |
|
LL_DMA_IFCR_CGIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CGIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CGIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CGIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CHTIF1 |
L4, G4, G0 |
LL_DMA_IFCR_CHTIF1 |
|
LL_DMA_IFCR_CHTIF2 |
L4, G4, G0 |
LL_DMA_IFCR_CHTIF2 |
|
LL_DMA_IFCR_CHTIF3 |
L4, G4, G0 |
LL_DMA_IFCR_CHTIF3 |
|
LL_DMA_IFCR_CHTIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CHTIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CHTIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CHTIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTCIF1 |
L4, G4, G0 |
LL_DMA_IFCR_CTCIF1 |
|
LL_DMA_IFCR_CTCIF2 |
L4, G4, G0 |
LL_DMA_IFCR_CTCIF1 |
|
LL_DMA_IFCR_CTCIF3 |
L4, G4, G0 |
LL_DMA_IFCR_CTCIF1 |
|
LL_DMA_IFCR_CTCIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTCIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTCIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTCIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTEIF1 |
L4, G4, G0 |
LL_DMA_IFCR_CTEIF1 |
|
LL_DMA_IFCR_CTEIF2 |
L4, G4, G0 |
LL_DMA_IFCR_CTEIF2 |
|
LL_DMA_IFCR_CTEIF3 |
L4, G4, G0 |
LL_DMA_IFCR_CTEIF3 |
|
LL_DMA_IFCR_CTEIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTEIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTEIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_IFCR_CTEIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_GIF1 |
L4, G4, G0 |
LL_DMA_ISR_GIF1 |
|
LL_DMA_ISR_GIF2 |
L4, G4, G0 |
LL_DMA_ISR_GIF2 |
|
LL_DMA_ISR_GIF3 |
L4, G4, G0 |
LL_DMA_ISR_GIF3 |
|
LL_DMA_ISR_GIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_GIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_GIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_GIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_HTIF1 |
L4, G4, G0 |
LL_DMA_ISR_HTIF1 |
|
LL_DMA_ISR_HTIF2 |
L4, G4, G0 |
LL_DMA_ISR_HTIF2 |
|
LL_DMA_ISR_HTIF3 |
L4, G4, G0 |
LL_DMA_ISR_HTIF3 |
|
LL_DMA_ISR_HTIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_HTIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_HTIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_HTIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TCIF1 |
L4, G4, G0 |
LL_DMA_ISR_TCIF1 |
|
LL_DMA_ISR_TCIF2 |
L4, G4, G0 |
LL_DMA_ISR_TCIF2 |
|
LL_DMA_ISR_TCIF3 |
L4, G4, G0 |
LL_DMA_ISR_TCIF3 |
|
LL_DMA_ISR_TCIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TCIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TCIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TCIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TEIF1 |
L4, G4, G0 |
LL_DMA_ISR_TEIF1 |
|
LL_DMA_ISR_TEIF2 |
L4, G4, G0 |
LL_DMA_ISR_TEIF2 |
|
LL_DMA_ISR_TEIF3 |
L4, G4, G0 |
LL_DMA_ISR_TEIF3 |
|
LL_DMA_ISR_TEIF4 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TEIF5 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TEIF6 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_ISR_TEIF7 |
L4, G4, G0 |
Not implemented yet in HAL2. |
|
LL_DMA_MDATAALIGN_BYTE |
L4, H7, G4, G0, C0 |
LL_DMA_MDATAALIGN_BYTE |
|
LL_DMA_MDATAALIGN_HALFWORD |
L4, H7, G4, G0, C0 |
LL_DMA_MDATAALIGN_HALFWORD |
|
LL_DMA_MDATAALIGN_WORD |
L4, H7, G4, G0, C0 |
LL_DMA_MDATAALIGN_WORD |
|
LL_DMA_MEMORY_INCREMENT |
L4, H7, G4, G0, C0 |
LL_DMA_MEMORY_INCREMENT |
|
LL_DMA_MEMORY_NOINCREMENT |
L4, H7, G4, G0, C0 |
LL_DMA_MEMORY_NOINCREMENT |
|
LL_DMA_MODE_CIRCULAR |
L4, H7, G4, G0, C0 |
LL_DMA_MODE_CIRCULARdma |
|
LL_DMA_MODE_NORMAL |
L4, H7, G4, G0, C0 |
LL_DMA_MODE_NORMAL |
|
LL_DMA_PDATAALIGN_BYTE |
L4, H7, G4, G0, C0 |
LL_DMA_PDATAALIGN_BYTE |
|
LL_DMA_PDATAALIGN_HALFWORD |
L4, H7, G4, G0, C0 |
LL_DMA_PDATAALIGN_HALFWORD |
|
LL_DMA_PDATAALIGN_WORD |
L4, H7, G4, G0, C0 |
LL_DMA_PDATAALIGN_WORD |
|
LL_DMA_PERIPH_INCREMENT |
L4, H7, G4, G0, C0 |
LL_DMA_PERIPH_INCREMENT |
|
LL_DMA_PERIPH_NOINCREMENT |
L4, H7, G4, G0, C0 |
LL_DMA_PERIPH_NOINCREMENT |
|
LL_DMA_PRIORITY_LOW |
L4, H7, G4, G0, C0 |
LL_DMA_PRIORITY_LOW |
|
LL_DMA_PRIORITY_MEDIUM |
L4, H7, G4, G0, C0 |
LL_DMA_PRIORITY_MEDIUM |
|
LL_DMA_PRIORITY_VERYHIGH |
L4, H7, G4, G0, C0 |
LL_DMA_PRIORITY_VERYHIGH |
|
LL_DMAMUX_CFR_CSOF1 |
H7, G4, G0, L4 |
LL_DMAMUX_CFR_CSOF |
|
LL_DMAMUX_CFR_CSOF2 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF3 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CFR_CSOF4 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF1 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF2 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF3 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_CSR_SOF4 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_REQ_GEN_0 |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_0 |
|
LL_DMAMUX_REQ_GEN_1 |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_1 |
|
LL_DMAMUX_REQ_GEN_2 |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_2 |
|
LL_DMAMUX_REQ_GEN_3 |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_3 |
|
LL_DMAMUX_REQ_GEN_NO_EVENT |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_NO_EVENT |
|
LL_DMAMUX_REQ_GEN_POL_FALLING |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_POL_FALLING |
|
LL_DMAMUX_REQ_GEN_POL_RISING |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_POL_RISING |
|
LL_DMAMUX_REQ_GEN_POL_RISING_FALLING |
H7, G4, G0, L4 |
LL_DMAMUX_REQ_GEN_POL_RISING_FALLING |
|
LL_DMAMUX_REQ_MEM2MEM |
L4, G4, G0, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_RGCFR_RGCOF1 |
H7, G4, G0, L4, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_RGCFR_RGCOF2 |
H7, G4, G0, L4, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_RGCFR_RGCOF3 |
H7, G4, G0, L4, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_RGCR_RGOIE |
H7, G4, G0, L4, C0 |
LL_DMAMUX_RGCR_RGOIE |
|
LL_DMAMUX_RGSR_RGOF1 |
H7, G4, G0, L4, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_RGSR_RGOF2 |
H7, G4, G0, L4, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_RGSR_RGOF3 |
H7, G4, G0, L4, C0 |
Not implemented yet in HAL2. |
|
LL_DMAMUX_SYNC_NO_EVENT |
H7, G4, G0, L4, C0 |
LL_DMAMUX_SYNC_NO_EVENT |
|
LL_DMAMUX_SYNC_POL_FALLING |
H7, G4, G0, L4, C0 |
LL_DMAMUX_SYNC_POL_FALLING |
|
LL_DMAMUX_SYNC_POL_RISING |
H7, G4, G0, L4, C0 |
LL_DMAMUX_SYNC_POL_RISING |
|
LL_DMAMUX_SYNC_POL_RISING_FALLING |
H7, G4, G0, L4, C0 |
LL_DMAMUX_SYNC_POL_RISING_FALLING |
|
LL_DMA_CHANNEL_NSEC |
H5, U5 |
LL_DMA_ATTR_NSEC |
|
LL_DMA_CHANNEL_SEC |
H5, U5 |
LL_DMA_ATTR_SEC |
|
LL_DMA_CHANNEL_SRC_NSEC |
H5, U5 |
LL_DMA_SEC_ITEM_DEST |
|
LL_DMA_CHANNEL_SRC_SEC |
H5, U5 |
Removed / New Usage changes |
|
LL_DMA_CHANNEL_DEST_NSEC |
H5, U5 |
Removed / New Usage changes |
|
LL_DMA_CHANNEL_DEST_SEC |
H5, U5 |
Removed / New Usage changes |
LL DMA macros ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_DMA_WriteReg |
L4, H7, H5, G4, G0, F4, C0, U5 |
LL_DMA_WRITE_REG |
|
LL_DMA_ReadReg |
L4, H7, H5, G4, G0, F4, C0, U5 |
LL_DMA_READ_REG |
|
LL_DMA_GET_CHANNEL |
L4, H5, G4, G0, C0, U5 |
LL_DMA_GET_CHANNEL_IDX |
|
__LL_DMA_GET_CHANNEL |
L4, G4, G0, C0 |
LL_DMA_GET_CHANNEL_IDX |
|
__LL_DMA_GET_CHANNEL_INSTANCE |
L4, G4, G0, C0 |
LL_DMA_GET_CHANNEL_INSTANCE |
|
__LL_DMA_GET_INSTANCE |
L4, H7, G4, G0, C0, F4 |
LL_DMA_GET_INSTANCE |
|
LL_DMAMUX_ReadReg |
H7, G4, G0, L4, C0 |
LL_DMAMUX_READ_REG |
|
LL_DMAMUX_WriteReg |
H7, G4, G0, L4, C0 |
LL_DMAMUX_WRITE_REG |
|
__LL_DMA_GET_STREAM |
H7, F4 |
Not implemented yet in HAL2. |
|
__LL_DMA_GET_STREAM_INSTANCE |
H7, F4 |
Not implemented yet in HAL2. |
LL DMA functions ¶
|
HAL1 |
series |
HAL2 |
refer to |
|---|---|---|---|
|
LL_DMA_Init |
L4, H7, H5, G4, G0, C0, F4, U5 |
Removed in HAL2/new usage sequence |
|
|
LL_DMA_DeInit |
L4, H7, H5, G4, G0, C0, F4, U5 |
Removed in HAL2/new usage sequence |
|
|
LL_DMA_List_Init |
H5, U5 |
Removed in HAL2/new usage sequence |
|
|
LL_DMA_List_DeInit |
H5, U5 |
Removed in HAL2/new usage sequence |
|
|
LL_DMA_SetPeriphRequest |
L4, H7, H5, G4, G0, C0, U5 |
LL_DMAMUX_SetRequestID |
Refer to |
|
LL_DMA_GetPeriphRequest |
L4, H7, H5, G4, G0, C0, U5 |
LL_DMAMUX_GetRequestID |
Refer to |
|
LL_DMA_ClearFlag_DTE |
H5, U5 |
LL_DMA_ClearFlag_DTE |
refer to |
|
LL_DMA_ClearFlag_HT |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_ClearFlag_HT |
refer to |
|
LL_DMA_ClearFlag_SUSP |
H5, U5 |
LL_DMA_ClearFlag_SUSP |
refer to |
|
LL_DMA_ClearFlag_TC |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_ClearFlag_TC |
refer to |
|
LL_DMA_ClearFlag_TO |
H5, U5 |
LL_DMA_ClearFlag_TO |
refer to |
|
LL_DMA_ClearFlag_ULE |
H5, U5 |
LL_DMA_ClearFlag_ULE |
refer to |
|
LL_DMA_ClearFlag_USE |
H5, U5 |
LL_DMA_ClearFlag_USE |
refer to |
|
LL_DMA_ConfigAddrUpdateValue |
H5, U5 |
LL_DMA_ConfigAddrUpdateValue |
refer to |
|
LL_DMA_ConfigAddresses |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_ConfigAddresses |
refer to |
|
LL_DMA_ConfigBlkCounters |
H5, U5 |
LL_DMA_ConfigBlkCounters |
refer to |
|
LL_DMA_ConfigBlkRptAddrUpdate |
H5, U5 |
LL_DMA_ConfigBlkRptAddrUpdate |
refer to |
|
LL_DMA_ConfigBlkRptAddrUpdateValue |
H5, U5 |
LL_DMA_ConfigBlkRptAddrUpdateValue |
refer to |
|
LL_DMA_ConfigBurstLength |
H5, U5 |
LL_DMA_ConfigBurstLength |
refer to |
|
LL_DMA_ConfigControl |
H5, U5 |
LL_DMA_ConfigControl |
refer to |
|
LL_DMA_ConfigLinkUpdate |
H5, U5 |
LL_DMA_ConfigLinkUpdate |
refer to |
|
LL_DMA_ConfigTransfer |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_ConfigTransfer |
refer to |
|
LL_DMA_DisableCBR1Update |
H5, U5 |
LL_DMA_DisableCBR1Update |
refer to |
|
LL_DMA_DisableCBR2Update |
H5, U5 |
LL_DMA_DisableCBR2Update |
refer to |
|
LL_DMA_DisableCDARUpdate |
H5, U5 |
LL_DMA_DisableCDARUpdate |
refer to |
|
LL_DMA_DisableCLLRUpdate |
H5, U5 |
LL_DMA_DisableCLLRUpdate |
refer to |
|
LL_DMA_DisableCSARUpdate |
H5, U5 |
LL_DMA_DisableCSARUpdate |
refer to |
|
LL_DMA_DisableCTR1Update |
H5, U5 |
LL_DMA_DisableCTR1Update |
refer to |
|
LL_DMA_DisableCTR2Update |
H5, U5 |
LL_DMA_DisableCTR2Update |
refer to |
|
LL_DMA_DisableCTR3Update |
H5, U5 |
LL_DMA_DisableCTR3Update |
refer to |
|
LL_DMA_DisableChannel |
L4, H5, G4, G0 |
LL_DMA_DisableChannel |
refer to |
|
LL_DMA_DisableIT_DTE |
H5, U5 |
LL_DMA_DisableIT_DTE |
refer to |
|
LL_DMA_DisableIT_HT |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_DisableIT_HT |
refer to |
|
LL_DMA_DisableIT_SUSP |
H5, U5 |
LL_DMA_DisableIT_SUSP |
refer to |
|
LL_DMA_DisableIT_TC |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_DisableIT_TC |
refer to |
|
LL_DMA_DisableIT_TO |
H5, U5 |
LL_DMA_DisableIT_TO |
refer to |
|
LL_DMA_DisableIT_ULE |
H5, U5 |
LL_DMA_DisableIT_ULE |
refer to |
|
LL_DMA_DisableIT_USE |
H5, U5 |
LL_DMA_DisableIT_USE |
refer to |
|
LL_DMA_EnableCBR1Update |
H5, U5 |
LL_DMA_EnableCBR1Update |
refer to |
|
LL_DMA_EnableCBR2Update |
H5, U5 |
LL_DMA_EnableCBR2Update |
refer to |
|
LL_DMA_EnableCDARUpdate |
H5, U5 |
LL_DMA_EnableCDARUpdate |
refer to |
|
LL_DMA_EnableCLLRUpdate |
H5, U5 |
LL_DMA_EnableCLLRUpdate |
refer to |
|
LL_DMA_EnableCSARUpdate |
H5, U5 |
LL_DMA_EnableCSARUpdate |
refer to |
|
LL_DMA_EnableCTR1Update |
H5, U5 |
LL_DMA_EnableCTR1Update |
refer to |
|
LL_DMA_EnableCTR2Update |
H5, U5 |
LL_DMA_EnableCTR2Update |
refer to |
|
LL_DMA_EnableCTR3Update |
H5, U5 |
LL_DMA_EnableCTR3Update |
refer to |
|
LL_DMA_EnableChannel |
L4, H5, G4, G0, C0, U5 |
LL_DMA_EnableChannel |
refer to |
|
LL_DMA_EnableIT_DTE |
H5, U5 |
LL_DMA_EnableIT_DTE |
refer to |
|
LL_DMA_EnableIT_HT |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_EnableIT_HT |
refer to |
|
LL_DMA_EnableIT_SUSP |
H5, U5 |
LL_DMA_EnableIT_SUSP |
refer to |
|
LL_DMA_EnableIT_TC |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_EnableIT_TC |
refer to |
|
LL_DMA_EnableIT_TO |
H5, U5 |
LL_DMA_EnableIT_TO |
refer to |
|
LL_DMA_EnableIT_ULE |
H5, U5 |
LL_DMA_EnableIT_ULE |
refer to |
|
LL_DMA_EnableIT_USE |
H5, U5 |
LL_DMA_EnableIT_USE |
refer to |
|
LL_DMA_GetBlkDataLength |
H5, U5 |
LL_DMA_GetBlkDataLength |
refer to |
|
LL_DMA_GetBlkHWRequest |
H5, U5 |
LL_DMA_GetHWRequestType |
refer to |
|
LL_DMA_GetBlkRptCount |
H5, U5 |
LL_DMA_GetBlkRptCount |
refer to |
|
LL_DMA_GetBlkRptDestAddrUpdate |
H5, U5 |
LL_DMA_GetBlkRptDestAddrUpdate |
refer to |
|
LL_DMA_GetBlkRptDestAddrUpdateValue |
H5, U5 |
LL_DMA_GetBlkRptDestAddrUpdateValue |
refer to |
|
LL_DMA_GetBlkRptSrcAddrUpdate |
H5, U5 |
LL_DMA_GetBlkRptSrcAddrUpdate |
refer to |
|
LL_DMA_GetBlkRptSrcAddrUpdateValue |
H5, U5 |
LL_DMA_GetBlkRptSrcAddrUpdateValue |
refer to |
|
LL_DMA_GetChannelPriorityLevel |
L4, H5, G4, G0, C0, U5 |
LL_DMA_GetChannelPriorityLevel |
refer to |
|
LL_DMA_GetDataAlignment |
H5, U5 |
LL_DMA_GetDataAlignment |
refer to |
|
LL_DMA_GetDataTransferDirection |
L4, H7, H5, G4, G0, C0, U5, F4 |
LL_DMA_GetDataTransferDirection |
refer to |
|
LL_DMA_GetDestAddrUpdate |
H5, U5 |
LL_DMA_GetDestAddrUpdate |
refer to |
|
LL_DMA_GetDestAddrUpdateValue |
H5, U5 |
LL_DMA_GetDestAddrUpdateValue |
refer to |
|
LL_DMA_GetDestAddress |
H5, U5 |
LL_DMA_GetDestAddress |
refer to |
|
LL_DMA_GetDestAllocatedPort |
H5, U5 |
LL_DMA_GetDestAllocatedPort |
refer to |
|
LL_DMA_GetDestBurstLength |
H5, U5 |
LL_DMA_GetDestBurstLength |
refer to |
|
LL_DMA_GetDestByteExchange |
H5, U5 |
LL_DMA_GetDestByteExchange |
refer to |
|
LL_DMA_GetDestDataWidth |
H5, U5 |
LL_DMA_GetDestDataWidth |
refer to |
|
LL_DMA_GetDestHWordExchange |
H5, U5 |
LL_DMA_GetDestHWordExchange |
refer to |
|
LL_DMA_GetDestIncMode |
H5, U5 |
LL_DMA_GetDestIncMode |
refer to |
|
LL_DMA_GetFIFOLevel |
H5, U5 |
LL_DMA_GetFIFOLevel |
refer to |
|
LL_DMA_GetHWTrigger |
H5, U5 |
LL_DMA_GetHWTrigger |
refer to |
|
LL_DMA_GetLinkAllocatedPort |
H5, U5 |
LL_DMA_GetLinkAllocatedPort |
refer to |
|
LL_DMA_GetLinkStepMode |
H5, U5 |
LL_DMA_GetLinkStepMode |
refer to |
|
LL_DMA_GetLinkedListAddrOffset |
H5, U5 |
LL_DMA_GetLinkedListAddrOffset |
refer to |
|
LL_DMA_GetLinkedListBaseAddr |
H5, U5 |
LL_DMA_GetLinkedListBaseAddr |
refer to |
|
LL_DMA_GetSrcAddrUpdate |
H5, U5 |
LL_DMA_GetSrcAddrUpdate |
refer to |
|
LL_DMA_GetSrcAddrUpdateValue |
H5, U5 |
LL_DMA_GetSrcAddrUpdateValue |
refer to |
|
LL_DMA_GetSrcAddress |
H5, U5 |
LL_DMA_GetSrcAddress |
refer to |
|
LL_DMA_GetSrcAllocatedPort |
H5, U5 |
LL_DMA_GetSrcAllocatedPort |
refer to |
|
LL_DMA_GetSrcBurstLength |
H5, U5 |
LL_DMA_GetSrcBurstLength |
refer to |
|
LL_DMA_GetSrcByteExchange |
H5, U5 |
LL_DMA_GetSrcByteExchange |
refer to |
|
LL_DMA_GetSrcDataWidth |
H5, U5 |
LL_DMA_GetSrcDataWidth |
refer to |
|
LL_DMA_GetSrcIncMode |
H5, U5 |
LL_DMA_GetSrcIncMode |
refer to |
|
LL_DMA_GetTransferEventMode |
H5, U5 |
LL_DMA_GetTransferEventMode |
refer to |
|
LL_DMA_GetTriggerMode |
H5, U5 |
LL_DMA_GetTriggerMode |
refer to |
|
LL_DMA_GetTriggerPolarity |
H5, U5 |
LL_DMA_GetTriggerPolarity |
refer to |
|
LL_DMA_IsActiveFlag_DTE |
H5, U5 |
LL_DMA_IsActiveFlag_DTE |
refer to |
|
LL_DMA_IsActiveFlag_HT |
H5, U5 |
LL_DMA_IsActiveFlag_HT |
refer to |
|
LL_DMA_IsActiveFlag_IDLE |
H5, U5 |
LL_DMA_IsActiveFlag_IDLE |
refer to |
|
LL_DMA_IsActiveFlag_SUSP |
H5, U5 |
LL_DMA_IsActiveFlag_SUSP |
refer to |
|
LL_DMA_IsActiveFlag_TC |
H5, U5 |
LL_DMA_IsActiveFlag_TC |
refer to |
|
LL_DMA_IsActiveFlag_TO |
H5, U5 |
LL_DMA_IsActiveFlag_TO |
refer to |
|
LL_DMA_IsActiveFlag_ULE |
H5, U5 |
LL_DMA_IsActiveFlag_ULE |
refer to |
|
LL_DMA_IsActiveFlag_USE |
H5, U5 |
LL_DMA_IsActiveFlag_USE |
refer to |
|
LL_DMA_IsEnabledCBR1Update |
H5, U5 |
LL_DMA_IsEnabledCBR1Update |
refer to |
|
LL_DMA_IsEnabledCBR2Update |
H5, U5 |
LL_DMA_IsEnabledCBR2Update |
refer to |
|
LL_DMA_IsEnabledCDARUpdate |
H5, U5 |
LL_DMA_IsEnabledCDARUpdate |
refer to |
|
LL_DMA_IsEnabledCLLRUpdate |
H5, U5 |
LL_DMA_IsEnabledCLLRUpdate |
refer to |
|
LL_DMA_IsEnabledCSARUpdate |
H5, U5 |
LL_DMA_IsEnabledCSARUpdate |
refer to |
|
LL_DMA_IsEnabledCTR1Update |
H5, U5 |
LL_DMA_IsEnabledCTR1Update |
refer to |
|
LL_DMA_IsEnabledCTR2Update |
H5, U5 |
LL_DMA_IsEnabledCTR2Update |
refer to |
|
LL_DMA_IsEnabledCTR3Update |
H5, U5 |
LL_DMA_IsEnabledCTR3Update |
refer to |
|
LL_DMA_IsEnabledChannel |
L4, H5, G4, G0, U5, C0 |
LL_DMA_IsEnabledChannel |
refer to |
|
LL_DMA_IsEnabledIT_DTE |
H5, U5 |
LL_DMA_IsEnabledIT_DTE |
refer to |
|
LL_DMA_IsEnabledIT_HT |
L4, H7, H5, G4, G0, F4, U5, C0 |
LL_DMA_IsEnabledIT_HT |
refer to |
|
LL_DMA_IsEnabledIT_SUSP |
H5, U5 |
LL_DMA_IsEnabledIT_SUSP |
refer to |
|
LL_DMA_IsEnabledIT_TC |
L4, H7, H5, G4, G0, F4, U5, C0 |
LL_DMA_IsEnabledIT_TC |
refer to |
|
LL_DMA_IsEnabledIT_TO |
H5, U5 |
LL_DMA_IsEnabledIT_TO |
refer to |
|
LL_DMA_IsEnabledIT_ULE |
H5, U5 |
LL_DMA_IsEnabledIT_ULE |
refer to |
|
LL_DMA_IsEnabledIT_USE |
H5, U5 |
LL_DMA_IsEnabledIT_USE |
refer to |
|
LL_DMA_IsSuspendedChannel |
H5, U5 |
LL_DMA_IsSuspendedChannel |
refer to |
|
LL_DMA_ResetChannel |
H5, U5 |
LL_DMA_ResetChannel |
refer to |
|
LL_DMA_ResumeChannel |
H5, U5 |
LL_DMA_ResumeChannel |
refer to |
|
LL_DMA_SetBlkDataLength |
H5, U5 |
LL_DMA_SetBlkDataLength |
refer to |
|
LL_DMA_SetBlkHWRequest |
H5, U5 |
LL_DMA_SetHWRequestMode |
refer to |
|
LL_DMA_SetBlkRptCount |
H5, U5 |
LL_DMA_SetBlkRptCount |
refer to |
|
LL_DMA_SetBlkRptDestAddrUpdate |
H5, U5 |
LL_DMA_SetBlkRptDestAddrUpdate |
refer to |
|
LL_DMA_SetBlkRptDestAddrUpdateValue |
H5, U5 |
LL_DMA_SetBlkRptDestAddrUpdateValue |
refer to |
|
LL_DMA_SetBlkRptSrcAddrUpdate |
H5, U5 |
LL_DMA_SetBlkRptSrcAddrUpdate |
refer to |
|
LL_DMA_SetBlkRptSrcAddrUpdateValue |
H5, U5 |
LL_DMA_SetBlkRptSrcAddrUpdateValue |
refer to |
|
LL_DMA_SetChannelPriorityLevel |
L4, H5, G4, G0, C0, U5 |
LL_DMA_SetChannelPriorityLevel |
refer to |
|
LL_DMA_SetDataAlignment |
H5, U5 |
LL_DMA_SetDataAlignment |
refer to |
|
LL_DMA_SetDataTransferDirection |
L4, H7, H5, G4, G0, F4, C0, U5 |
LL_DMA_SetDataTransferDirection |
refer to |
|
LL_DMA_SetDestAddrUpdate |
H5, U5 |
LL_DMA_SetDestAddrUpdate |
refer to |
|
LL_DMA_SetDestAddrUpdateValue |
H5, U5 |
LL_DMA_SetDestAddrUpdateValue |
refer to |
|
LL_DMA_SetDestAddress |
H5, U5 |
LL_DMA_SetDestAddress |
refer to |
|
LL_DMA_SetDestAllocatedPort |
H5, U5 |
LL_DMA_SetDestAllocatedPort |
refer to |
|
LL_DMA_SetDestBurstLength |
H5, U5 |
LL_DMA_SetDestBurstLength |
refer to |
|
LL_DMA_SetDestByteExchange |
H5, U5 |
LL_DMA_SetDestByteExchange |
refer to |
|
LL_DMA_SetDestDataWidth |
H5, U5 |
LL_DMA_SetDestDataWidth |
refer to |
|
LL_DMA_SetDestHWordExchange |
H5, U5 |
LL_DMA_SetDestHWordExchange |
refer to |
|
LL_DMA_SetDestIncMode |
H5, U5 |
LL_DMA_SetDestIncMode |
refer to |
|
LL_DMA_SetHWTrigger |
H5, U5 |
LL_DMA_SetHWTrigger |
refer to |
|
LL_DMA_SetLinkAllocatedPort |
H5, U5 |
LL_DMA_SetLinkAllocatedPort |
refer to |
|
LL_DMA_SetLinkStepMode |
H5, U5 |
LL_DMA_SetLinkStepMode |
refer to |
|
LL_DMA_SetLinkedListAddrOffset |
H5, U5 |
LL_DMA_SetLinkedListAddrOffset |
refer to |
|
LL_DMA_SetLinkedListBaseAddr |
H5, U5 |
LL_DMA_SetLinkedListBaseAddr |
refer to |
|
LL_DMA_SetSrcAddrUpdate |
H5, U5 |
LL_DMA_SetSrcAddrUpdate |
refer to |
|
LL_DMA_SetSrcAddrUpdateValue |
H5, U5 |
LL_DMA_SetSrcAddrUpdateValue |
refer to |
|
LL_DMA_SetSrcAddress |
H5, U5 |
LL_DMA_SetSrcAddress |
refer to |
|
LL_DMA_SetSrcAllocatedPort |
H5, U5 |
LL_DMA_SetSrcAllocatedPort |
refer to |
|
LL_DMA_SetSrcBurstLength |
H5, U5 |
LL_DMA_SetSrcBurstLength |
refer to |
|
LL_DMA_SetSrcByteExchange |
H5, U5 |
LL_DMA_SetSrcByteExchange |
refer to |
|
LL_DMA_SetSrcDataWidth |
H5, U5 |
LL_DMA_SetSrcDataWidth |
refer to |
|
LL_DMA_SetSrcIncMode |
H5, U5 |
LL_DMA_SetSrcIncMode |
refer to |
|
LL_DMA_SetTransferEventMode |
H5, U5 |
LL_DMA_SetTransferEventMode |
refer to |
|
LL_DMA_SetTriggerMode |
H5, U5 |
LL_DMA_SetTriggerMode |
refer to |
|
LL_DMA_SetTriggerPolarity |
H5, U5 |
LL_DMA_SetTriggerPolarity |
refer to |
|
LL_DMA_SuspendChannel |
H5, U5 |
LL_DMA_SuspendChannel |
refer to |
|
LL_DMAMUX_ClearFlag_RGO0 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_RGO0 |
refer to |
|
LL_DMAMUX_ClearFlag_RGO1 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_RGO1 |
refer to |
|
LL_DMAMUX_ClearFlag_RGO2 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_RGO2 |
refer to |
|
LL_DMAMUX_ClearFlag_RGO3 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_RGO3 |
refer to |
|
LL_DMAMUX_ClearFlag_SO0 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_SO0 |
refer to |
|
LL_DMAMUX_ClearFlag_SO1 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_SO1 |
refer to |
|
LL_DMAMUX_ClearFlag_SO2 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_SO2 |
refer to |
|
LL_DMAMUX_ClearFlag_SO3 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_SO3 |
refer to |
|
LL_DMAMUX_ClearFlag_SO4 |
H7, G4, G0, L4 |
LL_DMAMUX_ClearFlag_SO4 |
refer to |
|
LL_DMAMUX_DisableEventGeneration |
H7, G4, G0, L4 |
LL_DMAMUX_DisableEventGeneration |
refer to |
|
LL_DMAMUX_DisableIT_RGO |
H7, G4, G0, L4 |
LL_DMAMUX_DisableIT_RGO |
refer to |
|
LL_DMAMUX_DisableIT_SO |
H7, G4, G0, L4 |
LL_DMAMUX_DisableIT_SO |
refer to |
|
LL_DMAMUX_DisableRequestGen |
H7, G4, G0, L4 |
LL_DMAMUX_DisableRequestGen |
refer to |
|
LL_DMAMUX_DisableSync |
H7, G4, G0, L4 |
LL_DMAMUX_DisableSync |
refer to |
|
LL_DMAMUX_EnableEventGeneration |
H7, G4, G0, L4 |
LL_DMAMUX_EnableEventGeneration |
refer to |
|
LL_DMAMUX_EnableIT_RGO |
H7, G4, G0, L4 |
LL_DMAMUX_EnableIT_RGO |
refer to |
|
LL_DMAMUX_EnableIT_SO |
H7, G4, G0, L4 |
LL_DMAMUX_EnableIT_SO |
refer to |
|
LL_DMAMUX_EnableRequestGen |
H7, G4, G0, L4 |
LL_DMAMUX_EnableRequestGen |
refer to |
|
LL_DMAMUX_EnableSync |
H7, G4, G0, L4 |
LL_DMAMUX_EnableSync |
refer to |
|
LL_DMAMUX_GetGenRequestNb |
H7, G4, G0, L4 |
LL_DMAMUX_GetGenRequestNb |
refer to |
|
LL_DMAMUX_GetRequestGenPolarity |
H7, G4, G0, L4 |
LL_DMAMUX_GetRequestGenPolarity |
refer to |
|
LL_DMAMUX_GetRequestID |
H7, G4, G0, L4 |
LL_DMAMUX_GetRequestID |
refer to |
|
LL_DMAMUX_GetRequestSignalID |
H7, G4, G0, L4 |
LL_DMAMUX_GetRequestSignalID |
refer to |
|
LL_DMAMUX_GetSyncID |
H7, G4, G0, L4 |
LL_DMAMUX_GetSyncID |
refer to |
|
LL_DMAMUX_GetSyncPolarity |
H7, G4, G0, L4 |
LL_DMAMUX_GetSyncPolarity |
refer to |
|
LL_DMAMUX_GetSyncRequestNb |
H7, G4, G0, L4 |
LL_DMAMUX_GetSyncRequestNb |
refer to |
|
LL_DMAMUX_IsActiveFlag_RGO0 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_RGO0 |
refer to |
|
LL_DMAMUX_IsActiveFlag_RGO1 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_RGO1 |
refer to |
|
LL_DMAMUX_IsActiveFlag_RGO2 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_RGO2 |
refer to |
|
LL_DMAMUX_IsActiveFlag_RGO3 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_RGO3 |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO0 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_SO0 |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO1 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_SO1 |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO2 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_SO2 |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO3 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_SO3 |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO4 |
H7, G4, G0, L4 |
LL_DMAMUX_IsActiveFlag_SO4 |
refer to |
|
LL_DMAMUX_IsEnabledEventGeneration |
H7, G4, G0, L4 |
LL_DMAMUX_IsEnabledEventGeneration |
refer to |
|
LL_DMAMUX_IsEnabledIT_RGO |
H7, G4, G0, L4 |
LL_DMAMUX_IsEnabledIT_RGO |
refer to |
|
LL_DMAMUX_IsEnabledIT_SO |
H7, G4, G0, L4 |
LL_DMAMUX_IsEnabledIT_SO |
refer to |
|
LL_DMAMUX_IsEnabledRequestGen |
H7, G4, G0, L4 |
LL_DMAMUX_IsEnabledRequestGen |
refer to |
|
LL_DMAMUX_IsEnabledSync |
H7, G4, G0, L4 |
LL_DMAMUX_IsEnabledSync |
refer to |
|
LL_DMAMUX_SetGenRequestNb |
H7, G4, G0, L4 |
LL_DMAMUX_SetGenRequestNb |
refer to |
|
LL_DMAMUX_SetRequestGenPolarity |
H7, G4, G0, L4 |
LL_DMAMUX_SetRequestGenPolarity |
refer to |
|
LL_DMAMUX_SetRequestID |
H7, G4, G0, L4 |
LL_DMAMUX_SetRequestID |
refer to |
|
LL_DMAMUX_SetRequestSignalID |
H7, G4, G0, L4 |
LL_DMAMUX_SetRequestSignalID |
refer to |
|
LL_DMAMUX_SetSyncID |
H7, G4, G0, L4 |
LL_DMAMUX_SetSyncID |
refer to |
|
LL_DMAMUX_SetSyncPolarity |
H7, G4, G0, L4 |
LL_DMAMUX_SetSyncPolarity |
refer to |
|
LL_DMAMUX_SetSyncRequestNb |
H7, G4, G0, L4 |
LL_DMAMUX_SetSyncRequestNb |
refer to |
|
LL_DMA_ClearFlag_GI1 |
L4, G4, G0, C0 |
LL_DMA_ClearFlag_GI1 |
refer to |
|
LL_DMA_ClearFlag_GI2 |
L4, G4, G0, C0 |
LL_DMA_ClearFlag_GI2 |
refer to |
|
LL_DMA_ClearFlag_GI3 |
L4, G4, G0, C0 |
LL_DMA_ClearFlag_GI3 |
refer to |
|
LL_DMA_ClearFlag_HT1 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT1 |
refer to |
|
LL_DMA_ClearFlag_HT2 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT2 |
refer to |
|
LL_DMA_ClearFlag_HT3 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT3 |
refer to |
|
LL_DMA_ClearFlag_HT4 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT4 |
refer to |
|
LL_DMA_ClearFlag_HT5 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT5 |
refer to |
|
LL_DMA_ClearFlag_HT6 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT6 |
refer to |
|
LL_DMA_ClearFlag_HT7 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_HT7 |
refer to |
|
LL_DMA_ClearFlag_TC1 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC1 |
refer to |
|
LL_DMA_ClearFlag_TC2 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC2 |
refer to |
|
LL_DMA_ClearFlag_TC3 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC3 |
refer to |
|
LL_DMA_ClearFlag_TC4 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC4 |
refer to |
|
LL_DMA_ClearFlag_TC5 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC5 |
refer to |
|
LL_DMA_ClearFlag_TC6 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC6 |
refer to |
|
LL_DMA_ClearFlag_TC7 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TC7 |
refer to |
|
LL_DMA_ClearFlag_TE1 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE1 |
refer to |
|
LL_DMA_ClearFlag_TE2 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE2 |
refer to |
|
LL_DMA_ClearFlag_TE3 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE3 |
refer to |
|
LL_DMA_ClearFlag_TE4 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE4 |
refer to |
|
LL_DMA_ClearFlag_TE5 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE5 |
refer to |
|
LL_DMA_ClearFlag_TE6 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE6 |
refer to |
|
LL_DMA_ClearFlag_TE7 |
L4, H7, G4, G0 |
LL_DMA_ClearFlag_TE7 |
refer to |
|
LL_DMA_DisableIT_TE |
L4, H7, G4, G0 |
LL_DMA_DisableIT_TE |
refer to |
|
LL_DMA_EnableIT_TE |
L4, H7, G4, G0 |
LL_DMA_EnableIT_TE |
refer to |
|
LL_DMA_GetDataLength |
L4, H7, G4, G0 |
LL_DMA_GetDataLength |
refer to |
|
LL_DMA_GetM2MDstAddress |
L4, H7, G4, G0 |
LL_DMA_GetM2MDstAddress |
refer to |
|
LL_DMA_GetM2MSrcAddress |
L4, H7, G4, G0 |
LL_DMA_GetM2MSrcAddress |
refer to |
|
LL_DMA_GetMemoryAddress |
L4, H7, G4, G0 |
LL_DMA_GetMemoryAddress |
refer to |
|
LL_DMA_GetMemoryIncMode |
L4, H7, G4, G0 |
LL_DMA_GetMemoryIncMode |
refer to |
|
LL_DMA_GetMemorySize |
L4, H7, G4, G0 |
LL_DMA_GetMemorySize |
refer to |
|
LL_DMA_GetMode |
L4, H7, G4, G0 |
LL_DMA_GetMode |
refer to |
|
LL_DMA_GetPeriphAddress |
L4, H7, G4, G0 |
LL_DMA_GetPeriphAddress |
refer to |
|
LL_DMA_GetPeriphIncMode |
L4, H7, G4, G0 |
LL_DMA_GetPeriphIncMode |
refer to |
|
LL_DMA_GetPeriphSize |
L4, H7, G4, G0 |
LL_DMA_GetPeriphSize |
refer to |
|
LL_DMA_IsActiveFlag_GI1 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI1 |
refer to |
|
LL_DMA_IsActiveFlag_GI2 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI2 |
refer to |
|
LL_DMA_IsActiveFlag_GI3 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI3 |
refer to |
|
LL_DMA_IsActiveFlag_GI4 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI4 |
refer to |
|
LL_DMA_IsActiveFlag_GI5 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI5 |
refer to |
|
LL_DMA_IsActiveFlag_GI6 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI6 |
refer to |
|
LL_DMA_IsActiveFlag_GI7 |
L4, G4, G0 |
LL_DMA_IsActiveFlag_GI7 |
refer to |
|
LL_DMA_IsActiveFlag_HT1 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT1 |
refer to |
|
LL_DMA_IsActiveFlag_HT2 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT2 |
refer to |
|
LL_DMA_IsActiveFlag_HT3 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT3 |
refer to |
|
LL_DMA_IsActiveFlag_HT4 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT4 |
refer to |
|
LL_DMA_IsActiveFlag_HT5 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT5 |
refer to |
|
LL_DMA_IsActiveFlag_HT6 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT6 |
refer to |
|
LL_DMA_IsActiveFlag_HT7 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_HT7 |
refer to |
|
LL_DMA_IsActiveFlag_TC1 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC1 |
refer to |
|
LL_DMA_IsActiveFlag_TC2 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC2 |
refer to |
|
LL_DMA_IsActiveFlag_TC3 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC3 |
refer to |
|
LL_DMA_IsActiveFlag_TC4 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC4 |
refer to |
|
LL_DMA_IsActiveFlag_TC5 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC5 |
refer to |
|
LL_DMA_IsActiveFlag_TC6 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC6 |
refer to |
|
LL_DMA_IsActiveFlag_TC7 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TC7 |
refer to |
|
LL_DMA_IsActiveFlag_TE1 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE1 |
refer to |
|
LL_DMA_IsActiveFlag_TE2 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE2 |
refer to |
|
LL_DMA_IsActiveFlag_TE3 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE3 |
refer to |
|
LL_DMA_IsActiveFlag_TE4 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE4 |
refer to |
|
LL_DMA_IsActiveFlag_TE5 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE5 |
refer to |
|
LL_DMA_IsActiveFlag_TE6 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE6 |
refer to |
|
LL_DMA_IsActiveFlag_TE7 |
L4, H7, G4, G0 |
LL_DMA_IsActiveFlag_TE7 |
refer to |
|
LL_DMA_IsEnabledIT_TE |
L4, H7, G4, G0 |
LL_DMA_IsEnabledIT_TE |
refer to |
|
LL_DMA_SetDataLength |
L4, H7, G4, G0, C0 |
LL_DMA_SetDataLength |
refer to |
|
LL_DMA_SetM2MDstAddress |
L4, H7, G4, G0 |
LL_DMA_SetM2MDstAddress |
refer to |
|
LL_DMA_SetM2MSrcAddress |
L4, H7, G4, G0 |
LL_DMA_SetM2MSrcAddress |
refer to |
|
LL_DMA_SetMemoryAddress |
L4, H7, G4, G0, C0 |
LL_DMA_SetMemoryAddress |
refer to |
|
LL_DMA_SetMemoryIncMode |
L4, H7, G4, G0 |
LL_DMA_SetMemoryIncMode |
refer to |
|
LL_DMA_SetMemorySize |
L4, H7, G4, G0 |
LL_DMA_SetMemorySize |
refer to |
|
LL_DMA_SetMode |
L4, H7, G4, G0 |
LL_DMA_SetMode |
refer to |
|
LL_DMA_SetPeriphAddress |
L4, H7, G4, G0, C0 |
LL_DMA_SetPeriphAddress |
refer to |
|
LL_DMA_SetPeriphIncMode |
L4, H7, G4, G0 |
LL_DMA_SetPeriphIncMode |
refer to |
|
LL_DMA_SetPeriphSize |
L4, H7, G4, G0 |
LL_DMA_SetPeriphSize |
refer to |
|
LL_DMA_ClearFlag_DME0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME1 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME2 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME3 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME4 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME5 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME6 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_DME7 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE1 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE2 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE3 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE4 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE5 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE6 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_FE7 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_HT0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_TC0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_TE0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ConfigFifo |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_DisableDoubleBufferMode |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_DisableFifoMode |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_DisableIT_DME |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_DisableIT_FE |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_DisableStream |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_EnableDoubleBufferMode |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_EnableFifoMode |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_EnableIT_DME |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_EnableIT_FE |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_EnableStream |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetChannelSelection |
F4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetCurrentTargetMem |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetFIFOStatus |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetFIFOThreshold |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetIncOffsetSize |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetMemory1Address |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetMemoryBurstxfer |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetPeriphBurstxfer |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_GetStreamPriorityLevel |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME1 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME2 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME3 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME4 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME5 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME6 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_DME7 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE1 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE2 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE3 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE4 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE5 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE6 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_FE7 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_HT0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_TC0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_TE0 |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsEnabledIT_DME |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsEnabledIT_FE |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsEnabledStream |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetChannelSelection |
F4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetCurrentTargetMem |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetFIFOThreshold |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetIncOffsetSize |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetMemory1Address |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetMemoryBurstxfer |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetPeriphBurstxfer |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_SetStreamPriorityLevel |
H7 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO10 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO11 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO5 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO6 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO7 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO8 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO9 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO10 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO11 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO5 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO6 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO7 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO8 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO9 |
H7, G4, G0, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO12 |
H7, G4, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO13 |
H7, G4, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO14 |
H7, G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_ClearFlag_SO15 |
H7, G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO12 |
H7, G4, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO13 |
H7, G4, L4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO14 |
H7, G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMAMUX_IsActiveFlag_SO15 |
H7, G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_GI8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_HT8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_TC8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ClearFlag_TE8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_GI8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_HT8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_TC8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_IsActiveFlag_TE8 |
G4 |
Not implemented yet in HAL2. |
refer to |
|
LL_DMA_ConfigChannelTransfer |
H5, U5 |
LL_DMA_ConfigChannelTransfer |
Refer to |
|
LL_DMA_ConnectLinkNode |
H5, U5 |
LL_DMA_ConfigLinkUpdate |
Refer to |
|
LL_DMA_ClearFlag_GI4 |
L4, G4, G0, C0 |
Not implemented yet in HAL2. |
Refer to |
|
LL_DMA_ClearFlag_GI5 |
L4, G4, G0, C0 |
Not implemented yet in HAL2. |
Refer to |
|
LL_DMA_ClearFlag_GI6 |
L4, G4, G0, C0 |
Not implemented yet in HAL2. |
Refer to |
|
LL_DMA_ClearFlag_GI7 |
L4, G4, G0, C0 |
Not implemented yet in HAL2. |
Refer to |
|
LL_DMA_ConfigChannelSecure |
H5, U5 |
LL_DMA_SetXferSecAttr LL_DMA_SetSecAttr |
|
|
LL_DMA_EnableChannelSrcSecure |
H5, U5 |
LL_DMA_SetXferSecAttr |
|
|
LL_DMA_DisableChannelSrcSecure |
H5, U5 |
LL_DMA_SetXferSecAttr |
|
|
LL_DMA_IsEnabledChannelSrcSecure |
H5, U5 |
LL_DMA_GetXferSecAttr |
|
|
LL_DMA_EnableChannelDestSecure |
H5, U5 |
LL_DMA_SetXferSecAttr |
|
|
LL_DMA_DisableChannelDestSecure |
H5, U5 |
LL_DMA_SetXferSecAttr |
|
|
LL_DMA_IsEnabledChannelDestSecure |
H5, U5 |
LL_DMA_GetXferSecAttr |
|
|
LL_DMA_EnableChannelSecure |
H5, U5 |
LL_DMA_SetSecAttr |
|
|
LL_DMA_DisableChannelSecure |
H5, U5 |
LL_DMA_SetSecAttr |
|
|
LL_DMA_IsEnabledChannelSecure |
H5, U5 |
LL_DMA_GetSecAttr |
|
|
LL_DMA_EnableChannelPrivilege |
H5, U5 |
LL_DMA_SetPrivAttr |
|
|
LL_DMA_DisableChannelPrivilege |
H5, U5 |
LL_DMA_SetPrivAttr |
|
|
LL_DMA_IsEnabledChannelPrivilege |
H5, U5 |
LL_DMA_GetPrivAttr |
|
|
LL_DMA_EnableChannelLockAttribute |
H5, U5 |
LL_DMA_LockAttr |
|
|
LL_DMA_IsEnabledChannelLockAttribute |
H5, U5 |
LL_DMA_IsLockedAttr |