Reference Manual to LL API cross reference ¶

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for BUS registers

Register	Bit	Function
AHB1ENR	ADF1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	HSPEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	OTGFSEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1LPENR	ADF1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	GPDMA1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	HSPLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	OTGFSLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1RSTR	ADF1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPDMA1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	HSPRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	OTGFSRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB2ENR	AHBSRAM1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AHBSRAM2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AHBSRAM3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	CORDICEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	FMAC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2LPENR	AHBSRAM1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AHBSRAM2LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AHBSRAM3LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	CORDICLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	FMAC1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2RSTR	CORDICRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	FMAC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB3ENR	ADC12EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	ADC34EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC2EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC3EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	HASHEN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	RNGEN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3LPENR	ADC12LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	ADC34LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC1LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC2LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC3LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC4LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	HASHLPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	RNGLPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3RSTR	ADC12RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	ADC34RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC2RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC3RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC4RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	HASHRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	RNGRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB4ENR	BKPRAMEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	CRCEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOAEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOBEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOCEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIODEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOEEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOFEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOGEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOHEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOIEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4LPENR	BKPRAMLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	CRCLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOALPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOBLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOCLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIODLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOELPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOFLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOGLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOHLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOILPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4RSTR	CRCRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOARST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOBRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOCRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIODRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOERST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOFRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOGRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOHRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOIRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB5ENR	FMCEN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	HPDMA1EN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	NPUEN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	SDMMC1EN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	XSPI1EN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5LPENR	AXISRAMLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	DTCM1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	DTCM2LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	FLASHLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	FMCLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	HPDMA1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	ITCMLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	NPULPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	SDMMC1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	XSPI1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5RSTR	FMCRST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	HPDMA1RST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	NPURST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	SDMMC1RST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	XSPI1RST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
APB1ENR1	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I3C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	LPTIM1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM10EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM11EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM12EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM13EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM14EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART8EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR2	CRSEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	FDCANEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	UCPD1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1LPENR1	I2C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	I2C2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	I2C3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	I3C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	LPTIM1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	SPI2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	SPI3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM10LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM11LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM12LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM13LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM14LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART8LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	USART2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	USART3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	WWDGLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR2	CRSLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1LPENR2	FDCANLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1LPENR2	UCPD1LPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1RSTR1	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I3C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	LPTIM1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM10RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM11RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM12RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM13RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM14RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART8RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR2	CRSRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	FDCANRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPD1RST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB2ENR	HRTIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	HRTIM2EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI4EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI5EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM20EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM9EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	UART9EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART10EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART6EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2LPENR	HRTIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	HRTIM2LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	SPI1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	SPI4LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	SPI5LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM15LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM16LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM17LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM20LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM8LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM9LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	UART9LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART10LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART6LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2RSTR	HRTIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	HRTIM2RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI4RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI5RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM20RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM9RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	UART9RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART10RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART6RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB4ENR	COMP12EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	COMP34EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	COMP56EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	COMP78EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	DTSEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM2EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM3EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM4EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM5EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPUART1EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	RTCAPBEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	SBSEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	SPI6EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	VREFEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4LPENR	COMP12LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	COMP34LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	COMP56LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	COMP78LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	DTSLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM2LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM3LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM4LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM5LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPUART1LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	RTCAPBLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	SBSLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	SPI6LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	VREFLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4RSTR	COMP12RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	COMP34RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	COMP56RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	COMP78RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	DTSRST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM2RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM3RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM4RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM5RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPUART1RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	SBSRST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	SPI6RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	VREFRST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
CKGDISR	AHBICCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AHBMCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AHBSCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXICKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM2CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM3CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM4CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	CPUCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	EXTICKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	FLASHCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	FMCCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	HPDMA1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	JTAGCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	NPU0CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	NPU1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	SDMMC1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	XSPI1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`

Register	Bit	Function
AHB1ENR	ADF1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	GPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	HSPEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	OTGFSEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1LPENR	ADF1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	GPDMA1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	HSPLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	OTGFSLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1RSTR	ADF1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	GPDMA1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	HSPRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	OTGFSRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB2ENR	AHBSRAM1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AHBSRAM2EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AHBSRAM3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	CORDICEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	FMAC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2LPENR	AHBSRAM1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AHBSRAM2LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AHBSRAM3LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	CORDICLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	FMAC1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2RSTR	CORDICRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	FMAC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB3ENR	ADC12EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	ADC34EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC1EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC2EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC3EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	DAC4EN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	HASHEN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3ENR	RNGEN	`LL_AHB3_GRP1_DisableClock()` `LL_AHB3_GRP1_EnableClock()` `LL_AHB3_GRP1_IsEnabledClock()`
AHB3LPENR	ADC12LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	ADC34LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC1LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC2LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC3LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	DAC4LPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	HASHLPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3LPENR	RNGLPEN	`LL_AHB3_GRP1_DisableClockLowPower()` `LL_AHB3_GRP1_EnableClockLowPower()` `LL_AHB3_GRP1_IsEnabledClockLowPower()`
AHB3RSTR	ADC12RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	ADC34RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC1RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC2RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC3RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	DAC4RST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	HASHRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB3RSTR	RNGRST	`LL_AHB3_GRP1_ForceReset()` `LL_AHB3_GRP1_ReleaseReset()`
AHB4ENR	BKPRAMEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	CRCEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOAEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOBEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOCEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIODEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOEEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOFEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOGEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOHEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4ENR	GPIOIEN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4LPENR	BKPRAMLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	CRCLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOALPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOBLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOCLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIODLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOELPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOFLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOGLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOHLPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4LPENR	GPIOILPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4RSTR	CRCRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOARST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOBRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOCRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIODRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOERST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOFRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOGRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOHRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB4RSTR	GPIOIRST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
AHB5ENR	FMCEN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	HPDMA1EN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	NPUEN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	SDMMC1EN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5ENR	XSPI1EN	`LL_AHB5_GRP1_DisableClock()` `LL_AHB5_GRP1_EnableClock()` `LL_AHB5_GRP1_IsEnabledClock()`
AHB5LPENR	AXISRAMLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	DTCM1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	DTCM2LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	FLASHLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	FMCLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	HPDMA1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	ITCMLPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	NPULPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	SDMMC1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5LPENR	XSPI1LPEN	`LL_AHB5_GRP1_DisableClockLowPower()` `LL_AHB5_GRP1_EnableClockLowPower()` `LL_AHB5_GRP1_IsEnabledClockLowPower()`
AHB5RSTR	FMCRST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	HPDMA1RST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	NPURST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	SDMMC1RST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
AHB5RSTR	XSPI1RST	`LL_AHB5_GRP1_ForceReset()` `LL_AHB5_GRP1_ReleaseReset()`
APB1ENR1	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I2C3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	I3C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	LPTIM1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	SPI3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM10EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM11EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM12EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM13EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM14EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	UART8EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR1	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1ENR2	CRSEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	FDCANEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1ENR2	UCPD1EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1LPENR1	I2C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	I2C2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	I2C3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	I3C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	LPTIM1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	SPI2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	SPI3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM10LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM11LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM12LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM13LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM14LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	TIM7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	UART8LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	USART2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	USART3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR1	WWDGLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LPENR2	CRSLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1LPENR2	FDCANLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1LPENR2	UCPD1LPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1RSTR1	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I2C3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	I3C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	LPTIM1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	SPI3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM10RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM11RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM12RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM13RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM14RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	UART8RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR1	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1RSTR2	CRSRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	FDCANRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1RSTR2	UCPD1RST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB2ENR	HRTIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	HRTIM2EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI4EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	SPI5EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM20EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM9EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	UART9EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART10EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART6EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2LPENR	HRTIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	HRTIM2LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	SPI1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	SPI4LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	SPI5LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM15LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM16LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM17LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM20LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM8LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM9LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	UART9LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART10LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART6LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2RSTR	HRTIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	HRTIM2RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI4RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	SPI5RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM20RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM9RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	UART9RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART10RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART6RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB4ENR	COMP12EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	COMP34EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	COMP56EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	COMP78EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	DTSEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM2EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM3EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM4EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPTIM5EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	LPUART1EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	RTCAPBEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	SBSEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	SPI6EN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4ENR	VREFEN	`LL_APB4_GRP1_DisableClock()` `LL_APB4_GRP1_EnableClock()` `LL_APB4_GRP1_IsEnabledClock()`
APB4LPENR	COMP12LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	COMP34LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	COMP56LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	COMP78LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	DTSLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM2LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM3LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM4LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPTIM5LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	LPUART1LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	RTCAPBLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	SBSLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	SPI6LPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4LPENR	VREFLPEN	`LL_APB4_GRP1_DisableClockLowPower()` `LL_APB4_GRP1_EnableClockLowPower()` `LL_APB4_GRP1_IsEnabledClockLowPower()`
APB4RSTR	COMP12RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	COMP34RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	COMP56RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	COMP78RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	DTSRST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM2RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM3RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM4RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPTIM5RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	LPUART1RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	SBSRST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	SPI6RST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
APB4RSTR	VREFRST	`LL_APB4_GRP1_ForceReset()` `LL_APB4_GRP1_ReleaseReset()`
CKGDISR	AHBICCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AHBMCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AHBSCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXICKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM2CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM3CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	AXISRAM4CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	CPUCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	EXTICKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	FLASHCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	FMCCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	HPDMA1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	JTAGCKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	NPU0CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	NPU1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	SDMMC1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`
CKGDISR	XSPI1CKG	`LL_CKG_Disable()` `LL_CKG_Enable()` `LL_CKG_IsEnabled()`