Reference Manual to LL API cross reference ¶

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for RCC registers

Register	Bit	Function
APBCFGR	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
APBCFGR	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
APBCFGR	PPRE4	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB4Prescaler()` `LL_RCC_SetAPB4Prescaler()`
BDCR	LSEBYP	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()` `LL_RCC_LSE_IsBypassed()`
BDCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
BDCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
BDCR	LSECSSRA	`LL_RCC_LSE_ResetRearmCSS()` `LL_RCC_LSE_SetRearmCSS()`
BDCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
BDCR	LSEEXT	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_GetExternalClockType()` `LL_RCC_LSE_SetExternalClockType()`
BDCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
BDCR	LSERDY	`LL_RCC_LSE_IsReady()`
BDCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
BDCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`
BDCR	VSWRST	`LL_RCC_ForceBackupDomainReset()` `LL_RCC_ReleaseBackupDomainReset()`
BMCFGR	BMPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetBMPrescaler()` `LL_RCC_SetBMPrescaler()`
CCIPR1	ADCDIV	`LL_RCC_GetADCPrescaler()` `LL_RCC_SetADCPrescaler()`
CCIPR1	ADCSEL	`LL_RCC_GetADCClockSource()` `LL_RCC_SetADCClockSource()`
CCIPR1	ADF1SEL	`LL_RCC_GetADFClockSource()` `LL_RCC_SetADFClockSource()`
CCIPR1	CKPERSEL	`LL_RCC_PERCLK_GetSource()` `LL_RCC_PERCLK_SetSource()`
CCIPR1	FMCSEL	`LL_RCC_GetFMCClockSource()` `LL_RCC_SetFMCClockSource()`
CCIPR1	OTGFSSEL	`LL_RCC_GetUSBOTGFSClockSource()` `LL_RCC_SetUSBOTGFSClockSource()`
CCIPR1	SDMMC1SEL	`LL_RCC_GetSDMMCClockSource()` `LL_RCC_SetSDMMCClockSource()`
CCIPR1	XSPI1SEL	`LL_RCC_GetXSPIClockSource()` `LL_RCC_SetXSPIClockSource()`
CCIPR2		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR2	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR2	I2C123SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I3C1SEL	`LL_RCC_GetI3CClockSource()` `LL_RCC_SetI3CClockSource()`
CCIPR2	LPTIM1SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR2	SPI23SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR2	UART234578SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR3		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR3	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR3	SPI45SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR3	USART16910SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR4		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR4	DAC1SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	DAC1SHSEL	`LL_RCC_GetDACSHClockSource()` `LL_RCC_SetDACSHClockSource()`
CCIPR4	DAC2SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	DAC3SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	DAC4SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	LPTIM23SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR4	LPTIM45SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR4	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()` `LL_RCC_SetLPUARTClockSource()`
CCIPR4	SPI6SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR5	ADCDIV	`LL_RCC_ConfigADC()`
CDCFGR	CPRE	`LL_RCC_GetSysPrescaler()` `LL_RCC_SetSysPrescaler()`
CFGR	MCO1PRE	`LL_RCC_ConfigMCO()`
CFGR	MCO1SEL	`LL_RCC_ConfigMCO()`
CFGR	MCO2PRE	`LL_RCC_ConfigMCO()`
CFGR	MCO2SEL	`LL_RCC_ConfigMCO()`
CFGR	RTCPRE	`LL_RCC_GetRTC_HSEPrescaler()` `LL_RCC_SetRTC_HSEPrescaler()`
CFGR	STOPKERWUCK	`LL_RCC_GetKerClkAfterWakeFromStop()` `LL_RCC_SetKerClkAfterWakeFromStop()`
CFGR	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR	SW	`LL_RCC_SetSysClkSource()`
CFGR	SWS	`LL_RCC_GetSysClkSource()`
CICR	CSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_CSIRDY()`
CICR	HSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSI48RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSI48RDY()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	LSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSECSS()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	PLL1RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL1RDY()`
CICR	PLL2RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL2RDY()`
CICR	PLL3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL3RDY()`
CIER	CSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_CSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_CSIRDY()` `LL_RCC_IsEnabledIT_CSIRDY()`
CIER	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSI48RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSI48RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSI48RDY()` `LL_RCC_IsEnabledIT_HSI48RDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSECSSIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSECSS()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSECSS()` `LL_RCC_IsEnabledIT_LSECSS()`
CIER	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	PLL1RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PLL1RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PLL1RDY()` `LL_RCC_IsEnabledIT_PLL1RDY()`
CIER	PLL2RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PLL2RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PLL2RDY()` `LL_RCC_IsEnabledIT_PLL2RDY()`
CIER	PLL3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PLL3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PLL3RDY()` `LL_RCC_IsEnabledIT_PLL3RDY()`
CIFR	CSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_CSIRDY()`
CIFR	HSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSI48RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSI48RDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSECSS()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	PLL1RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PLL1RDY()`
CIFR	PLL2RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PLL2RDY()`
CIFR	PLL3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PLL3RDY()`
CKPROTR	FMCCKP	`LL_RCC_DisableFMCClockProtection()` `LL_RCC_EnableFMCClockProtection()` `LL_RCC_IsEnabledFMCClockProtection()`
CKPROTR	FMCSWP	`LL_RCC_GetFMCSwitchPosition()`
CKPROTR	XSPICKP	`LL_RCC_DisableXSPIClockProtection()` `LL_RCC_EnableXSPIClockProtection()` `LL_RCC_IsEnabledXSPIClockProtection()`
CKPROTR	XSPISWP	`LL_RCC_GetXSPISwitchPosition()`
CR	CSIKERON	`LL_RCC_CSI_DisableInStopMode()` `LL_RCC_CSI_EnableInStopMode()` `LL_RCC_CSI_IsEnabledInStopMode()`
CR	CSION	`LL_RCC_CSI_Disable()` `LL_RCC_CSI_Enable()` `LL_RCC_CSI_IsEnabled()`
CR	CSIRDY	`LL_RCC_CSI_IsReady()`
CR	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR	HSECSSON	`LL_RCC_HSE_EnableCSS()`
CR	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetExternalClockType()` `LL_RCC_HSE_SetExternalClockType()`
CR	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR	HSERDY	`LL_RCC_HSE_IsReady()`
CR	HSI48ON	`LL_RCC_HSI48_Disable()` `LL_RCC_HSI48_Enable()` `LL_RCC_HSI48_IsEnabled()`
CR	HSI48RDY	`LL_RCC_HSI48_IsReady()`
CR	HSIDIV	`LL_RCC_HSI_GetDivider()` `LL_RCC_HSI_SetDivider()`
CR	HSIDIVF	`LL_RCC_HSI_IsDividerReady()`
CR	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR	HSION	`LL_RCC_HSI_Disable()` `LL_RCC_HSI_Enable()` `LL_RCC_HSI_IsEnabled()`
CR	HSIRDY	`LL_RCC_HSI_IsReady()`
CR	PLL1ON	`LL_RCC_PLL1_Disable()` `LL_RCC_PLL1_Enable()`
CR	PLL1RDY	`LL_RCC_PLL1_IsReady()`
CR	PLL2ON	`LL_RCC_PLL2_Disable()` `LL_RCC_PLL2_Enable()`
CR	PLL2RDY	`LL_RCC_PLL2_IsReady()`
CR	PLL3ON	`LL_RCC_PLL3_Disable()` `LL_RCC_PLL3_Enable()`
CR	PLL3RDY	`LL_RCC_PLL3_IsReady()`
CRRCR	HSI48CAL	`LL_RCC_HSI48_GetCalibration()`
CSICFGR	CSICAL	`LL_RCC_CSI_GetCalibration()`
CSICFGR	CSITRIM	`LL_RCC_CSI_GetCalibTrimming()` `LL_RCC_CSI_SetCalibTrimming()`
CSR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
CSR	LSIRDY	`LL_RCC_LSI_IsReady()`
HSICFGR	HSICAL	`LL_RCC_HSI_GetCalibration()`
HSICFGR	HSITRIM	`LL_RCC_HSI_GetCalibTrimming()` `LL_RCC_HSI_SetCalibTrimming()`
PLL1DIVR1	DIVN	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetN()` `LL_RCC_PLL1_SetN()`
PLL1DIVR1	DIVP	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetP()` `LL_RCC_PLL1_SetP()`
PLL1DIVR1	DIVQ	`LL_RCC_PLL1_GetQ()` `LL_RCC_PLL1_SetQ()`
PLL1DIVR2	DIVS	`LL_RCC_PLL1_GetS()` `LL_RCC_PLL1_SetS()`
PLL1FRACR	FRACN	`LL_RCC_PLL1_GetFRACN()`
PLL1SSCGR	INCSTEP	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_GetSSCGIncrementStep()` `LL_RCC_PLL1_SetSSCGIncrementStep()`
PLL1SSCGR	MODPER	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_GetSSCGModulationPeriod()` `LL_RCC_PLL1_SetSSCGModulationPeriod()`
PLL1SSCGR	RPDFNDIS	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_DisableSSCGRPDFNDithering()` `LL_RCC_PLL1_EnableSSCGRPDFNDithering()` `LL_RCC_PLL1_GetSSCGDithering()` `LL_RCC_PLL1_IsEnabledSSCGRPDFNDithering()`
PLL1SSCGR	SPREADSEL	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_GetSSCGSpreadSelection()` `LL_RCC_PLL1_SetSSCGSpreadSelection()`
PLL1SSCGR	TPDFNDIS	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_DisableSSCGTPDFNDithering()` `LL_RCC_PLL1_EnableSSCGTPDFNDithering()` `LL_RCC_PLL1_GetSSCGDithering()` `LL_RCC_PLL1_IsEnabledSSCGTPDFNDithering()`
PLL2DIVR1	DIVN	`LL_RCC_PLL2_GetN()` `LL_RCC_PLL2_SetN()`
PLL2DIVR1	DIVP	`LL_RCC_PLL2_GetP()` `LL_RCC_PLL2_SetP()`
PLL2DIVR1	DIVQ	`LL_RCC_PLL2_GetQ()` `LL_RCC_PLL2_SetQ()`
PLL2DIVR1	DIVR	`LL_RCC_PLL2_GetR()` `LL_RCC_PLL2_SetR()`
PLL2DIVR2	DIVS	`LL_RCC_PLL2_GetS()` `LL_RCC_PLL2_SetS()`
PLL2DIVR2	DIVT	`LL_RCC_PLL2_GetT()` `LL_RCC_PLL2_SetT()`
PLL2FRACR	FRACN	`LL_RCC_PLL2_GetFRACN()` `LL_RCC_PLL2_SetFRACN()`
PLL2SSCGR	INCSTEP	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_GetSSCGIncrementStep()` `LL_RCC_PLL2_SetSSCGIncrementStep()`
PLL2SSCGR	MODPER	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_GetSSCGModulationPeriod()` `LL_RCC_PLL2_SetSSCGModulationPeriod()`
PLL2SSCGR	RPDFNDIS	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_DisableSSCGRPDFNDithering()` `LL_RCC_PLL2_EnableSSCGRPDFNDithering()` `LL_RCC_PLL2_GetSSCGDithering()` `LL_RCC_PLL2_IsEnabledSSCGRPDFNDithering()`
PLL2SSCGR	SPREADSEL	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_GetSSCGSpreadSelection()` `LL_RCC_PLL2_SetSSCGSpreadSelection()`
PLL2SSCGR	TPDFNDIS	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_DisableSSCGTPDFNDithering()` `LL_RCC_PLL2_EnableSSCGTPDFNDithering()` `LL_RCC_PLL2_GetSSCGDithering()` `LL_RCC_PLL2_IsEnabledSSCGTPDFNDithering()`
PLL3DIVR1	DIVN	`LL_RCC_PLL3_GetN()` `LL_RCC_PLL3_SetN()`
PLL3DIVR1	DIVP	`LL_RCC_PLL3_GetP()` `LL_RCC_PLL3_SetP()`
PLL3DIVR1	DIVQ	`LL_RCC_PLL3_GetQ()` `LL_RCC_PLL3_SetQ()`
PLL3DIVR1	DIVR	`LL_RCC_PLL3_GetR()` `LL_RCC_PLL3_SetR()`
PLL3DIVR2	DIVS	`LL_RCC_PLL3_GetS()` `LL_RCC_PLL3_SetS()`
PLL3FRACR	FRACN	`LL_RCC_PLL3_GetFRACN()` `LL_RCC_PLL3_SetFRACN()`
PLL3SSCGR	INCSTEP	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_GetSSCGIncrementStep()` `LL_RCC_PLL3_SetSSCGIncrementStep()`
PLL3SSCGR	MODPER	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_GetSSCGModulationPeriod()` `LL_RCC_PLL3_SetSSCGModulationPeriod()`
PLL3SSCGR	RPDFNDIS	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_DisableSSCGRPDFNDithering()` `LL_RCC_PLL3_EnableSSCGRPDFNDithering()` `LL_RCC_PLL3_GetSSCGDithering()` `LL_RCC_PLL3_IsEnabledSSCGRPDFNDithering()`
PLL3SSCGR	SPREADSEL	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_GetSSCGSpreadSelection()` `LL_RCC_PLL3_SetSSCGSpreadSelection()`
PLL3SSCGR	TPDFNDIS	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_DisableSSCGTPDFNDithering()` `LL_RCC_PLL3_EnableSSCGTPDFNDithering()` `LL_RCC_PLL3_GetSSCGDithering()` `LL_RCC_PLL3_IsEnabledSSCGTPDFNDithering()`
PLLCFGR	PLL1FRACEN	`LL_RCC_PLL1_DisableFRACN()` `LL_RCC_PLL1_EnableFRACN()` `LL_RCC_PLL1_IsEnabledFRACN()`
PLLCFGR	PLL1PEN	`LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_DisableOutputP()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_EnableOutputP()` `LL_RCC_PLL1_GetOutput()` `LL_RCC_PLL1_IsEnabledOutputP()` `LL_RCC_PLL1_IsOutputEnabled()`
PLLCFGR	PLL1QEN	`LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_DisableOutputQ()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_EnableOutputQ()` `LL_RCC_PLL1_GetOutput()` `LL_RCC_PLL1_IsEnabledOutputQ()` `LL_RCC_PLL1_IsOutputEnabled()`
PLLCFGR	PLL1RGE	`LL_RCC_PLL1_GetInputRange()` `LL_RCC_PLL1_SetInputRange()`
PLLCFGR	PLL1SEN	`LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_DisableOutputS()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_EnableOutputS()` `LL_RCC_PLL1_GetOutput()` `LL_RCC_PLL1_IsEnabledOutputS()` `LL_RCC_PLL1_IsOutputEnabled()`
PLLCFGR	PLL1SSCGEN	`LL_RCC_PLL1_DisableSSCG()` `LL_RCC_PLL1_EnableSSCG()` `LL_RCC_PLL1_IsEnabledSSCG()`
PLLCFGR	PLL1VCOSEL	`LL_RCC_PLL1_GetVCORange()` `LL_RCC_PLL1_SetVCORange()`
PLLCFGR	PLL2FRACLEN	`LL_RCC_PLL2_DisableFRACN()` `LL_RCC_PLL2_EnableFRACN()` `LL_RCC_PLL2_IsEnabledFRACN()`
PLLCFGR	PLL2PEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputP()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputP()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputP()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2QEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputQ()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputQ()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputQ()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2REN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputR()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputR()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputR()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2RGE	`LL_RCC_PLL2_GetInputRange()` `LL_RCC_PLL2_SetInputRange()`
PLLCFGR	PLL2SEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputS()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputS()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputS()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2SSCGEN	`LL_RCC_PLL2_DisableSSCG()` `LL_RCC_PLL2_EnableSSCG()` `LL_RCC_PLL2_IsEnabledSSCG()`
PLLCFGR	PLL2TEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputT()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputT()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputT()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2VCOSEL	`LL_RCC_PLL2_GetVCORange()` `LL_RCC_PLL2_SetVCORange()`
PLLCFGR	PLL3FRACEN	`LL_RCC_PLL3_DisableFRACN()` `LL_RCC_PLL3_EnableFRACN()` `LL_RCC_PLL3_IsEnabledFRACN()`
PLLCFGR	PLL3PEN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputP()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputP()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputP()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3QEN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputQ()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputQ()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputQ()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3REN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputR()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputR()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputR()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3RGE	`LL_RCC_PLL3_GetInputRange()` `LL_RCC_PLL3_SetInputRange()`
PLLCFGR	PLL3SEN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputS()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputS()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputS()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3SSCGEN	`LL_RCC_PLL3_DisableSSCG()` `LL_RCC_PLL3_EnableSSCG()` `LL_RCC_PLL3_IsEnabledSSCG()`
PLLCFGR	PLL3VCOSEL	`LL_RCC_PLL3_GetVCORange()` `LL_RCC_PLL3_SetVCORange()`
PLLCKSELR	DIVM1	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetM()` `LL_RCC_PLL1_SetM()`
PLLCKSELR	DIVM2	`LL_RCC_PLL2_GetM()` `LL_RCC_PLL2_SetM()`
PLLCKSELR	DIVM3	`LL_RCC_PLL3_GetM()` `LL_RCC_PLL3_SetM()`
PLLCKSELR	PLLSRC	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL_GetSource()` `LL_RCC_PLL_SetSource()`
RCC_PLLCFGR	PLL1PEN	`LL_RCC_PLL1_DisableOutput_SYS()` `LL_RCC_PLL1_EnableOutput_SYS()` `LL_RCC_PLL1_IsEnabledOutput_SYS()`
RSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
RSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
RSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
RSR	OBLRSTF	`LL_RCC_IsActiveFlag_OBLRST()`
RSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
RSR	PORRSTF	`LL_RCC_IsActiveFlag_PORRST()`
RSR	RMVF	`LL_RCC_ClearResetFlags()`
RSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
RSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`

Register	Bit	Function
APBCFGR	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
APBCFGR	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
APBCFGR	PPRE4	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB4Prescaler()` `LL_RCC_SetAPB4Prescaler()`
BDCR	LSEBYP	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()` `LL_RCC_LSE_IsBypassed()`
BDCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
BDCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
BDCR	LSECSSRA	`LL_RCC_LSE_ResetRearmCSS()` `LL_RCC_LSE_SetRearmCSS()`
BDCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
BDCR	LSEEXT	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_GetExternalClockType()` `LL_RCC_LSE_SetExternalClockType()`
BDCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
BDCR	LSERDY	`LL_RCC_LSE_IsReady()`
BDCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
BDCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`
BDCR	VSWRST	`LL_RCC_ForceBackupDomainReset()` `LL_RCC_ReleaseBackupDomainReset()`
BMCFGR	BMPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetBMPrescaler()` `LL_RCC_SetBMPrescaler()`
CCIPR1	ADCDIV	`LL_RCC_GetADCPrescaler()` `LL_RCC_SetADCPrescaler()`
CCIPR1	ADCSEL	`LL_RCC_GetADCClockSource()` `LL_RCC_SetADCClockSource()`
CCIPR1	ADF1SEL	`LL_RCC_GetADFClockSource()` `LL_RCC_SetADFClockSource()`
CCIPR1	CKPERSEL	`LL_RCC_PERCLK_GetSource()` `LL_RCC_PERCLK_SetSource()`
CCIPR1	FMCSEL	`LL_RCC_GetFMCClockSource()` `LL_RCC_SetFMCClockSource()`
CCIPR1	OTGFSSEL	`LL_RCC_GetUSBOTGFSClockSource()` `LL_RCC_SetUSBOTGFSClockSource()`
CCIPR1	SDMMC1SEL	`LL_RCC_GetSDMMCClockSource()` `LL_RCC_SetSDMMCClockSource()`
CCIPR1	XSPI1SEL	`LL_RCC_GetXSPIClockSource()` `LL_RCC_SetXSPIClockSource()`
CCIPR2		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR2	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR2	I2C123SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I3C1SEL	`LL_RCC_GetI3CClockSource()` `LL_RCC_SetI3CClockSource()`
CCIPR2	LPTIM1SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR2	SPI23SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR2	UART234578SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR3		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR3	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR3	SPI45SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR3	USART16910SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR4		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR4	DAC1SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	DAC1SHSEL	`LL_RCC_GetDACSHClockSource()` `LL_RCC_SetDACSHClockSource()`
CCIPR4	DAC2SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	DAC3SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	DAC4SEL	`LL_RCC_GetDACClockSource()` `LL_RCC_SetDACClockSource()`
CCIPR4	LPTIM23SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR4	LPTIM45SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR4	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()` `LL_RCC_SetLPUARTClockSource()`
CCIPR4	SPI6SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR5	ADCDIV	`LL_RCC_ConfigADC()`
CDCFGR	CPRE	`LL_RCC_GetSysPrescaler()` `LL_RCC_SetSysPrescaler()`
CFGR	MCO1PRE	`LL_RCC_ConfigMCO()`
CFGR	MCO1SEL	`LL_RCC_ConfigMCO()`
CFGR	MCO2PRE	`LL_RCC_ConfigMCO()`
CFGR	MCO2SEL	`LL_RCC_ConfigMCO()`
CFGR	RTCPRE	`LL_RCC_GetRTC_HSEPrescaler()` `LL_RCC_SetRTC_HSEPrescaler()`
CFGR	STOPKERWUCK	`LL_RCC_GetKerClkAfterWakeFromStop()` `LL_RCC_SetKerClkAfterWakeFromStop()`
CFGR	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR	SW	`LL_RCC_SetSysClkSource()`
CFGR	SWS	`LL_RCC_GetSysClkSource()`
CICR	CSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_CSIRDY()`
CICR	HSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSI48RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSI48RDY()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	LSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSECSS()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	PLL1RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL1RDY()`
CICR	PLL2RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL2RDY()`
CICR	PLL3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PLL3RDY()`
CIER	CSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_CSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_CSIRDY()` `LL_RCC_IsEnabledIT_CSIRDY()`
CIER	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSI48RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSI48RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSI48RDY()` `LL_RCC_IsEnabledIT_HSI48RDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSECSSIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSECSS()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSECSS()` `LL_RCC_IsEnabledIT_LSECSS()`
CIER	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	PLL1RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PLL1RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PLL1RDY()` `LL_RCC_IsEnabledIT_PLL1RDY()`
CIER	PLL2RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PLL2RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PLL2RDY()` `LL_RCC_IsEnabledIT_PLL2RDY()`
CIER	PLL3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PLL3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PLL3RDY()` `LL_RCC_IsEnabledIT_PLL3RDY()`
CIFR	CSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_CSIRDY()`
CIFR	HSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSI48RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSI48RDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSECSS()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	PLL1RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PLL1RDY()`
CIFR	PLL2RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PLL2RDY()`
CIFR	PLL3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PLL3RDY()`
CKPROTR	FMCCKP	`LL_RCC_DisableFMCClockProtection()` `LL_RCC_EnableFMCClockProtection()` `LL_RCC_IsEnabledFMCClockProtection()`
CKPROTR	FMCSWP	`LL_RCC_GetFMCSwitchPosition()`
CKPROTR	XSPICKP	`LL_RCC_DisableXSPIClockProtection()` `LL_RCC_EnableXSPIClockProtection()` `LL_RCC_IsEnabledXSPIClockProtection()`
CKPROTR	XSPISWP	`LL_RCC_GetXSPISwitchPosition()`
CR	CSIKERON	`LL_RCC_CSI_DisableInStopMode()` `LL_RCC_CSI_EnableInStopMode()` `LL_RCC_CSI_IsEnabledInStopMode()`
CR	CSION	`LL_RCC_CSI_Disable()` `LL_RCC_CSI_Enable()` `LL_RCC_CSI_IsEnabled()`
CR	CSIRDY	`LL_RCC_CSI_IsReady()`
CR	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR	HSECSSON	`LL_RCC_HSE_EnableCSS()`
CR	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetExternalClockType()` `LL_RCC_HSE_SetExternalClockType()`
CR	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR	HSERDY	`LL_RCC_HSE_IsReady()`
CR	HSI48ON	`LL_RCC_HSI48_Disable()` `LL_RCC_HSI48_Enable()` `LL_RCC_HSI48_IsEnabled()`
CR	HSI48RDY	`LL_RCC_HSI48_IsReady()`
CR	HSIDIV	`LL_RCC_HSI_GetDivider()` `LL_RCC_HSI_SetDivider()`
CR	HSIDIVF	`LL_RCC_HSI_IsDividerReady()`
CR	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR	HSION	`LL_RCC_HSI_Disable()` `LL_RCC_HSI_Enable()` `LL_RCC_HSI_IsEnabled()`
CR	HSIRDY	`LL_RCC_HSI_IsReady()`
CR	PLL1ON	`LL_RCC_PLL1_Disable()` `LL_RCC_PLL1_Enable()`
CR	PLL1RDY	`LL_RCC_PLL1_IsReady()`
CR	PLL2ON	`LL_RCC_PLL2_Disable()` `LL_RCC_PLL2_Enable()`
CR	PLL2RDY	`LL_RCC_PLL2_IsReady()`
CR	PLL3ON	`LL_RCC_PLL3_Disable()` `LL_RCC_PLL3_Enable()`
CR	PLL3RDY	`LL_RCC_PLL3_IsReady()`
CRRCR	HSI48CAL	`LL_RCC_HSI48_GetCalibration()`
CSICFGR	CSICAL	`LL_RCC_CSI_GetCalibration()`
CSICFGR	CSITRIM	`LL_RCC_CSI_GetCalibTrimming()` `LL_RCC_CSI_SetCalibTrimming()`
CSR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
CSR	LSIRDY	`LL_RCC_LSI_IsReady()`
HSICFGR	HSICAL	`LL_RCC_HSI_GetCalibration()`
HSICFGR	HSITRIM	`LL_RCC_HSI_GetCalibTrimming()` `LL_RCC_HSI_SetCalibTrimming()`
PLL1DIVR1	DIVN	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetN()` `LL_RCC_PLL1_SetN()`
PLL1DIVR1	DIVP	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetP()` `LL_RCC_PLL1_SetP()`
PLL1DIVR1	DIVQ	`LL_RCC_PLL1_GetQ()` `LL_RCC_PLL1_SetQ()`
PLL1DIVR2	DIVS	`LL_RCC_PLL1_GetS()` `LL_RCC_PLL1_SetS()`
PLL1FRACR	FRACN	`LL_RCC_PLL1_GetFRACN()`
PLL1SSCGR	INCSTEP	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_GetSSCGIncrementStep()` `LL_RCC_PLL1_SetSSCGIncrementStep()`
PLL1SSCGR	MODPER	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_GetSSCGModulationPeriod()` `LL_RCC_PLL1_SetSSCGModulationPeriod()`
PLL1SSCGR	RPDFNDIS	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_DisableSSCGRPDFNDithering()` `LL_RCC_PLL1_EnableSSCGRPDFNDithering()` `LL_RCC_PLL1_GetSSCGDithering()` `LL_RCC_PLL1_IsEnabledSSCGRPDFNDithering()`
PLL1SSCGR	SPREADSEL	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_GetSSCGSpreadSelection()` `LL_RCC_PLL1_SetSSCGSpreadSelection()`
PLL1SSCGR	TPDFNDIS	`LL_RCC_PLL1_ConfigSSCG()` `LL_RCC_PLL1_DisableSSCGTPDFNDithering()` `LL_RCC_PLL1_EnableSSCGTPDFNDithering()` `LL_RCC_PLL1_GetSSCGDithering()` `LL_RCC_PLL1_IsEnabledSSCGTPDFNDithering()`
PLL2DIVR1	DIVN	`LL_RCC_PLL2_GetN()` `LL_RCC_PLL2_SetN()`
PLL2DIVR1	DIVP	`LL_RCC_PLL2_GetP()` `LL_RCC_PLL2_SetP()`
PLL2DIVR1	DIVQ	`LL_RCC_PLL2_GetQ()` `LL_RCC_PLL2_SetQ()`
PLL2DIVR1	DIVR	`LL_RCC_PLL2_GetR()` `LL_RCC_PLL2_SetR()`
PLL2DIVR2	DIVS	`LL_RCC_PLL2_GetS()` `LL_RCC_PLL2_SetS()`
PLL2DIVR2	DIVT	`LL_RCC_PLL2_GetT()` `LL_RCC_PLL2_SetT()`
PLL2FRACR	FRACN	`LL_RCC_PLL2_GetFRACN()` `LL_RCC_PLL2_SetFRACN()`
PLL2SSCGR	INCSTEP	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_GetSSCGIncrementStep()` `LL_RCC_PLL2_SetSSCGIncrementStep()`
PLL2SSCGR	MODPER	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_GetSSCGModulationPeriod()` `LL_RCC_PLL2_SetSSCGModulationPeriod()`
PLL2SSCGR	RPDFNDIS	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_DisableSSCGRPDFNDithering()` `LL_RCC_PLL2_EnableSSCGRPDFNDithering()` `LL_RCC_PLL2_GetSSCGDithering()` `LL_RCC_PLL2_IsEnabledSSCGRPDFNDithering()`
PLL2SSCGR	SPREADSEL	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_GetSSCGSpreadSelection()` `LL_RCC_PLL2_SetSSCGSpreadSelection()`
PLL2SSCGR	TPDFNDIS	`LL_RCC_PLL2_ConfigSSCG()` `LL_RCC_PLL2_DisableSSCGTPDFNDithering()` `LL_RCC_PLL2_EnableSSCGTPDFNDithering()` `LL_RCC_PLL2_GetSSCGDithering()` `LL_RCC_PLL2_IsEnabledSSCGTPDFNDithering()`
PLL3DIVR1	DIVN	`LL_RCC_PLL3_GetN()` `LL_RCC_PLL3_SetN()`
PLL3DIVR1	DIVP	`LL_RCC_PLL3_GetP()` `LL_RCC_PLL3_SetP()`
PLL3DIVR1	DIVQ	`LL_RCC_PLL3_GetQ()` `LL_RCC_PLL3_SetQ()`
PLL3DIVR1	DIVR	`LL_RCC_PLL3_GetR()` `LL_RCC_PLL3_SetR()`
PLL3DIVR2	DIVS	`LL_RCC_PLL3_GetS()` `LL_RCC_PLL3_SetS()`
PLL3FRACR	FRACN	`LL_RCC_PLL3_GetFRACN()` `LL_RCC_PLL3_SetFRACN()`
PLL3SSCGR	INCSTEP	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_GetSSCGIncrementStep()` `LL_RCC_PLL3_SetSSCGIncrementStep()`
PLL3SSCGR	MODPER	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_GetSSCGModulationPeriod()` `LL_RCC_PLL3_SetSSCGModulationPeriod()`
PLL3SSCGR	RPDFNDIS	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_DisableSSCGRPDFNDithering()` `LL_RCC_PLL3_EnableSSCGRPDFNDithering()` `LL_RCC_PLL3_GetSSCGDithering()` `LL_RCC_PLL3_IsEnabledSSCGRPDFNDithering()`
PLL3SSCGR	SPREADSEL	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_GetSSCGSpreadSelection()` `LL_RCC_PLL3_SetSSCGSpreadSelection()`
PLL3SSCGR	TPDFNDIS	`LL_RCC_PLL3_ConfigSSCG()` `LL_RCC_PLL3_DisableSSCGTPDFNDithering()` `LL_RCC_PLL3_EnableSSCGTPDFNDithering()` `LL_RCC_PLL3_GetSSCGDithering()` `LL_RCC_PLL3_IsEnabledSSCGTPDFNDithering()`
PLLCFGR	PLL1FRACEN	`LL_RCC_PLL1_DisableFRACN()` `LL_RCC_PLL1_EnableFRACN()` `LL_RCC_PLL1_IsEnabledFRACN()`
PLLCFGR	PLL1PEN	`LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_DisableOutputP()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_EnableOutputP()` `LL_RCC_PLL1_GetOutput()` `LL_RCC_PLL1_IsEnabledOutputP()` `LL_RCC_PLL1_IsOutputEnabled()`
PLLCFGR	PLL1QEN	`LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_DisableOutputQ()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_EnableOutputQ()` `LL_RCC_PLL1_GetOutput()` `LL_RCC_PLL1_IsEnabledOutputQ()` `LL_RCC_PLL1_IsOutputEnabled()`
PLLCFGR	PLL1RGE	`LL_RCC_PLL1_GetInputRange()` `LL_RCC_PLL1_SetInputRange()`
PLLCFGR	PLL1SEN	`LL_RCC_PLL1_DisableOutput()` `LL_RCC_PLL1_DisableOutputS()` `LL_RCC_PLL1_EnableOutput()` `LL_RCC_PLL1_EnableOutputS()` `LL_RCC_PLL1_GetOutput()` `LL_RCC_PLL1_IsEnabledOutputS()` `LL_RCC_PLL1_IsOutputEnabled()`
PLLCFGR	PLL1SSCGEN	`LL_RCC_PLL1_DisableSSCG()` `LL_RCC_PLL1_EnableSSCG()` `LL_RCC_PLL1_IsEnabledSSCG()`
PLLCFGR	PLL1VCOSEL	`LL_RCC_PLL1_GetVCORange()` `LL_RCC_PLL1_SetVCORange()`
PLLCFGR	PLL2FRACLEN	`LL_RCC_PLL2_DisableFRACN()` `LL_RCC_PLL2_EnableFRACN()` `LL_RCC_PLL2_IsEnabledFRACN()`
PLLCFGR	PLL2PEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputP()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputP()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputP()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2QEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputQ()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputQ()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputQ()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2REN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputR()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputR()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputR()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2RGE	`LL_RCC_PLL2_GetInputRange()` `LL_RCC_PLL2_SetInputRange()`
PLLCFGR	PLL2SEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputS()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputS()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputS()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2SSCGEN	`LL_RCC_PLL2_DisableSSCG()` `LL_RCC_PLL2_EnableSSCG()` `LL_RCC_PLL2_IsEnabledSSCG()`
PLLCFGR	PLL2TEN	`LL_RCC_PLL2_DisableOutput()` `LL_RCC_PLL2_DisableOutputT()` `LL_RCC_PLL2_EnableOutput()` `LL_RCC_PLL2_EnableOutputT()` `LL_RCC_PLL2_GetOutput()` `LL_RCC_PLL2_IsEnabledOutputT()` `LL_RCC_PLL2_IsOutputEnabled()`
PLLCFGR	PLL2VCOSEL	`LL_RCC_PLL2_GetVCORange()` `LL_RCC_PLL2_SetVCORange()`
PLLCFGR	PLL3FRACEN	`LL_RCC_PLL3_DisableFRACN()` `LL_RCC_PLL3_EnableFRACN()` `LL_RCC_PLL3_IsEnabledFRACN()`
PLLCFGR	PLL3PEN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputP()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputP()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputP()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3QEN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputQ()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputQ()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputQ()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3REN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputR()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputR()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputR()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3RGE	`LL_RCC_PLL3_GetInputRange()` `LL_RCC_PLL3_SetInputRange()`
PLLCFGR	PLL3SEN	`LL_RCC_PLL3_DisableOutput()` `LL_RCC_PLL3_DisableOutputS()` `LL_RCC_PLL3_EnableOutput()` `LL_RCC_PLL3_EnableOutputS()` `LL_RCC_PLL3_GetOutput()` `LL_RCC_PLL3_IsEnabledOutputS()` `LL_RCC_PLL3_IsOutputEnabled()`
PLLCFGR	PLL3SSCGEN	`LL_RCC_PLL3_DisableSSCG()` `LL_RCC_PLL3_EnableSSCG()` `LL_RCC_PLL3_IsEnabledSSCG()`
PLLCFGR	PLL3VCOSEL	`LL_RCC_PLL3_GetVCORange()` `LL_RCC_PLL3_SetVCORange()`
PLLCKSELR	DIVM1	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL1_GetM()` `LL_RCC_PLL1_SetM()`
PLLCKSELR	DIVM2	`LL_RCC_PLL2_GetM()` `LL_RCC_PLL2_SetM()`
PLLCKSELR	DIVM3	`LL_RCC_PLL3_GetM()` `LL_RCC_PLL3_SetM()`
PLLCKSELR	PLLSRC	`LL_RCC_PLL1_ConfigDomain_SYS()` `LL_RCC_PLL_GetSource()` `LL_RCC_PLL_SetSource()`
RCC_PLLCFGR	PLL1PEN	`LL_RCC_PLL1_DisableOutput_SYS()` `LL_RCC_PLL1_EnableOutput_SYS()` `LL_RCC_PLL1_IsEnabledOutput_SYS()`
RSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
RSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
RSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
RSR	OBLRSTF	`LL_RCC_IsActiveFlag_OBLRST()`
RSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
RSR	PORRSTF	`LL_RCC_IsActiveFlag_PORRST()`
RSR	RMVF	`LL_RCC_ClearResetFlags()`
RSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
RSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`