HAL ICACHE How to Use

group ICACHE_How_To_Use

ICACHE Introduction

The Instruction Cache (ICACHE) is introduced on the C-AHB code bus of the Cortex-M33 processor to improve performance when fetching instructions and data from both internal and external memories. Some specific features like dual master ports, hit-under-miss and critical-word-first refill policy, allows near-zero-wait-state performance in most use cases.

Main features

The main features of ICACHE are described below:

• Bus interface

  • one 32-bit AHB slave port, the execution port (input from Cortex-M33 C-AHB code interface)

  • two AHB master ports: master1 and master2 ports (outputs to Fast and Slow buses of main AHB bus matrix, respectively)

  • one 32-bit AHB slave port for control (input from AHB peripherals interconnect, for ICACHE register access)

• Cache access

  • 0 wait-state on hits

  • Hit-under-miss capability: ability to serve processor requests (access to cached data) during an ongoing line refill due to a previous cache miss

  • Dual master access: feature used to decouple the traffic according to targeted memory. For example, the ICACHE assigns fast traffic (addressing flash and SRAM memories) to the AHB master1 port and slow traffic (addressing external memories) to the AHB master2 port, thus preventing processor stalls on lines refills from external memories. This allows ISR (interrupt service routine) fetching on internal flash memory to take place in parallel with a cache line refill from external memories.

  • Minimal impact on interrupt latency, thanks to dual master

  • Optimal cache line refill thanks to WRAPw bursts of the size of the cache line (32-bit word size, w, aligned on cache line size)

  • n-way set-associative default configuration with the possibility to configure as 1-way, that is, direct-mapped

• Memory address remap

  • Possibility to remap input addresses falling into up to four memory regions (used to remap aliased code in SRAM memories to the Code region, for execution from C-AHB code interface).

• Replacement and refill

  • pLRU-t replacement policy (pseudo-least-recently-used, based on a binary tree), algorithm with the best complexity/performance balance

  • Critical-word-first refill policy, minimizing processor stalls

  • Possibility to configure the burst type of AHB memory transaction for remapped regions: INCRw or WRAPw (size w aligned on cache line size)

• Performance counters ICACHE implements two performance counters:

  • Hit monitor counter (32-bit)

  • Miss monitor counter (16-bit)

• Error management

  • Possibility to detect an unexpected cacheable write access, to flag an error and optionally to raise an interrupt

• Maintenance operation

  • Cache invalidate: full cache invalidation, fast command, non-interruptible.

How to use the HAL ICACHE driver

Use the HAL ICACHE driver as follows:

Main use

• Initialize the ICACHE according to the associated handle with HAL_ICACHE_Init().

• Set the configuration of the ICACHE to choose the associativity mode with the HAL_ICACHE_SetAssociativityMode() function (default is 2-ways).

• Enable and disable up to four regions to remap input addresses from external memories to the internal Code region for execution with the HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() functions.

• Then start the ICACHE driver with HAL_ICACHE_Start(). Enable error interrupt detection to receive callbacks if cache function errors occur.

• Execute the ICACHE maintenance operations if necessary:

  • Use HAL_ICACHE_Invalidate() to invalidate the full cache content:

    • Cache content is lost and reloaded when needed.

    • Used for complete invalidation of the ICACHE if required.

    • Blocking call until the operation is done.

Monitoring performance

• Use the performance monitoring Hit and Miss counters as follows: HAL_ICACHE_EnableMonitors() and HAL_ICACHE_DisableMonitors() respectively enable and disable any monitors. To retrieve the counter values, use the HAL_ICACHE_GetMonitorHitValue() or HAL_ICACHE_GetMonitorMissValue() functions. The HAL_ICACHE_ResetMonitors() function allows you to clear any monitor values.

Interrupt Mode

• The ICACHE provides two interrupt sources:

  • The error interrupt.

  • The invalidate completion interrupt.

• For each interrupt, there is a corresponding callback launched in the HAL_ICACHE_IRQHandler() function.

• In case of an interrupt, depending on which callback registration method is used, it triggers either the weak callback or the registered one.

• Error:

  • Override weak definition for following callbacks:

    • HAL_ICACHE_ErrorCallback()

  • Or use register callbacks (USE_HAL_ICACHE_REGISTER_CALLBACKS = 1):

    • HAL_ICACHE_RegisterErrorCallback()

  • Start the ICACHE driver with HAL_ICACHE_Start(hicache, HAL_ICACHE_IT_ERROR) as explained above.

• Maintenance operation:

  • Override weak definition for following callbacks:

    • HAL_ICACHE_InvalidateCompleteCallback()

  • Or use register callbacks (USE_HAL_ICACHE_REGISTER_CALLBACKS = 1):

    • HAL_ICACHE_RegisterInvalidateCompleteCallback()

  • Launch a maintenance operation with interrupt: HAL_ICACHE_Invalidate_IT().

HAL ICACHE Driver State

• Use HAL_ICACHE_GetState() to return the HAL ICACHE state.