Reference Manual to LL API cross reference ¶

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for RCC registers

Register	Bit	Function
CCIPR1		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR1	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR1	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()` `LL_RCC_SetLPUARTClockSource()`
CCIPR1	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI2SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI3SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	UART4SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART5SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART7SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	USART1SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART2SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART3SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART6SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR2		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR2	ADCDACPRE	`LL_RCC_ConfigADCDAC()` `LL_RCC_GetConfigADCDAC()` `LL_RCC_SetADCDACPrescaler()`
CCIPR2	ADCDACSEL	`LL_RCC_ConfigADCDAC()` `LL_RCC_GetADCDACClockSource()` `LL_RCC_GetADCDACPrescaler()` `LL_RCC_GetConfigADCDAC()` `LL_RCC_SetADCDACClockSource()`
CCIPR2	CK48SEL	`LL_RCC_GetCKClockSource()` `LL_RCC_SetCK48ClockSource()`
CCIPR2	DACSEL	`LL_RCC_GetDACSHClockSource()` `LL_RCC_SetDACSHClockSource()`
CCIPR2	I2C1SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I2C2SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I3C1SEL	`LL_RCC_GetI3CClockSource()` `LL_RCC_SetI3CClockSource()`
CCIPR2	LPTIM1SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR2	SYSTICKSEL	`LL_RCC_GetSystickClockSource()` `LL_RCC_SetSystickClockSource()`
CCIPR3		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CFGR1	MCO1PRE	`LL_RCC_ConfigMCO()`
CFGR1	MCO1SEL	`LL_RCC_ConfigMCO()`
CFGR1	MCO2PRE	`LL_RCC_ConfigMCO()`
CFGR1	MCO2SEL	`LL_RCC_ConfigMCO()`
CFGR1	RTCPRE	`LL_RCC_GetRTC_HSEPrescaler()` `LL_RCC_SetRTC_HSEPrescaler()`
CFGR1	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR1	SW	`LL_RCC_SetSysClkSource()`
CFGR1	SWS	`LL_RCC_GetSysClkSource()`
CFGR2	HPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAHBPrescaler()` `LL_RCC_SetAHBPrescaler()`
CFGR2	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
CFGR2	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
CFGR2	PPRE3	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB3Prescaler()` `LL_RCC_SetAPB3Prescaler()`
CICR	HSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSIDIV3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIDIV3RDY()`
CICR	HSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIKRDY()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	LSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSECSS()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	PSIDIV3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIDIV3RDY()`
CICR	PSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIKRDY()`
CICR	PSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIRDY()`
CIER	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSIDIV3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIDIV3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIDIV3RDY()` `LL_RCC_IsEnabledIT_HSIDIV3RDY()`
CIER	HSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIKRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIKRDY()` `LL_RCC_IsEnabledIT_HSIKRDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	PSIDIV3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIDIV3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIDIV3RDY()` `LL_RCC_IsEnabledIT_PSIDIV3RDY()`
CIER	PSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIKRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIKRDY()` `LL_RCC_IsEnabledIT_PSIKRDY()`
CIER	PSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIRDY()` `LL_RCC_IsEnabledIT_PSIRDY()`
CIFR	HSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSIDIV3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIDIV3RDY()`
CIFR	HSIKRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIKRDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSECSS()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	PSIDIV3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIDIV3RDY()`
CIFR	PSIKRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIKRDY()`
CIFR	PSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIRDY()`
CR1	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR1	HSECSSON	`LL_RCC_HSE_EnableCSS()`
CR1	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetClockMode()` `LL_RCC_HSE_SelectAnalogClock()` `LL_RCC_HSE_SelectDigitalClock()` `LL_RCC_HSE_SetClockMode()`
CR1	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR1	HSERDY	`LL_RCC_HSE_IsReady()`
CR1	HSIDIV3ON	`LL_RCC_HSIDIV3_Disable()` `LL_RCC_HSIDIV3_Enable()` `LL_RCC_HSIDIV3_IsEnabled()`
CR1	HSIDIV3RDY	`LL_RCC_HSIDIV3_IsReady()`
CR1	HSIK	`LL_RCC_HSIK_IsEnabled()`
CR1	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR1	HSIKON	`LL_RCC_HSIK_Disable()` `LL_RCC_HSIK_Enable()`
CR1	HSIKRDY	`LL_RCC_HSIK_IsReady()`
CR1	HSISON	`LL_RCC_HSIS_Disable()` `LL_RCC_HSIS_Enable()` `LL_RCC_HSIS_IsEnabled()`
CR1	HSISRDY	`LL_RCC_HSIS_IsReady()`
CR1	PSIDIV3ON	`LL_RCC_PSIDIV3_Disable()` `LL_RCC_PSIDIV3_Enable()` `LL_RCC_PSIDIV3_IsEnabled()`
CR1	PSIDIV3RDY	`LL_RCC_PSIDIV3_IsReady()`
CR1	PSIKERON	`LL_RCC_PSI_DisableInStopMode()` `LL_RCC_PSI_EnableInStopMode()` `LL_RCC_PSI_IsEnabledInStopMode()`
CR1	PSIKON	`LL_RCC_PSIK_Disable()` `LL_RCC_PSIK_Enable()` `LL_RCC_PSIK_IsEnabled()`
CR1	PSIKRDY	`LL_RCC_PSIK_IsReady()`
CR1	PSISON	`LL_RCC_PSIS_Disable()` `LL_RCC_PSIS_Enable()` `LL_RCC_PSIS_IsEnabled()`
CR1	PSISRDY	`LL_RCC_PSIS_IsReady()`
CR2	HSIKDIV	`LL_RCC_HSIK_GetDivider()` `LL_RCC_HSIK_SetDivider()`
CR2	PSIFREQ	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIFreqOutput()` `LL_RCC_SetPSIFreqOutput()`
CR2	PSIKDIV	`LL_RCC_PSIK_GetDivider()` `LL_RCC_PSIK_SetDivider()`
CR2	PSIREF	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIRef()` `LL_RCC_SetPSIRef()`
CR2	PSIREFSRC	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIClkSource()` `LL_RCC_SetPSIClkSource()`
RSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
RSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
RSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
RSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
RSR	RMVF	`LL_RCC_ForceClearResetFlags()` `LL_RCC_ReleaseClearResetFlags()`
RSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
RSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`
RTCCR	LSCOEN	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_Disable()` `LL_RCC_LSCO_Enable()`
RTCCR	LSCOSEL	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_GetSource()` `LL_RCC_LSCO_SetSource()`
RTCCR	LSEBYP	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()` `LL_RCC_LSE_IsBypassed()`
RTCCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
RTCCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
RTCCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
RTCCR	LSEEXT	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_GetClockMode()` `LL_RCC_LSE_SetClockMode()`
RTCCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
RTCCR	LSERDY	`LL_RCC_LSE_IsReady()`
RTCCR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
RTCCR	LSIRDY	`LL_RCC_LSI_IsReady()`
RTCCR	RTCDRST	`LL_RCC_ForceRTCDomainReset()` `LL_RCC_ReleaseRTCDomainReset()`
RTCCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
RTCCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`

Register	Bit	Function
CCIPR1		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR1	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR1	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()` `LL_RCC_SetLPUARTClockSource()`
CCIPR1	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI2SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI3SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	UART4SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART5SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART7SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	USART1SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART2SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART3SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART6SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR2		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR2	ADCDACPRE	`LL_RCC_ConfigADCDAC()` `LL_RCC_GetConfigADCDAC()` `LL_RCC_SetADCDACPrescaler()`
CCIPR2	ADCDACSEL	`LL_RCC_ConfigADCDAC()` `LL_RCC_GetADCDACClockSource()` `LL_RCC_GetADCDACPrescaler()` `LL_RCC_GetConfigADCDAC()` `LL_RCC_SetADCDACClockSource()`
CCIPR2	CK48SEL	`LL_RCC_GetCKClockSource()` `LL_RCC_SetCK48ClockSource()`
CCIPR2	DACSEL	`LL_RCC_GetDACSHClockSource()` `LL_RCC_SetDACSHClockSource()`
CCIPR2	I2C1SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I2C2SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I3C1SEL	`LL_RCC_GetI3CClockSource()` `LL_RCC_SetI3CClockSource()`
CCIPR2	LPTIM1SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR2	SYSTICKSEL	`LL_RCC_GetSystickClockSource()` `LL_RCC_SetSystickClockSource()`
CCIPR3		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR3	ETH1CLKDIV	`LL_RCC_ConfigETH1()` `LL_RCC_GetConfigETH1()` `LL_RCC_GetETH1Prescaler()`
CCIPR3	ETH1CLKDIVSEL	`LL_RCC_SetETH1Prescaler()`
CCIPR3	ETH1CLKSEL	`LL_RCC_ConfigETH1()` `LL_RCC_GetConfigETH1()` `LL_RCC_GetETH1ClockSource()` `LL_RCC_SetETH1ClockSource()`
CCIPR3	ETH1PTPCLKSEL	`LL_RCC_ConfigETH1PTP()` `LL_RCC_GetConfigETH1PTP()` `LL_RCC_GetETH1ClockSource()` `LL_RCC_SetETH1ClockSource()`
CCIPR3	ETH1PTPDIV	`LL_RCC_ConfigETH1PTP()` `LL_RCC_GetConfigETH1PTP()` `LL_RCC_GetETH1PTPPrescaler()` `LL_RCC_SetETH1PTPPrescaler()`
CCIPR3	ETH1REFCLKSEL	`LL_RCC_GetETH1ClockSource()` `LL_RCC_SetETH1ClockSource()`
CCIPR3	XSPI1SEL	`LL_RCC_GetXSPIClockSource()`
CFGR1	MCO1PRE	`LL_RCC_ConfigMCO()`
CFGR1	MCO1SEL	`LL_RCC_ConfigMCO()`
CFGR1	MCO2PRE	`LL_RCC_ConfigMCO()`
CFGR1	MCO2SEL	`LL_RCC_ConfigMCO()`
CFGR1	RTCPRE	`LL_RCC_GetRTC_HSEPrescaler()` `LL_RCC_SetRTC_HSEPrescaler()`
CFGR1	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR1	SW	`LL_RCC_SetSysClkSource()`
CFGR1	SWS	`LL_RCC_GetSysClkSource()`
CFGR2	HPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAHBPrescaler()` `LL_RCC_SetAHBPrescaler()`
CFGR2	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
CFGR2	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
CFGR2	PPRE3	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB3Prescaler()` `LL_RCC_SetAPB3Prescaler()`
CICR	HSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSIDIV3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIDIV3RDY()`
CICR	HSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIKRDY()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	LSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSECSS()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	PSIDIV3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIDIV3RDY()`
CICR	PSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIKRDY()`
CICR	PSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIRDY()`
CIER	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSIDIV3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIDIV3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIDIV3RDY()` `LL_RCC_IsEnabledIT_HSIDIV3RDY()`
CIER	HSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIKRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIKRDY()` `LL_RCC_IsEnabledIT_HSIKRDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	PSIDIV3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIDIV3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIDIV3RDY()` `LL_RCC_IsEnabledIT_PSIDIV3RDY()`
CIER	PSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIKRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIKRDY()` `LL_RCC_IsEnabledIT_PSIKRDY()`
CIER	PSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIRDY()` `LL_RCC_IsEnabledIT_PSIRDY()`
CIFR	HSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSIDIV3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIDIV3RDY()`
CIFR	HSIKRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIKRDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSECSS()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	PSIDIV3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIDIV3RDY()`
CIFR	PSIKRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIKRDY()`
CIFR	PSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIRDY()`
CR1	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR1	HSECSSON	`LL_RCC_HSE_EnableCSS()`
CR1	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetClockMode()` `LL_RCC_HSE_SelectAnalogClock()` `LL_RCC_HSE_SelectDigitalClock()` `LL_RCC_HSE_SetClockMode()`
CR1	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR1	HSERDY	`LL_RCC_HSE_IsReady()`
CR1	HSIDIV3ON	`LL_RCC_HSIDIV3_Disable()` `LL_RCC_HSIDIV3_Enable()` `LL_RCC_HSIDIV3_IsEnabled()`
CR1	HSIDIV3RDY	`LL_RCC_HSIDIV3_IsReady()`
CR1	HSIK	`LL_RCC_HSIK_IsEnabled()`
CR1	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR1	HSIKON	`LL_RCC_HSIK_Disable()` `LL_RCC_HSIK_Enable()`
CR1	HSIKRDY	`LL_RCC_HSIK_IsReady()`
CR1	HSISON	`LL_RCC_HSIS_Disable()` `LL_RCC_HSIS_Enable()` `LL_RCC_HSIS_IsEnabled()`
CR1	HSISRDY	`LL_RCC_HSIS_IsReady()`
CR1	PSIDIV3ON	`LL_RCC_PSIDIV3_Disable()` `LL_RCC_PSIDIV3_Enable()` `LL_RCC_PSIDIV3_IsEnabled()`
CR1	PSIDIV3RDY	`LL_RCC_PSIDIV3_IsReady()`
CR1	PSIKERON	`LL_RCC_PSI_DisableInStopMode()` `LL_RCC_PSI_EnableInStopMode()` `LL_RCC_PSI_IsEnabledInStopMode()`
CR1	PSIKON	`LL_RCC_PSIK_Disable()` `LL_RCC_PSIK_Enable()` `LL_RCC_PSIK_IsEnabled()`
CR1	PSIKRDY	`LL_RCC_PSIK_IsReady()`
CR1	PSISON	`LL_RCC_PSIS_Disable()` `LL_RCC_PSIS_Enable()` `LL_RCC_PSIS_IsEnabled()`
CR1	PSISRDY	`LL_RCC_PSIS_IsReady()`
CR2	HSIKDIV	`LL_RCC_HSIK_GetDivider()` `LL_RCC_HSIK_SetDivider()`
CR2	PSIFREQ	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIFreqOutput()` `LL_RCC_SetPSIFreqOutput()`
CR2	PSIKDIV	`LL_RCC_PSIK_GetDivider()` `LL_RCC_PSIK_SetDivider()`
CR2	PSIREF	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIRef()` `LL_RCC_SetPSIRef()`
CR2	PSIREFSRC	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIClkSource()` `LL_RCC_SetPSIClkSource()`
RSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
RSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
RSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
RSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
RSR	RMVF	`LL_RCC_ForceClearResetFlags()` `LL_RCC_ReleaseClearResetFlags()`
RSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
RSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`
RTCCR	LSCOEN	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_Disable()` `LL_RCC_LSCO_Enable()`
RTCCR	LSCOSEL	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_GetSource()` `LL_RCC_LSCO_SetSource()`
RTCCR	LSEBYP	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()` `LL_RCC_LSE_IsBypassed()`
RTCCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
RTCCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
RTCCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
RTCCR	LSEEXT	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_GetClockMode()` `LL_RCC_LSE_SetClockMode()`
RTCCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
RTCCR	LSERDY	`LL_RCC_LSE_IsReady()`
RTCCR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
RTCCR	LSIRDY	`LL_RCC_LSI_IsReady()`
RTCCR	RTCDRST	`LL_RCC_ForceRTCDomainReset()` `LL_RCC_ReleaseRTCDomainReset()`
RTCCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
RTCCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`

Register	Bit	Function
CCIPR1		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR1	FDCANSEL	`LL_RCC_GetFDCANClockSource()` `LL_RCC_SetFDCANClockSource()`
CCIPR1	LPUART1SEL	`LL_RCC_GetLPUARTClockSource()` `LL_RCC_SetLPUARTClockSource()`
CCIPR1	SPI1SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI2SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	SPI3SEL	`LL_RCC_GetSPIClockSource()` `LL_RCC_SetSPIClockSource()`
CCIPR1	UART4SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART5SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	UART7SEL	`LL_RCC_GetUARTClockSource()` `LL_RCC_SetUARTClockSource()`
CCIPR1	USART1SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART2SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART3SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR1	USART6SEL	`LL_RCC_GetUSARTClockSource()` `LL_RCC_SetUSARTClockSource()`
CCIPR2		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CCIPR2	ADCDACPRE	`LL_RCC_ConfigADCDAC()` `LL_RCC_GetConfigADCDAC()` `LL_RCC_SetADCDACPrescaler()`
CCIPR2	ADCDACSEL	`LL_RCC_ConfigADCDAC()` `LL_RCC_GetADCDACClockSource()` `LL_RCC_GetADCDACPrescaler()` `LL_RCC_GetConfigADCDAC()` `LL_RCC_SetADCDACClockSource()`
CCIPR2	CK48SEL	`LL_RCC_GetCKClockSource()` `LL_RCC_SetCK48ClockSource()`
CCIPR2	DACSEL	`LL_RCC_GetDACSHClockSource()` `LL_RCC_SetDACSHClockSource()`
CCIPR2	I2C1SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I2C2SEL	`LL_RCC_GetI2CClockSource()` `LL_RCC_SetI2CClockSource()`
CCIPR2	I3C1SEL	`LL_RCC_GetI3CClockSource()` `LL_RCC_SetI3CClockSource()`
CCIPR2	LPTIM1SEL	`LL_RCC_GetLPTIMClockSource()` `LL_RCC_SetLPTIMClockSource()`
CCIPR2	SYSTICKSEL	`LL_RCC_GetSystickClockSource()` `LL_RCC_SetSystickClockSource()`
CCIPR3		`LL_RCC_GetClockSource()` `LL_RCC_SetClockSource()`
CFGR1	MCO1PRE	`LL_RCC_ConfigMCO()`
CFGR1	MCO1SEL	`LL_RCC_ConfigMCO()`
CFGR1	MCO2PRE	`LL_RCC_ConfigMCO()`
CFGR1	MCO2SEL	`LL_RCC_ConfigMCO()`
CFGR1	RTCPRE	`LL_RCC_GetRTC_HSEPrescaler()` `LL_RCC_SetRTC_HSEPrescaler()`
CFGR1	STOPWUCK	`LL_RCC_GetClkAfterWakeFromStop()` `LL_RCC_SetClkAfterWakeFromStop()`
CFGR1	SW	`LL_RCC_SetSysClkSource()`
CFGR1	SWS	`LL_RCC_GetSysClkSource()`
CFGR2	HPRE	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAHBPrescaler()` `LL_RCC_SetAHBPrescaler()`
CFGR2	PPRE1	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB1Prescaler()` `LL_RCC_SetAPB1Prescaler()`
CFGR2	PPRE2	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB2Prescaler()` `LL_RCC_SetAPB2Prescaler()`
CFGR2	PPRE3	`LL_RCC_ConfigBusClock()` `LL_RCC_GetAPB3Prescaler()` `LL_RCC_SetAPB3Prescaler()`
CICR	HSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSECSS()`
CICR	HSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSERDY()`
CICR	HSIDIV3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIDIV3RDY()`
CICR	HSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIKRDY()`
CICR	HSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_HSIRDY()`
CICR	LSECSSC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSECSS()`
CICR	LSERDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSERDY()`
CICR	LSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_LSIRDY()`
CICR	PSIDIV3RDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIDIV3RDY()`
CICR	PSIKRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIKRDY()`
CICR	PSIRDYC	`LL_RCC_ClearFlag()` `LL_RCC_ClearFlag_PSIRDY()`
CIER	HSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSERDY()` `LL_RCC_IsEnabledIT_HSERDY()`
CIER	HSIDIV3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIDIV3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIDIV3RDY()` `LL_RCC_IsEnabledIT_HSIDIV3RDY()`
CIER	HSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIKRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIKRDY()` `LL_RCC_IsEnabledIT_HSIKRDY()`
CIER	HSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_HSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_HSIRDY()` `LL_RCC_IsEnabledIT_HSIRDY()`
CIER	LSERDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSERDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSERDY()` `LL_RCC_IsEnabledIT_LSERDY()`
CIER	LSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_LSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_LSIRDY()` `LL_RCC_IsEnabledIT_LSIRDY()`
CIER	PSIDIV3RDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIDIV3RDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIDIV3RDY()` `LL_RCC_IsEnabledIT_PSIDIV3RDY()`
CIER	PSIKRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIKRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIKRDY()` `LL_RCC_IsEnabledIT_PSIKRDY()`
CIER	PSIRDYIE	`LL_RCC_DisableIT()` `LL_RCC_DisableIT_PSIRDY()` `LL_RCC_EnableIT()` `LL_RCC_EnableIT_PSIRDY()` `LL_RCC_IsEnabledIT_PSIRDY()`
CIFR	HSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSECSS()`
CIFR	HSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSERDY()`
CIFR	HSIDIV3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIDIV3RDY()`
CIFR	HSIKRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIKRDY()`
CIFR	HSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_HSIRDY()`
CIFR	LSECSSF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSECSS()`
CIFR	LSERDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSERDY()`
CIFR	LSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_LSIRDY()`
CIFR	PSIDIV3RDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIDIV3RDY()`
CIFR	PSIKRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIKRDY()`
CIFR	PSIRDYF	`LL_RCC_IsActiveFlag()` `LL_RCC_IsActiveFlag_PSIRDY()`
CR1	HSEBYP	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_DisableBypass()` `LL_RCC_HSE_EnableBypass()` `LL_RCC_HSE_IsBypassed()`
CR1	HSECSSON	`LL_RCC_HSE_EnableCSS()`
CR1	HSEEXT	`LL_RCC_HSE_ConfigBypass()` `LL_RCC_HSE_GetClockMode()` `LL_RCC_HSE_SelectAnalogClock()` `LL_RCC_HSE_SelectDigitalClock()` `LL_RCC_HSE_SetClockMode()`
CR1	HSEON	`LL_RCC_HSE_Disable()` `LL_RCC_HSE_Enable()` `LL_RCC_HSE_IsEnabled()`
CR1	HSERDY	`LL_RCC_HSE_IsReady()`
CR1	HSIDIV3ON	`LL_RCC_HSIDIV3_Disable()` `LL_RCC_HSIDIV3_Enable()` `LL_RCC_HSIDIV3_IsEnabled()`
CR1	HSIDIV3RDY	`LL_RCC_HSIDIV3_IsReady()`
CR1	HSIK	`LL_RCC_HSIK_IsEnabled()`
CR1	HSIKERON	`LL_RCC_HSI_DisableInStopMode()` `LL_RCC_HSI_EnableInStopMode()` `LL_RCC_HSI_IsEnabledInStopMode()`
CR1	HSIKON	`LL_RCC_HSIK_Disable()` `LL_RCC_HSIK_Enable()`
CR1	HSIKRDY	`LL_RCC_HSIK_IsReady()`
CR1	HSISON	`LL_RCC_HSIS_Disable()` `LL_RCC_HSIS_Enable()` `LL_RCC_HSIS_IsEnabled()`
CR1	HSISRDY	`LL_RCC_HSIS_IsReady()`
CR1	PSIDIV3ON	`LL_RCC_PSIDIV3_Disable()` `LL_RCC_PSIDIV3_Enable()` `LL_RCC_PSIDIV3_IsEnabled()`
CR1	PSIDIV3RDY	`LL_RCC_PSIDIV3_IsReady()`
CR1	PSIKERON	`LL_RCC_PSI_DisableInStopMode()` `LL_RCC_PSI_EnableInStopMode()` `LL_RCC_PSI_IsEnabledInStopMode()`
CR1	PSIKON	`LL_RCC_PSIK_Disable()` `LL_RCC_PSIK_Enable()` `LL_RCC_PSIK_IsEnabled()`
CR1	PSIKRDY	`LL_RCC_PSIK_IsReady()`
CR1	PSISON	`LL_RCC_PSIS_Disable()` `LL_RCC_PSIS_Enable()` `LL_RCC_PSIS_IsEnabled()`
CR1	PSISRDY	`LL_RCC_PSIS_IsReady()`
CR2	HSIKDIV	`LL_RCC_HSIK_GetDivider()` `LL_RCC_HSIK_SetDivider()`
CR2	PSIFREQ	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIFreqOutput()` `LL_RCC_SetPSIFreqOutput()`
CR2	PSIKDIV	`LL_RCC_PSIK_GetDivider()` `LL_RCC_PSIK_SetDivider()`
CR2	PSIREF	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIRef()` `LL_RCC_SetPSIRef()`
CR2	PSIREFSRC	`LL_RCC_ConfigPSI()` `LL_RCC_GetConfigPSI()` `LL_RCC_GetPSIClkSource()` `LL_RCC_SetPSIClkSource()`
RSR	BORRSTF	`LL_RCC_IsActiveFlag_BORRST()`
RSR	IWDGRSTF	`LL_RCC_IsActiveFlag_IWDGRST()`
RSR	LPWRRSTF	`LL_RCC_IsActiveFlag_LPWRRST()`
RSR	PINRSTF	`LL_RCC_IsActiveFlag_PINRST()`
RSR	RMVF	`LL_RCC_ForceClearResetFlags()` `LL_RCC_ReleaseClearResetFlags()`
RSR	SFTRSTF	`LL_RCC_IsActiveFlag_SFTRST()`
RSR	WWDGRSTF	`LL_RCC_IsActiveFlag_WWDGRST()`
RTCCR	LSCOEN	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_Disable()` `LL_RCC_LSCO_Enable()`
RTCCR	LSCOSEL	`LL_RCC_ConfigLSCO()` `LL_RCC_LSCO_GetSource()` `LL_RCC_LSCO_SetSource()`
RTCCR	LSEBYP	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_DisableBypass()` `LL_RCC_LSE_EnableBypass()` `LL_RCC_LSE_IsBypassed()`
RTCCR	LSECSSD	`LL_RCC_LSE_IsCSSDetected()`
RTCCR	LSECSSON	`LL_RCC_LSE_DisableCSS()` `LL_RCC_LSE_EnableCSS()`
RTCCR	LSEDRV	`LL_RCC_LSE_GetDriveCapability()` `LL_RCC_LSE_SetDriveCapability()`
RTCCR	LSEEXT	`LL_RCC_LSE_ConfigBypass()` `LL_RCC_LSE_GetClockMode()` `LL_RCC_LSE_SetClockMode()`
RTCCR	LSEON	`LL_RCC_LSE_Disable()` `LL_RCC_LSE_Enable()` `LL_RCC_LSE_IsEnabled()`
RTCCR	LSERDY	`LL_RCC_LSE_IsReady()`
RTCCR	LSION	`LL_RCC_LSI_Disable()` `LL_RCC_LSI_Enable()` `LL_RCC_LSI_IsEnabled()`
RTCCR	LSIRDY	`LL_RCC_LSI_IsReady()`
RTCCR	RTCDRST	`LL_RCC_ForceRTCDomainReset()` `LL_RCC_ReleaseRTCDomainReset()`
RTCCR	RTCEN	`LL_RCC_DisableRTC()` `LL_RCC_EnableRTC()` `LL_RCC_IsEnabledRTC()`
RTCCR	RTCSEL	`LL_RCC_GetRTCClockSource()` `LL_RCC_SetRTCClockSource()`