Reference Manual to LL API cross reference ¶

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for BUS registers

Register	Bit	Function
AHB1ENR	CORDICEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CRCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1CKEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1RXEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1TXEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FLASHEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	LPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	LPDMA2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	RAMCFGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1LPENR	CORDICLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	CRCLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1CKLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1RXLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1TXLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	FLASHLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ICACHELPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	LPDMA1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	LPDMA2LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	RAMCFGLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	SRAM1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	SRAM2LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1RSTR	CORDICRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	CRCRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	ETH1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	LPDMA1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	LPDMA2RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	RAMCFGRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB2ENR	ADC12EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	ADC3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	CCBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	DAC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOCEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIODEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOEEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOFEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	HASHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	PKAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	RNGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	SAESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2LPENR	ADC12LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	ADC3LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AESLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	CCBLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	DAC1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOALPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOBLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOCLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIODLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOELPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOFLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOGLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOHLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	HASHLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	PKALPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	RNGLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	SAESLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2RSTR	ADC12RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	ADC3RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	AESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	CCBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	DAC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOCRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIODRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOERST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOFRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	HASHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	PKARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	RNGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	SAESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
APB1HENR	COMP12EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1HENR	FDCANEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1HLPENR	COMP12LPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1HLPENR	FDCANLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1HRSTR	COMP12RST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1HRSTR	FDCANRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1LENR	CRSEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I3C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	OPAMP1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	SPI3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM12EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LLPENR	CRSLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I2C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I2C2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I3C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	OPAMP1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	SPI2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	SPI3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM12LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	WWDGLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LRSTR	CRSRST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I3C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	OPAMP1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	SPI3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM12RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USBEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2LPENR	SPI1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM15LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM16LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM17LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM8LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USBLPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USBRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB3ENR	LPTIM1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPUART1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	RTCAPBEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SBSEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3LPENR	LPTIM1LPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	LPUART1LPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	RTCAPBLPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	SBSLPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3RSTR	LPTIM1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPUART1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SBSRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
CFGR2	AHB1DIS	`LL_AHB1_DisableBusClock()` `LL_AHB1_EnableBusClock()` `LL_AHB1_IsEnabledBusClock()`
CFGR2	AHB2DIS	`LL_AHB2_DisableBusClock()` `LL_AHB2_EnableBusClock()` `LL_AHB2_IsEnabledBusClock()`
CFGR2	APB1DIS	`LL_APB1_DisableBusClock()` `LL_APB1_EnableBusClock()` `LL_APB1_IsEnabledBusClock()`
CFGR2	APB3DIS	`LL_APB3_DisableBusClock()` `LL_APB3_IsEnabledBusClock()`

Register	Bit	Function
AHB1ENR	CORDICEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CRCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1CKEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1RXEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1TXEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FLASHEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	LPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	LPDMA2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	RAMCFGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1LPENR	CORDICLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	CRCLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1CKLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1RXLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1TXLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	FLASHLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ICACHELPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	LPDMA1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	LPDMA2LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	RAMCFGLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	SRAM1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	SRAM2LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1RSTR	CORDICRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	CRCRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	ETH1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	LPDMA1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	LPDMA2RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	RAMCFGRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB2ENR	ADC12EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	ADC3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	CCBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	DAC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOCEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIODEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOEEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOFEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	HASHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	PKAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	RNGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	SAESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2LPENR	ADC12LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	ADC3LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AESLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	CCBLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	DAC1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOALPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOBLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOCLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIODLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOELPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOFLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOGLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOHLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	HASHLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	PKALPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	RNGLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	SAESLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2RSTR	ADC12RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	ADC3RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	AESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	CCBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	DAC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOCRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIODRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOERST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOFRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	HASHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	PKARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	RNGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	SAESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB4ENR	XSPI1EN	`LL_AHB4_GRP1_DisableClock()` `LL_AHB4_GRP1_EnableClock()` `LL_AHB4_GRP1_IsEnabledClock()`
AHB4LPENR	XSPI1LPEN	`LL_AHB4_GRP1_DisableClockLowPower()` `LL_AHB4_GRP1_EnableClockLowPower()` `LL_AHB4_GRP1_IsEnabledClockLowPower()`
AHB4RSTR	XSPI1RST	`LL_AHB4_GRP1_ForceReset()` `LL_AHB4_GRP1_ReleaseReset()`
APB1HENR	COMP12EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1HENR	FDCANEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1HLPENR	COMP12LPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1HLPENR	FDCANLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1HRSTR	COMP12RST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1HRSTR	FDCANRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1LENR	CRSEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I3C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	OPAMP1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	SPI3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM12EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LLPENR	CRSLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I2C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I2C2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I3C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	OPAMP1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	SPI2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	SPI3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM12LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	WWDGLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LRSTR	CRSRST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I3C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	OPAMP1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	SPI3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM12RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USBEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2LPENR	SPI1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM15LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM16LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM17LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM8LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USBLPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USBRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB3ENR	LPTIM1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPUART1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	RTCAPBEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SBSEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3LPENR	LPTIM1LPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	LPUART1LPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	RTCAPBLPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	SBSLPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3RSTR	LPTIM1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPUART1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SBSRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
CFGR2	AHB1DIS	`LL_AHB1_DisableBusClock()` `LL_AHB1_EnableBusClock()` `LL_AHB1_IsEnabledBusClock()`
CFGR2	AHB2DIS	`LL_AHB2_DisableBusClock()` `LL_AHB2_EnableBusClock()` `LL_AHB2_IsEnabledBusClock()`
CFGR2	AHB4DIS	`LL_AHB4_DisableBusClock()` `LL_AHB4_EnableBusClock()` `LL_AHB4_IsEnabledBusClock()`
CFGR2	APB1DIS	`LL_APB1_DisableBusClock()` `LL_APB1_EnableBusClock()` `LL_APB1_IsEnabledBusClock()`
CFGR2	APB3DIS	`LL_APB3_DisableBusClock()` `LL_APB3_IsEnabledBusClock()`

Register	Bit	Function
AHB1ENR	CORDICEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	CRCEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1CKEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1RXEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	ETH1TXEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	FLASHEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	LPDMA1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	LPDMA2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	RAMCFGEN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM1EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1ENR	SRAM2EN	`LL_AHB1_GRP1_DisableClock()` `LL_AHB1_GRP1_EnableClock()` `LL_AHB1_GRP1_IsEnabledClock()`
AHB1LPENR	CORDICLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	CRCLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1CKLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1RXLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ETH1TXLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	FLASHLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	ICACHELPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	LPDMA1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	LPDMA2LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	RAMCFGLPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	SRAM1LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1LPENR	SRAM2LPEN	`LL_AHB1_GRP1_DisableClockLowPower()` `LL_AHB1_GRP1_EnableClockLowPower()` `LL_AHB1_GRP1_IsEnabledClockLowPower()`
AHB1RSTR	CORDICRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	CRCRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	ETH1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	LPDMA1RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	LPDMA2RST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB1RSTR	RAMCFGRST	`LL_AHB1_GRP1_ForceReset()` `LL_AHB1_GRP1_ReleaseReset()`
AHB2ENR	ADC12EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	ADC3EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	AESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	CCBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	DAC1EN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOBEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOCEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIODEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOEEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOFEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	GPIOHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	HASHEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	PKAEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	RNGEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2ENR	SAESEN	`LL_AHB2_GRP1_DisableClock()` `LL_AHB2_GRP1_EnableClock()` `LL_AHB2_GRP1_IsEnabledClock()`
AHB2LPENR	ADC12LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	ADC3LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	AESLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	CCBLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	DAC1LPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOALPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOBLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOCLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIODLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOELPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOFLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOGLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	GPIOHLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	HASHLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	PKALPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	RNGLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2LPENR	SAESLPEN	`LL_AHB2_GRP1_DisableClockLowPower()` `LL_AHB2_GRP1_EnableClockLowPower()` `LL_AHB2_GRP1_IsEnabledClockLowPower()`
AHB2RSTR	ADC12RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	ADC3RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	AESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	CCBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	DAC1RST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOBRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOCRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIODRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOERST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOFRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	GPIOHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	HASHRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	PKARST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	RNGRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
AHB2RSTR	SAESRST	`LL_AHB2_GRP1_ForceReset()` `LL_AHB2_GRP1_ReleaseReset()`
APB1HENR	COMP12EN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1HENR	FDCANEN	`LL_APB1_GRP2_DisableClock()` `LL_APB1_GRP2_EnableClock()` `LL_APB1_GRP2_IsEnabledClock()`
APB1HLPENR	COMP12LPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1HLPENR	FDCANLPEN	`LL_APB1_GRP2_DisableClockLowPower()` `LL_APB1_GRP2_EnableClockLowPower()` `LL_APB1_GRP2_IsEnabledClockLowPower()`
APB1HRSTR	COMP12RST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1HRSTR	FDCANRST	`LL_APB1_GRP2_ForceReset()` `LL_APB1_GRP2_ReleaseReset()`
APB1LENR	CRSEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I2C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I2C2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	I3C1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	OPAMP1EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	SPI2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	SPI3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM12EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	TIM7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART4EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART5EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	UART7EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART2EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART3EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	USART6EN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LENR	WWDGEN	`LL_APB1_GRP1_DisableClock()` `LL_APB1_GRP1_EnableClock()` `LL_APB1_GRP1_IsEnabledClock()`
APB1LLPENR	CRSLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I2C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I2C2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	I3C1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	OPAMP1LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	SPI2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	SPI3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM12LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	TIM7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART4LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART5LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	UART7LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART2LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART3LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	USART6LPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LLPENR	WWDGLPEN	`LL_APB1_GRP1_DisableClockLowPower()` `LL_APB1_GRP1_EnableClockLowPower()` `LL_APB1_GRP1_IsEnabledClockLowPower()`
APB1LRSTR	CRSRST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I2C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I2C2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	I3C1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	OPAMP1RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	SPI2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	SPI3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM12RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	TIM7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART4RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART5RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	UART7RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART2RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART3RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB1LRSTR	USART6RST	`LL_APB1_GRP1_ForceReset()` `LL_APB1_GRP1_ReleaseReset()`
APB2ENR	SPI1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM15EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM16EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM17EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	TIM8EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USART1EN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2ENR	USBEN	`LL_APB2_GRP1_DisableClock()` `LL_APB2_GRP1_EnableClock()` `LL_APB2_GRP1_IsEnabledClock()`
APB2LPENR	SPI1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM15LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM16LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM17LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	TIM8LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USART1LPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2LPENR	USBLPEN	`LL_APB2_GRP1_DisableClockLowPower()` `LL_APB2_GRP1_EnableClockLowPower()` `LL_APB2_GRP1_IsEnabledClockLowPower()`
APB2RSTR	SPI1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM15RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM16RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM17RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	TIM8RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USART1RST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB2RSTR	USBRST	`LL_APB2_GRP1_ForceReset()` `LL_APB2_GRP1_ReleaseReset()`
APB3ENR	LPTIM1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	LPUART1EN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	RTCAPBEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3ENR	SBSEN	`LL_APB3_GRP1_DisableClock()` `LL_APB3_GRP1_EnableClock()` `LL_APB3_GRP1_IsEnabledClock()`
APB3LPENR	LPTIM1LPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	LPUART1LPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	RTCAPBLPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3LPENR	SBSLPEN	`LL_APB3_GRP1_DisableClockLowPower()` `LL_APB3_GRP1_EnableClockLowPower()` `LL_APB3_GRP1_IsEnabledClockLowPower()`
APB3RSTR	LPTIM1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	LPUART1RST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
APB3RSTR	SBSRST	`LL_APB3_GRP1_ForceReset()` `LL_APB3_GRP1_ReleaseReset()`
CFGR2	AHB1DIS	`LL_AHB1_DisableBusClock()` `LL_AHB1_EnableBusClock()` `LL_AHB1_IsEnabledBusClock()`
CFGR2	AHB2DIS	`LL_AHB2_DisableBusClock()` `LL_AHB2_EnableBusClock()` `LL_AHB2_IsEnabledBusClock()`
CFGR2	APB1DIS	`LL_APB1_DisableBusClock()` `LL_APB1_EnableBusClock()` `LL_APB1_IsEnabledBusClock()`
CFGR2	APB3DIS	`LL_APB3_DisableBusClock()` `LL_APB3_IsEnabledBusClock()`