Reference Manual to LL API cross reference

The following table provides the mapping between the registers and bits, as they appear inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correlation for FLASH registers

Register

Bit

Function

ACR

EMPTY

ACR

LATENCY

ACR

PRFTEN

ACR

WRHIGHFREQ

BL_COM_CFGR

BL_COM_CFG

BOOTR

BOOT_LOCK

BOOTR_CUR

BOOTADD

BOOTR_PRG

BOOTADD

BSKEYR

BSKEY

CCR

CLR_EOP

CCR

CLR_INCERR

CCR

CLR_OPTCHANGEERR

CCR

CLR_PGSERR

CCR

CLR_STRBERR

CCR

CLR_WRPERR

CR

BER/STRT

CR

BKER/EDATASEL/PNB/PER/STRT

CR

BKSEL/BER

CR

BKSEL/EDATASEL/PNB

CR

BKSEL/STRT/BER

CR

EOPIE

CR

EOPIE/WRPERRIE/PGSERRIE/STRBERRIE/INCERRIE/OPTCHANGEERRIE

CR

FW

CR

INCERRIE

CR

LOCK

CR

MER

CR

OPTCHANGEERRIE

CR

PER

CR

PG

CR

PGSERRIE

CR

STRBERRIE

CR

STRT

CR

WRPERRIE

ECCCORR

ADDR_ECC

ECCCORR

BK_ECC

ECCCORR

ECCC

ECCCORR

ECCCIE

ECCCORR

EDATA_ECC

ECCCORR

EDATA_ECC|BK_ECC/SYSF_ECC|OTP_ECC

ECCCORR

OTP_ECC

ECCCORR

SYSF_ECC

ECCDETR

ADDR_ECC

ECCDETR

BK_ECC

ECCDETR

ECCD

ECCDETR

EDATA_ECC

ECCDETR

EDATA_ECC|BK_ECC/SYSF_ECC|OTP_ECC

ECCDETR

OTP_ECC

ECCDETR

SYSF_ECC

ECCDR

DATA_ADDR_ECC

ECCDR

DATA_ECC

HDP1R_CUR/HDP2R_CUR

HDP1R_END/HDP2R_END

HDP1R_CUR/HDP2R_CUR

HDP1R_STRT/HDP2R_STRT

HDP1R_PRG/HDP2R_PRG

HDP1R_END/HDP2R_END

HDP1R_PRG/HDP2R_PRG

HDP1R_END|HDP1R_STRT/HDP2R_END|HDP2R_STRT

HDP1R_PRG/HDP2R_PRG

HDP1R_STRT/HDP2R_STRT

HDPEXTR

HDP1_EXT/HDP2_EXT

KEYR

KEY/SECKEY

NSCR/SECCR

PG/PER/MER1/MER2

OEMKEYR1

OEMKEY

OEMKEYR2

OEMKEY

OEMKEYR3

OEMKEY

OEMKEYR4

OEMKEY

OPSR

ADDR_OP

OPSR

BK_OP

OPSR

CODE_OP

OPSR

DATA_OP

OPSR

DATA_OP|BK_OP|OTP_OP

OPSR

OTP_OP

OPSR_PRG

RDP_LEVEL

OPTCR

OPTLOCK

OPTCR

OPTSTRT

OPTCR

SWAP_BANK

OPTKEYR

OPTKEY

OPTSR

IWDG_SW

OPTSR2_CUR

SRAM1_RST

OPTSR2_CUR

SRAM2_ECC

OPTSR2_CUR

SRAM2_RST

OPTSR2_PRG

SRAM1_RST

OPTSR2_PRG

SRAM2_ECC

OPTSR2_PRG

SRAM2_RST

OPTSR_CUR

BOOT0

OPTSR_CUR

BOOT_SEL

OPTSR_CUR

BOOT_SEL|BOOT0

OPTSR_CUR

EDATA_EN

OPTSR_CUR

IWDG_STDBY

OPTSR_CUR

IWDG_STOP

OPTSR_CUR

NRST_STDBY

OPTSR_CUR

NRST_STOP

OPTSR_CUR

SINGLE_BANK

OPTSR_CUR

SWAP_BANK

OPTSR_CUR

WWDG_SW

OPTSR_PGR

RDP_LEVEL

OPTSR_PRG

BOOT0

OPTSR_PRG

BOOT_SEL

OPTSR_PRG

BOOT_SEL|BOOT0

OPTSR_PRG

EDATA_EN

OPTSR_PRG

IWDG_STDBY

OPTSR_PRG

IWDG_STOP

OPTSR_PRG

NRST_STDBY

OPTSR_PRG

NRST_STOP

OPTSR_PRG

SINGLE_BANK

OPTSR_PRG

SWAP_BANK

OPTSR_PRG

WWDG_SW

OTPBLR_CUR

LOCKBL

OTPBLR_PRG

LOCKBL

PRIVCFGR

PRIV

SECBOOTR

BOOT_LOCK

SR

BSLOCK

SR

BSY

SR

BSY|WBNE|DBNE

SR

DBNE

SR

EOP

SR

EOP/WRPERR/PGSERR/STRBERR/INCERR/OPTCHANGEERR

SR

INCERR

SR

OEMLOCK

SR

OPTCHANGEERR

SR

PGSERR

SR

STRBERR

SR

WBNE

SR

WRPERR

WRP1R/WRP2R

WRP1R_WRPSG/WRP2R_WRPSG

WRP1R_PRG/WRP2R_PRG

WRP1R_WRPSG/WRP2R_WRPSG